On Sun, 1 Nov 2020 at 08:20, Jernej Skrabec wrote:
>
> RX/TX delay on OrangePi One Plus board is set on PHY. Reflect that in
> ethernet node.
>
> Fixes: 7ee32a17e0d6 ("arm64: dts: allwinner: h6: orangepi-one-plus: Enable
> ethernet")
> Signed-off-by: Jernej Skrabec
Hi Jernej,
Tested-by: Marcus
Good catchSPI2 is also wrong they should be
spi2: spi@1c17000 and spi3: spi@1c1f000
CK
On Tue, 10 Mar 2020 at 13:08, JuanEsf wrote:
>
> Hello along with greeting, I wish you good morning.
> In kernel 5.6-rc5 the SPI nodes in R40 SoC have been added,
> But the SPI3 node in mainline
>
On Wed, 16 Oct 2019 at 10:04, Maxime Ripard wrote:
>
> On Wed, Oct 16, 2019 at 09:07:34AM +0200, codekip...@gmail.com wrote:
> > From: Marcus Cooper
> >
> > On the newer SoCs the offset is used to set the mode of the
> > connection. As it is to be used elsewhere then it makes sense
> > to move
On Wed, 16 Oct 2019 at 10:06, Maxime Ripard wrote:
>
> Hi,
>
> On Wed, Oct 16, 2019 at 09:07:35AM +0200, codekip...@gmail.com wrote:
> > From: Marcus Cooper
> >
> > Newer SoCs like the H6 have the channel offset bits in a different
> > position to what is on the H3. As we will eventually add
On Fri, 30 Aug 2019 at 13:45, Mark Brown wrote:
>
> On Wed, Aug 21, 2019 at 06:23:20PM +0200, codekip...@gmail.com wrote:
> > From: Marcus Cooper
> >
> > Fixes: 21faaea1343f ("ASoC: sun4i-i2s: Add support for A83T")
> > Signed-off-by: Marcus Cooper
> > ---
>
> This doesn't apply against current
On Tue, 27 Aug 2019 at 11:34, Maxime Ripard wrote:
>
> On Mon, Aug 26, 2019 at 08:07:33PM +0200, codekip...@gmail.com wrote:
> > From: Marcus Cooper
> >
> > On the newer SoCs such as the H3 and A64 this is set by default
> > to transfer a 0 after each sample in each slot. However the A10
> > and
On Tue, 27 Aug 2019 at 09:01, Maxime Ripard wrote:
>
> On Mon, Aug 26, 2019 at 08:07:34PM +0200, codekip...@gmail.com wrote:
> > From: Marcus Cooper
> >
> > Some codecs such as i2s based HDMI audio and the Pine64 DAC require
> > a different amount of bit clocks per frame than what is calculated
On Tue, 27 Aug 2019 at 10:01, Chen-Yu Tsai wrote:
>
> On Tue, Aug 27, 2019 at 1:55 PM Code Kipper wrote:
> >
> > On Tue, 27 Aug 2019 at 06:13, Chen-Yu Tsai wrote:
> > >
> > > On Tue, Aug 27, 2019 at 2:07 AM wrote:
> > > >
> > > > F
On Tue, 27 Aug 2019 at 06:13, Chen-Yu Tsai wrote:
>
> On Tue, Aug 27, 2019 at 2:07 AM wrote:
> >
> > From: Marcus Cooper
> >
> > The regmap configuration is set up for the legacy block on the
> > A83T whereas it uses the new block with a larger register map.
>
> Looking at the code Allwinner
On Wed, 14 Aug 2019 at 08:09, wrote:
>
> From: Jernej Skrabec
>
> I2S doesn't work if parent rate couldn't be change. Difference between
> wanted and actual rate is too big.
>
> Fix this by adding CLK_SET_RATE_PARENT flag to I2S clocks.
>
> Signed-off-by: Jernej Skrabec
Signed-off-by: Marcus
ThanksI've added to my next patch series but if you could add it
when applying that would be great.
BR,
CK
On Wed, 21 Aug 2019 at 06:07, Chen-Yu Tsai wrote:
>
> On Wed, Aug 14, 2019 at 2:09 PM wrote:
> >
> > From: Jernej Skrabec
> >
> > I2S doesn't work if parent rate couldn't be change.
On Wed, 14 Aug 2019 at 13:08, Maxime Ripard wrote:
>
> Hi,
>
> On Wed, Aug 14, 2019 at 08:08:41AM +0200, codekip...@gmail.com wrote:
> > From: Marcus Cooper
> >
> > Codecs without a control connection such as i2s based HDMI audio and
> > the Pine64 DAC require a different amount of bit clocks
On Wed, 14 Aug 2019 at 11:30, Mark Brown wrote:
>
> On Wed, Aug 14, 2019 at 08:08:41AM +0200, codekip...@gmail.com wrote:
> > From: Marcus Cooper
> >
> > Codecs without a control connection such as i2s based HDMI audio and
> > the Pine64 DAC require a different amount of bit clocks per frame
On Wed, 14 Aug 2019 at 13:08, Maxime Ripard wrote:
>
> Hi,
>
> On Wed, Aug 14, 2019 at 08:08:40AM +0200, codekip...@gmail.com wrote:
> > From: Marcus Cooper
> >
> > On the newer SoCs such as the H3 and A64 this is set by default
> > to transfer a 0 after each sample in each slot. However the A10
On Wed, 14 Aug 2019 at 13:08, Maxime Ripard wrote:
>
> On Wed, Aug 14, 2019 at 08:08:43AM +0200, codekip...@gmail.com wrote:
> > From: Marcus Cooper
> >
> > There is a need to support more formats on the newer SoCs(H3 and later).
> > Extend the formats supported to include DSP_A and DSP_B modes.
On Wed, 14 Aug 2019 at 13:08, Maxime Ripard wrote:
>
> On Wed, Aug 14, 2019 at 08:08:51AM +0200, codekip...@gmail.com wrote:
> > From: Marcus Cooper
> >
> > The i2s block supports multi-lane i2s output however this functionality
> > is only possible in earlier SoCs where the pins are exposed and
On Wed, 14 Aug 2019 at 09:57, Jernej Škrabec wrote:
>
> Hi!
>
> Dne sreda, 14. avgust 2019 ob 08:08:50 CEST je codekip...@gmail.com
> napisal(a):
> > From: Jernej Skrabec
> >
> > H6 I2S is very similar to that in H3, except it supports up to 16
> > channels.
> >
> > Signed-off-by: Jernej Skrabec
On Wed, 14 Aug 2019 at 10:38, Jernej Škrabec wrote:
>
> Hi!
>
> Dne sreda, 14. avgust 2019 ob 08:08:54 CEST je codekip...@gmail.com
> napisal(a):
> > From: Marcus Cooper
> >
> > Bypass the regmap cache when flushing the i2s FIFOs and modify the tables
> > to reflect this.
> >
> > Signed-off-by:
On Wed, 14 Aug 2019 at 10:28, Jernej Škrabec wrote:
>
> Hi!
>
> Dne sreda, 14. avgust 2019 ob 08:08:53 CEST je codekip...@gmail.com
> napisal(a):
> > From: Marcus Cooper
> >
> > Extend the functionality of the driver to include support of 20 and
> > 24 bits per sample for the earlier SoCs.
> >
>
On Tue, 6 Aug 2019 at 17:57, wrote:
>
> From: Ondrej Jirman
>
> Orange Pi 3 has a DDC_CEC_EN signal connected to PH2, that enables the DDC
> I2C bus voltage shifter. Before EDID can be read, we need to pull PH2 high.
> This is realized by the ddc-en-gpios property.
Great work. Is there any
On Tue, 4 Jun 2019 at 09:53, Chen-Yu Tsai wrote:
>
> On Tue, Jun 4, 2019 at 1:47 AM wrote:
> >
> > From: Marcus Cooper
> >
> > On the newer SoCs this is set by default to transfer a 0 after
> > each sample in each slot. However the platform that this driver
> > was developed on had the default
On Tue, 4 Jun 2019 at 11:02, Christopher Obbard wrote:
>
> On Tue, 4 Jun 2019 at 09:43, Code Kipper wrote:
> >
> > On Tue, 4 Jun 2019 at 09:58, Maxime Ripard
> > wrote:
> > >
> > > On Mon, Jun 03, 2019 at 07:47:32PM +0200, codekip...@gm
On Tue, 4 Jun 2019 at 09:46, Maxime Ripard wrote:
>
> On Mon, Jun 03, 2019 at 07:47:30PM +0200, codekip...@gmail.com wrote:
> > From: Marcus Cooper
> >
> > We have a number of flags used to identify the functionality
> > of the IP block found on the sun8i-h3 and later devices. As it
> > is only
On Tue, 4 Jun 2019 at 09:58, Maxime Ripard wrote:
>
> On Mon, Jun 03, 2019 at 07:47:32PM +0200, codekip...@gmail.com wrote:
> > From: Marcus Cooper
> >
> > The i2s block supports multi-lane i2s output however this functionality
> > is only possible in earlier SoCs where the pins are exposed and
On Tue, 4 Jun 2019 at 09:39, Chen-Yu Tsai wrote:
>
> On Tue, Jun 4, 2019 at 3:34 PM Maxime Ripard
> wrote:
> >
> > On Mon, Jun 03, 2019 at 07:47:27PM +0200, codekip...@gmail.com wrote:
> > > From: Marcus Cooper
> > >
> > > Although not causing any noticeable issues, the mask for the
> > >
On Wed, 29 May 2019 at 14:01, Jagan Teki wrote:
>
> On Wed, May 29, 2019 at 5:25 PM wrote:
> >
> > From: Marcus Cooper
> >
> > The Beelink X2 is an STB based on the Allwinner H3 SoC with a uSD slot,
> > 2 USB ports( 1 * USB-2 Host, 1 USB OTG), a 10/100M ethernet port using the
> > SoC's
On Wed, 29 May 2019 at 13:55, wrote:
>
> From: Marcus Cooper
>
> The Beelink X2 is an STB based on the Allwinner H3 SoC with a uSD slot,
> 2 USB ports( 1 * USB-2 Host, 1 USB OTG), a 10/100M ethernet port using the
> SoC's integrated PHY, Wifi via an sdio wifi chip, HDMI, an IR receiver, a
> dual
On Mon, 27 May 2019 at 09:30, Clément Péron wrote:
>
> Hi Marcus,
>
> On Sun, 26 May 2019 at 16:57, wrote:
> >
> > From: Marcus Cooper
> >
> > The Beelink X2 is an STB based on the Allwinner H3 SoC with a uSD slot,
> > 2 USB ports( 1 * USB-2 Host, 1 USB OTG), a 10/100M ethernet port using the
>
On Sun, 26 May 2019 at 14:13, Jernej Škrabec wrote:
>
> Hi!
>
> Dne nedelja, 26. maj 2019 ob 08:28:41 CEST je codekip...@gmail.com napisal(a):
> > From: Marcus Cooper
> >
> > The Beelink X2 is an STB based on the Allwinner H3 SoC with a uSD slot,
> > 2 USB ports( 1 * USB-2 Host, 1 USB OTG), a
On Sun, 26 May 2019 at 08:42, Jernej Škrabec wrote:
>
> Hi!
>
> Dne nedelja, 26. maj 2019 ob 08:28:41 CEST je codekip...@gmail.com napisal(a):
> > From: Marcus Cooper
> >
> > The Beelink X2 is an STB based on the Allwinner H3 SoC with a uSD slot,
> > 2 USB ports( 1 * USB-2 Host, 1 USB OTG), a
On Sun, 13 Jan 2019 at 18:42, @lex wrote:
>
> Hmm, i thought you would know about the wrong size, or where to look for.
> The patches are maybe from Icenowy, Jagan and some others, maybe they can
> give some directions.
> I have seen a showcase of Pine64SO with sound working but have yet to see
On Sun, 13 Jan 2019 at 13:35, @lex wrote:
>
> Hi Marcus,
> Thank you for the input.
>
> The patch seems to be verbatim.
> The message is clear about the size mismatch, but where it should be fixed?
>
> #thermal-sensor-cells = <2>; <= this gives the warning about the wronng size
>
> The bootlog
s
s
On Sat, 12 Jan 2019 at 20:33, @lex wrote:
>
> I've tried to apply this patch in a hope to get the thermal sensor working
> but things got hairy, can anyone please explain what is wrong with this patch:
> https://patchwork.kernel.org/patch/10555615/
Hi Alex,
check the patch after applying
: Remove support for Exynos4212 SoCs in
Exynos CLKOUT driver
7c4f63ec94a1 clk: sunxi-ng: a83t: Fix invalid csi-mclk mux offset
WORKS
0a4e632b6f9d Merge branch 'clk-fixes' into clk-next
BR,
CK
On 22 May 2018 at 21:27, Code Kipper <codekip...@gmail.com> wrote:
> Hi Markus,
> I'
Hi Markus,
I've been able to reproduce this on my A31 board with linux-next(plays
at 44100 but not at 96K)so it is an issue. I also tested the same code
on my A64 and it worked fine, The blocks are very similar so it maybe
a clocking issue, I'll look into this.
BR,
CK
On 21 May 2018 at 20:17,
On 20 May 2018 at 14:23, 'Markus Mitsch' via linux-sunxi
wrote:
> Hello,
>
> i have a new problem. if i want to output sound from optical i get
> distorted sound. At 44.1 khz its like an old vinly, but at 48 khz and
> higher it is very bad. thanks in advance for your
On 13 March 2018 at 09:23, Maxime Ripard <maxime.rip...@bootlin.com> wrote:
> On Tue, Mar 13, 2018 at 09:15:49AM +0100, Code Kipper wrote:
>> On 13 March 2018 at 09:00, Maxime Ripard <maxime.rip...@bootlin.com> wrote:
>> > On Mon, Mar 12, 2018 at 04:57:51PM +01
On 13 March 2018 at 09:00, Maxime Ripard wrote:
> On Mon, Mar 12, 2018 at 04:57:51PM +0100, codekip...@gmail.com wrote:
>> From: Marcus Cooper
>>
>> The i2s block supports multi-lane i2s output however this functionality
>> is only possible in
On 31 January 2018 at 16:34, Maxime Ripard
wrote:
> On Tue, Jan 30, 2018 at 08:50:54AM +0100, codekip...@gmail.com wrote:
>> From: Marcus Cooper
>>
>> Enable the display pipeline and HDMI output on the Olimex
>> A20-SOM-EVB.
>>
>>
On 31 January 2018 at 16:32, Maxime Ripard
wrote:
> On Tue, Jan 30, 2018 at 07:33:27PM +0100, codekip...@gmail.com wrote:
>> From: Marcus Cooper
>>
>> The Mele I7 has an HDMI connector wired to the HDMI pins
>> on the SoC. Enable the
On 31 January 2018 at 08:16, maxime ripard
wrote:
> On Mon, Jan 29, 2018 at 11:35:27AM +0100, Jernej Škrabec wrote:
>> Hi Maxime,
>>
>> (previously I respond only to linux-sunxi mailing list)
>>
>> >On Mon, Jan 29, 2018 at 10:22:23AM +0100, codekip...@gmail.com
On 29 January 2018 at 12:32, Mark Brown <broo...@kernel.org> wrote:
> On Mon, Jan 29, 2018 at 08:34:00AM +0100, Code Kipper wrote:
>
>> I'm not sure..I was looking for a clean example of being able to
>> override the number of bclks in the lrclk width and some other
&g
On 29 January 2018 at 10:35, Jernej Skrabec wrote:
> Hi,
>
> Dne ponedeljek, 29. januar 2018 10.22.27 UTC+1 je oseba CodeKipper napisala:
>>
>> From: Marcus Cooper
>>
>> Add the new DAI block for I2S2 which is used for HDMI audio.
>>
>>
On 29 January 2018 at 08:38, Chen-Yu Tsai <w...@csie.org> wrote:
> On Mon, Jan 29, 2018 at 3:34 PM, Code Kipper <codekip...@gmail.com> wrote:
>> On 29 January 2018 at 02:50, Chen-Yu Tsai <w...@csie.org> wrote:
>>> On Wed, Jan 24, 2018 at 10:10 PM, <codekip
On 29 January 2018 at 02:50, Chen-Yu Tsai wrote:
> On Wed, Jan 24, 2018 at 10:10 PM, wrote:
>> From: Marcus Cooper
>>
>> Some codecs require a different amount of a bit clocks per frame than
>> what is calculated by the sample width.
On 25 January 2018 at 09:29, Maxime Ripard
<maxime.rip...@free-electrons.com> wrote:
> On Wed, Jan 24, 2018 at 12:39:31PM +0100, Code Kipper wrote:
>> On 24 January 2018 at 12:02, Maxime Ripard
>> <maxime.rip...@free-electrons.com> wrote:
>> > Hi,
>> >
On 25 January 2018 at 09:29, Maxime Ripard
<maxime.rip...@free-electrons.com> wrote:
> On Wed, Jan 24, 2018 at 12:39:31PM +0100, Code Kipper wrote:
>> On 24 January 2018 at 12:02, Maxime Ripard
>> <maxime.rip...@free-electrons.com> wrote:
>> > Hi,
>> >
On 25 January 2018 at 09:41, Maxime Ripard
wrote:
> Hi,
>
> On Wed, Jan 24, 2018 at 03:11:01PM +0100, codekip...@gmail.com wrote:
>> From: Marcus Cooper
>>
>> On the newer SoCs this is set by default to transfer a 0 after
>> each sample in
On 24 January 2018 at 18:18, Phil wrote:
> Hi CodeKipper,
>
> I know that this thread is old but I'll take a chance.
>
> I have an old VidOn Box that is collecting dust in my closet.
>
> I want to use it again and install linux and wipe completely Android.
>
> I was
On 24 January 2018 at 15:11, wrote:
> From: Marcus Cooper
>
> On the newer SoCs this is set by default to transfer a 0 after
> each sample in each slot. Add the regmap field to configure this
> and set it so that it pads the sample with 0s.
>
>
On 24 January 2018 at 11:39, wrote:
> From: Marcus Cooper
>
NACK.just noticed the lack of commit message...
BR,
CK
> ---
> arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts | 7 +++
> 1 file changed, 7 insertions(+)
>
> diff --git
On 24 January 2018 at 12:02, Chen-Yu Tsai wrote:
> On Wed, Jan 24, 2018 at 7:00 PM, Maxime Ripard
> wrote:
>> On Wed, Jan 24, 2018 at 11:39:40AM +0100, codekip...@gmail.com wrote:
>>> From: Marcus Cooper
>>>
>>> Add the
On 24 January 2018 at 12:01, Maxime Ripard
wrote:
> On Wed, Jan 24, 2018 at 11:39:41AM +0100, codekip...@gmail.com wrote:
>> From: Marcus Cooper
>>
>> Add the device tree sound bindings for the S/PDIF block.
>>
>> Signed-off-by: Marcus
On 24 January 2018 at 12:02, Maxime Ripard
wrote:
> Hi,
>
> On Wed, Jan 24, 2018 at 11:39:43AM +0100, codekip...@gmail.com wrote:
>> From: Marcus Cooper
>>
>> Add the DAI blocks to the device tree. I2S0 and I2S1 are for
>> connecting to an
On 22 January 2018 at 09:04, Maxime Ripard
wrote:
> Hi,
>
> On Sun, Jan 21, 2018 at 07:06:49PM +0100, codekip...@gmail.com wrote:
>> From: Marcus Cooper
>>
>> The Beelink X2 is an STB based on the Allwinner H3 SoC with a uSD slot,
>> 2 USB
On 16 January 2018 at 09:00, Kai wrote:
> I found I've tried not very long ago, but the obstacle was that I could not
> compile it successfully.
> "make dtbs" did not generate any *.dtb file (seems it builds related tools
> like dtc),
> while,
> "dtc -I dts -O dtb xxx" warned
On 11 January 2018 at 03:34, Kai wrote:
> Cubieboard2 exposes SPDIF interface on GPIO (pin 64 regarding to the
> diagram).
> On a legacy kernel, to enable it, script.fex is used, however mainline
> kernel uses dts.
> Both using A20, cubietruck exported SPDIF by default, but I
On 16 December 2017 at 02:03, Matt Flax <flat...@flatmax.org> wrote:
>
>
> On 16/12/17 06:47, Code Kipper wrote:
>>
>> On 15 December 2017 at 20:05, Chris Obbard <obba...@gmail.com> wrote:
>>>
>>> Thanks Chen-Yu, that patch was literally what I wa
ze range from 64 to 16384
>> >> Using max buffer size 131072
>> >> Periods = 4
>> >> Unable to set hw params for playback: Invalid argument
>> >> Setting of hwparams failed: Invalid argument
>> >
>> >
>> > Will start delvin
DBVDD not found, using dummy
>> regulator
>> [8.051789] sun4i-i2s 1c22000.i2s: Could not register PCM
>> [8.059306] sun4i-codec 1c22c00.codec: Failed to register against
>> DMAEngine
>> [8.697652] sun4i-i2s 1c22000.i2s: Could not register PCM
>> [8.
plugging the Pi HAT in, but it never seems to be as
> simple as that :-).
>
>
> Will keep you updated with progress.
>
> Cheers!
>
>
> On 11 December 2017 at 13:16, Code Kipper <codekip...@gmail.com> wrote:
>>
>> Hi Chris.
>> H5 support went in with the H3 so
Hi Chris.
H5 support went in with the H3 so it should work. You will need to
make dts changes or overlays for the devices that you're using.
CK
On 11 December 2017 at 12:41, Chris Obbard wrote:
> Hey
>
> I am looking into the H5 i2s mainline support, can anyone update me on
On 3 September 2017 at 18:35, Jernej Škrabec wrote:
> Hi Marcus!
>
> Dne nedelja, 03. september 2017 ob 17:08:06 CEST je codekip...@gmail.com
> napisal(a):
>> From: Marcus Cooper
>>
>> Add the new DAI blocks to the device tree. I2S0 and I2S1 are for
On 3 September 2017 at 17:08, wrote:
> From: Marcus Cooper
>
> Add the new DAI blocks to the device tree.
>
> Signed-off-by: Marcus Cooper
Hi all,
I haven't got a dev board for this SoC but was able to confirm that
this worked
On 31 August 2017 at 16:52, Maxime Ripard
wrote:
> On Thu, Aug 31, 2017 at 01:36:09AM +0200, Stefan Brüns wrote:
>> The A64 SoC has the same dma engine as the H3 (sun8i), with a
>> reduced amount of physical channels. Add the proper config data
>> and compatible
On 31 August 2017 at 13:50, Code Kipper <codekip...@gmail.com> wrote:
> Hi Mark,
>
> Wens has given this patch series his blessing so it's good to go.
>
> Let us know if you need me to resubmit,
I take that back as I can see that's all been submitted.
Thanks,
CK
>
> B
Hi Mark,
Wens has given this patch series his blessing so it's good to go.
Let us know if you need me to resubmit,
BR,
CK
On 19 August 2017 at 14:48, wrote:
> From: Marcus Cooper
>
> Hi All,
> please find attached a series of patches to bring i2s
On 31 August 2017 at 01:36, Stefan Brüns wrote:
> The A64 SoC has the same dma engine as the H3 (sun8i), with a
> reduced amount of physical channels. Add the proper config data
> and compatible string to support it.
>
> Signed-off-by: Stefan Brüns
On 25 August 2017 at 12:32, Antony Antony wrote:
> Add initial DT support for NanoPi NEO Plus 2 by FriendlyELEC
> Allwinner quad core H5 Cortex A53 with an ARM Mali-450MP GPU
> 1 GB DDR3 RAM
> 8GB eMMC flash (Samsung
On 12 August 2017 at 14:27, Chen-Yu Tsai wrote:
> On Sat, Aug 12, 2017 at 7:00 PM, wrote:
>> From: Marcus Cooper
>>
>> The sun8i-h3 introduces a lot of changes to the i2s block such
>> as different register locations, extended clock
On 1 August 2017 at 10:31, Chen-Yu Tsai wrote:
> On Sat, Jul 29, 2017 at 10:17 PM, wrote:
>> From: Marcus Cooper
>>
>> On the original i2s block the channel mapping and selection were
>> configured for stereo audio by default: This is
On 1 August 2017 at 04:55, Chen-Yu Tsai wrote:
> On Sat, Jul 29, 2017 at 10:17 PM, wrote:
>> From: Marcus Cooper
>>
>> The BCLKDIV and MCLKDIV found on newer SoCs start from an offset of 1.
>> Add the functionality to adjust the
On 31 July 2017 at 09:05, Olliver Schinagl wrote:
> Hey Marcus,
>
> On 29-07-17 16:17, codekip...@gmail.com wrote:
>>
>> From: Marcus Cooper
>>
>> Hi All,
>> please find attached a series of patches to bring i2s support to the
>> Allwinner H3 SoC.
On 25 July 2017 at 16:36, Maxime Ripard
wrote:
> Hi,
>
> On Sat, Jul 22, 2017 at 08:53:52AM +0200, codekip...@gmail.com wrote:
>> From: Marcus Cooper
>>
>> The sun8i-h3 introduces a lot of changes to the i2s block such
>> as different
On 25 July 2017 at 07:52, Maxime Ripard
wrote:
> Hi Markus,
>
> On Sat, Jul 22, 2017 at 08:53:51AM +0200, codekip...@gmail.com wrote:
>> From: Marcus Cooper
>>
>> In preparation for changing this driver to support newer SoC
>>
No...I've only got an Olimex SOM EVB which exposes these pins on a
GPIO header (like many of the dev boards). Just thought if we included
them in the dtsi then adding overlays for i2s devices would be
simplified.
BR,
CK
On 24 July 2017 at 10:20, Maxime Ripard
On 5 July 2017 at 18:20, Maxime Ripard wrote:
> On Wed, Jul 05, 2017 at 05:43:24PM +0200, codekip...@gmail.com wrote:
>> From: Marcus Cooper
>>
>> There are a lot of changes to the sun8i-h3 i2s block but not enough
>> to warrant to a new
On 22 May 2017 at 08:25, Chen-Yu Tsai wrote:
> The A83T SoC has a DMA controller that supports 8 DMA channels
> to and from various peripherals.
>
> Add a device node for it.
>
> Signed-off-by: Chen-Yu Tsai
> ---
> arch/arm/boot/dts/sun8i-a83t.dtsi | 9 +
>
On 21 April 2017 at 16:51, Maxime Ripard
wrote:
> On Fri, Apr 21, 2017 at 05:35:40PM +0300, Hazar Karabay wrote:
>> 2017-04-21 10:35 GMT+03:00 Maxime Ripard :
>> > Wait, what are you calling MCLK?
>>
>> Master clock, is it wrong?
I can also confirm this on an A20 with HDMI.
Much appreciated,
CK
On 21 March 2017 at 01:02, Icenowy Zheng wrote:
>
>
> 21.03.2017, 06:01, "Jernej Skrabec" :
>> This series implements support for HDMI output. This is done using
>> DM video framework and
On 19 January 2017 at 18:03, Mark Brown <broo...@kernel.org> wrote:
> On Wed, Jan 18, 2017 at 08:09:00AM +0100, Code Kipper wrote:
>
>> I missed the binding documentation on the patch for the driver so I
>> pushed it separately instead of pushing a new patch version.
On 17 January 2017 at 19:15, Mark Brown wrote:
> On Thu, Jan 12, 2017 at 06:33:43PM +0100, codekip...@gmail.com wrote:
>> From: Marcus Cooper
>>
>> The H3 SoC uses the same SPDIF block as found in earlier SoCs, but the
>> transmit fifo is at a different
On 12 January 2017 at 18:28, Maxime Ripard
wrote:
> Hi,
>
> On Thu, Jan 12, 2017 at 06:11:35PM +0100, codekip...@gmail.com wrote:
>> From: Marcus Cooper
>>
>> The Beelink X2 is an STB based on the Allwinner H3 SoC with a uSD slot,
>> 2 USB
On 20 December 2016 at 20:16, Maxime Ripard
wrote:
> Hi,
>
> On Tue, Dec 20, 2016 at 03:55:24PM +0100, codekip...@gmail.com wrote:
>> From: Marcus Cooper
>>
>> Newer SoCs have additional functionality so a quirks structure
>> has been added
On 20 December 2016 at 15:16, Maxime Ripard
wrote:
> On Tue, Dec 20, 2016 at 11:22:42AM +0100, codekip...@gmail.com wrote:
>> From: Marcus Cooper
>>
>> This patch adds the regulator nodes for the axp209 by including
>> the axp209 dtsi.
>>
On 20 December 2016 at 15:07, Maxime Ripard
wrote:
> Hi,
>
> On Tue, Dec 20, 2016 at 11:40:37AM +0100, codekip...@gmail.com wrote:
>> From: Marcus Cooper
>>
>> Add the SPDIF transceiver controller block to the A31 dtsi.
>>
>> Signed-off-by:
On 11 November 2016 at 11:05, Chen-Yu Tsai wrote:
> The audio module clocks are supposed to be set according to the sample
> rate of the audio stream. The audio PLL provides the clock signal for
> thees module clocks, and only it is freely tunable.
nick! these
CK
>
> Set
On 8 November 2016 at 11:13, Andre Przywara <andre.przyw...@arm.com> wrote:
> Hi,
>
> On 08/11/16 09:44, Code Kipper wrote:
>> On 7 November 2016 at 15:29, Benjamin Henrion <zoo...@gmail.com> wrote:
>>> On Mon, Nov 7, 2016 at 3:23 PM, Chen-Yu Tsai <w...@cs
Much appreciated.I've just started playing with my Pine64 and
mainly use netboot for tinkering.
Thanks,
CK
On 7 November 2016 at 13:57, Benjamin Henrion wrote:
> Hi,
>
> There is now TFTP boot support in the latest u-boot tarball, so I made
> this recipe if you want to
On 18 October 2016 at 12:13, Thomas Gahr wrote:
>> Hi Thomas,
>> have you played with the alsamixer settings? you may have to do some
>> unmuting https://groups.google.com/forum/#!topic/linux-sunxi/rJDiF8qSnLc
>
>
> Hi CodeKipper,
> thanks for your answer!
>
> I'm afraid
On 4 October 2016 at 11:46, Mylène Josserand
wrote:
> Add the audio card for sun8i SoC. This card links the codec driver
> (digital part) with the DAI driver. The analog codec driver is
> added as an aux_device.
>
> Signed-off-by: Mylène Josserand
On 4 October 2016 at 11:46, Mylène Josserand
wrote:
> Add APB deassert function for sun4i-i2s driver.
>
> Signed-off-by: Mylène Josserand
> ---
> sound/soc/sunxi/sun4i-i2s.c | 16 +++-
> 1 file changed, 15
On 4 October 2016 at 11:46, Mylène Josserand
wrote:
> Add the analog part of the sun8i (A33) codec driver. This driver
> implements all the analog part of the codec using PRCM registers.
>
> The read/write regmap functions must be handled in a custom way as
>
On 4 October 2016 at 11:46, Mylène Josserand
wrote:
> Add the audio card for sun8i SoC. This card links the codec driver
> (digital part) with the DAI driver. The analog codec driver is
> added as an aux_device.
>
> Signed-off-by: Mylène Josserand
On 30 July 2016 at 17:17, Maxime Ripard
wrote:
> On Sat, Jul 30, 2016 at 04:27:15PM +0200, codekip...@gmail.com wrote:
>> From: Marcus Cooper
>>
>> The A31 SoC uses the same SPDIF block as found in earlier SoCs, but its
>> reset is
Hi Boobwrt,
I've also restarted looking at the h3 codec(although I will try and
get i2s working on my orange pi 2 first). Looking at the PRCM if you
could get something to read and write using syscon that would be the
first step...this was an old attempt
On 4 May 2016 at 11:44, Christo Radev wrote:
> Hi to All,
>
>
> I am trying to use USB OTG on A20-Olinuxino-Lime2-eMMC with own build of
> Armbian 5.11, U-Boot 2016.05--rec1, mainline kernel 4.5.2 and Debian Jessie
> without success. I have tested:
I don't think Wens
On 19 April 2016 at 17:11, Chen-Yu Tsai wrote:
> On Tue, Apr 19, 2016 at 10:46 PM, wrote:
>> Hi ChenYu,
>>
>> Thanks for your comments.
>>
>> On Tuesday, April 19, 2016 at 7:11:50 AM UTC-4, Chen-Yu Tsai wrote:
>>> Hi,
>>>
>>> >
On 14 April 2016 at 12:53, Juan Carlos Barrientos wrote:
> Thanks!! i would like to run accelerometer stk8313 and sound, is any kernel
> module ?
Hi Juan,
good effort on what you've done with the tablet. There is no sound
driver yet for the sun6i(a31) platform on
On 20 March 2016 at 10:16, Peter Korsgaard <pe...@korsgaard.com> wrote:
>>>>>> "Code" == Code Kipper <codekip...@gmail.com> writes:
>
> > Hi all,
> > I've been playing with the audio on sun4i for some time now and have
> > placed a br
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