Signed-off-by: Chen-Yu Tsai w...@csie.org
---
arch/arm/cpu/armv7/sunxi/pinmux.c | 18 ++
arch/arm/include/asm/arch-sunxi/gpio.h | 4
2 files changed, 22 insertions(+)
diff --git a/arch/arm/cpu/armv7/sunxi/pinmux.c
b/arch/arm/cpu/armv7/sunxi/pinmux.c
index 89a4b71
From: Jens Kuske jensku...@gmail.com
Signed-off-by: Jens Kuske jensku...@gmail.com
---
boards.cfg | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/boards.cfg b/boards.cfg
index 5d147e2..405cf56 100644
--- a/boards.cfg
+++ b/boards.cfg
@@ -364,8 +364,8 @@ Active arm
Signed-off-by: Chen-Yu Tsai w...@csie.org
---
arch/arm/cpu/armv7/sunxi/board.c | 7 ++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/arch/arm/cpu/armv7/sunxi/board.c b/arch/arm/cpu/armv7/sunxi/board.c
index 386b16e..5d19a64 100644
--- a/arch/arm/cpu/armv7/sunxi/board.c
+++ b
GMAC in A20 SoC supports MII and RGMII modes.
Support both so we can use GMAC in different boards.
Signed-off-by: Chen-Yu Tsai w...@csie.org
---
arch/arm/cpu/armv7/sunxi/board.c | 9 +
boards.cfg | 4 ++--
2 files changed, 11 insertions(+), 2 deletions(-)
diff
GMAC on cubietruck uses a gigabit PHY.
Enable gigabit PHY support so auto-negotiation is correct.
Signed-off-by: Chen-Yu Tsai w...@csie.org
---
include/configs/sunxi-common.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/include/configs/sunxi-common.h b/include/configs/sunxi-common.h
index
Add macros for gmac clock control, instead of using raw values.
Also add comment noting GMAC ahb gate is in second gate register,
to avoid confusion over same offset as EMAC.
Signed-off-by: Chen-Yu Tsai w...@csie.org
---
arch/arm/include/asm/arch-sunxi/clock.h | 8
1 file changed, 8
to gmac clock macros instead of magic numbers
* Added comment on ahb0 vs ahb1 for GMAC clock gate offset
* Added explanatory message to Ma Haijun's commit
Chen-Yu Tsai (8):
ARM: sunxi: Enable support for gigabit PHYs
ARM: sunxi: Add functions to set pin drive levels
ARM: sunxi: Set drive level
From: Jens Kuske jensku...@gmail.com
Signed-off-by: Jens Kuske jensku...@gmail.com
---
boards.cfg | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/boards.cfg b/boards.cfg
index 5d147e2..405cf56 100644
--- a/boards.cfg
+++ b/boards.cfg
@@ -364,8 +364,8 @@ Active arm
Signed-off-by: Chen-Yu Tsai w...@csie.org
---
arch/arm/cpu/armv7/sunxi/board.c | 7 ++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/arch/arm/cpu/armv7/sunxi/board.c b/arch/arm/cpu/armv7/sunxi/board.c
index 386b16e..5d19a64 100644
--- a/arch/arm/cpu/armv7/sunxi/board.c
+++ b
GMAC init code now exists in a glue layer driver under drivers/net,
instead of sunxi board initialization code. It has been cleaned up
to use macros for clock controls.
Signed-off-by: Chen-Yu Tsai w...@csie.org
---
arch/arm/cpu/armv7/sunxi/board.c | 32 +---
drivers/net
From: Jens Kuske jensku...@gmail.com
The GMAC module in Allwinner sunxi SoCs seems to have problems with
burst lenghts 8.
Signed-off-by: Jens Kuske jensku...@gmail.com
---
drivers/net/designware.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/net/designware.c
This patch adds support for the external clock outputs on the
Allwinner A20 SoC. The clock outputs are similar to module 0
type clocks, with different offsets and widths for clock factors.
Signed-off-by: Chen-Yu Tsai w...@csie.org
---
drivers/clk/sunxi/clk-sunxi.c | 57
This patch adds the clock output pin functions on the A20.
The 2 pins can output a configurable clock to be used by
external modules. This is used on the CubieTruck, to supply
a 32768 Hz low power clock to the onboard Wifi+BT module.
Signed-off-by: Chen-Yu Tsai w...@csie.org
---
drivers/pinctrl
This commit adds the two external clock outputs available on A20 to
its device tree. A dummy fixed factor clock is also added to serve as
the first input of the clock outputs, which according to AW's A20 user
manual, is the 24MHz oscillator divided by 750.
Signed-off-by: Chen-Yu Tsai w
Hi,
On Mon, Dec 30, 2013 at 11:25 PM, Maxime Ripard
maxime.rip...@free-electrons.com wrote:
Hi,
On Mon, Dec 30, 2013 at 11:25:47AM +0800, Chen-Yu Tsai wrote:
This commit adds the two external clock outputs available on A20 to
its device tree. A dummy fixed factor clock is also added to serve
This patch adds the clock output pin options on the A20.
The 2 pins can output a configurable clock to be used by
external modules. This is used on the CubieTruck, to supply
a 32768 Hz low power clock to the onboard Wifi+BT module.
Signed-off-by: Chen-Yu Tsai w...@csie.org
---
arch/arm/boot/dts
This patch adds the clock output pin functions on the A20.
The 2 pins can output a configurable clock to be used by
external modules. This is used on the CubieTruck, to supply
a 32768 Hz low power clock to the onboard Wifi+BT module.
Signed-off-by: Chen-Yu Tsai w...@csie.org
Acked-by: Maxime
This patch adds support for the external clock outputs on the
Allwinner A20 SoC. The clock outputs are similar to module 0
type clocks, with different offsets and widths for clock factors.
Signed-off-by: Chen-Yu Tsai w...@csie.org
---
Documentation/devicetree/bindings/clock/sunxi.txt | 1
Hi,
Would you like to merge v2 of the gmac series as it is now?
It has proper MII/RGMII support, so it doesn't need u-boot.
https://github.com/wens/linux/tree/wip/stmmac-v2
Cheers,
ChenYu
On Thu, Jan 2, 2014 at 10:12 PM, Hans de Goede hdego...@redhat.com wrote:
Hi All,
I've just updated:
Hi,
On Thu, Jan 2, 2014 at 9:59 PM, Arend van Spriel ar...@broadcom.com wrote:
[snip]
Hi Chen-Yu,
I confirmed the patch is working with a revision 0 of the device. What
chip revision does it give in your log (need to load brcmfmac with
module parameter debug=4).
Mine is revision 1. Managed
Hi,
On Fri, Jan 3, 2014 at 12:52 AM, Michal Suchanek hramr...@gmail.com wrote:
Hello,
On 19 December 2013 11:12, Chen-Yu Tsai w...@csie.org wrote:
[snip]
Bluetooth still isn't responding.
Well, bluetooth is supposed to be attached to an UART, not SDIO.
That's what the datasheets
On Thu, Jan 2, 2014 at 10:10 PM, Hans de Goede hdego...@redhat.com wrote:
[snip]
I've also taken a quick look at your patches, I've one remark about:
https://github.com/linux-sunxi/linux-sunxi/commit/796b36502919bd4327029d0f0b10180af279c72e
Hi David, in the patch Hans noted, it seems you missed
Device tree naming conventions state that node names should match
node function. Change fully functioning clock nodes to match.
Signed-off-by: Chen-Yu Tsai w...@csie.org
---
arch/arm/boot/dts/sun7i-a20.dtsi | 19 +++
1 file changed, 11 insertions(+), 8 deletions(-)
diff --git
the strcmp in mod0
clock to match the others.
Signed-off-by: Chen-Yu Tsai w...@csie.org
---
Should I split this patch?
drivers/clk/sunxi/clk-sunxi.c | 15 +++
1 file changed, 7 insertions(+), 8 deletions(-)
diff --git a/drivers/clk/sunxi/clk-sunxi.c b/drivers/clk/sunxi/clk-sunxi.c
index
Device tree naming conventions state that node names should match
node function. Change fully functioning clock nodes to match.
Signed-off-by: Chen-Yu Tsai w...@csie.org
---
arch/arm/boot/dts/sun4i-a10.dtsi | 24 ++--
1 file changed, 14 insertions(+), 10 deletions(-)
diff
The Cubietruck makes use of the first three i2c controllers found on the
Allwinner A10; i2c-0 is used internally for the PMIC, i2c-1 is exposed on
the board headers, and i2c-2 is used for DDC on the VGA connector. This
patch enables them in the device tree.
Signed-off-by: Chen-Yu Tsai w
sunxi clock drivers use dt node name as clock name, but clock
nodes should be named clk@X, so the names would be the same.
Let the drivers read clock names from dt clock-output-names
property.
Signed-off-by: Chen-Yu Tsai w...@csie.org
---
drivers/clk/sunxi/clk-sunxi.c | 6 ++
1 file changed
On Wed, Jan 8, 2014 at 4:56 PM, Arend van Spriel ar...@broadcom.com wrote:
On 12/27/2013 01:36 PM, Chen-Yu Tsai wrote:
Working tree:
https://github.com/wens/linux/tree/wip/sunxi-next-wifi
Comments welcome :)
No comment, but: Nice work!
Thanks. BTW, who should submit the patch
Device tree naming conventions state that node names should match
node function. Change fully functioning clock nodes to match.
Also add the output name for pll5 to use as the clock name.
Signed-off-by: Chen-Yu Tsai w...@csie.org
---
arch/arm/boot/dts/sun4i-a10.dtsi | 24
Device tree naming conventions state that node names should match
node function. Change fully functioning clock nodes to match.
Signed-off-by: Chen-Yu Tsai w...@csie.org
---
arch/arm/boot/dts/sun6i-a31.dtsi | 12 +++-
1 file changed, 7 insertions(+), 5 deletions(-)
diff --git a/arch/arm
clock-output-names is now required for most of sunxi clock nodes, to
provide the name of the corresponding clock. Add the new requirements,
exceptions, as well as examples.
Signed-off-by: Chen-Yu Tsai w...@csie.org
---
Documentation/devicetree/bindings/clock/sunxi.txt | 36
.
* Dropped pll5 output name in dts due to the previous change.
* Added dts binding documentation for clock-output-names, as well as
examples.
Changes since v1:
* Fixed pll5, pll6 divs clock name handling
Cheers
ChenYu
Chen-Yu Tsai (8):
clk: sunxi: add clock-output-names dt property
Device tree naming conventions state that node names should match
node function. Change fully functioning clock nodes to match.
Also add the output name for pll5 to use as the clock name.
Signed-off-by: Chen-Yu Tsai w...@csie.org
---
arch/arm/boot/dts/sun7i-a20.dtsi | 19 +++
1
sunxi clock drivers use dt node name as clock name, but clock
nodes should be named clk@X, so the names would be the same.
Let the drivers read clock names from dt clock-output-names
property.
Signed-off-by: Chen-Yu Tsai w...@csie.org
---
drivers/clk/sunxi/clk-sunxi.c | 6 ++
1 file changed
Device tree naming conventions state that node names should match
node function. Change fully functioning clock nodes to match.
Also add the output name for pll5 to use as the clock name.
Signed-off-by: Chen-Yu Tsai w...@csie.org
---
arch/arm/boot/dts/sun5i-a10s.dtsi | 24
GMAC has better performance and fewer hardware issues.
Use the GMAC in MII mode for ethernet instead of the EMAC.
Signed-off-by: Chen-Yu Tsai w...@csie.org
---
arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts | 27 +++--
1 file changed, 12 insertions(+), 15 deletions(-)
diff
stmmac callbacks have been extended for better seperation.
Update them to avoid breakage.
Signed-off-by: Chen-Yu Tsai w...@csie.org
---
arch/blackfin/mach-bf609/boards/ezkit.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/blackfin/mach-bf609/boards/ezkit.c
b/arch
The current .init and .exit callbacks requires access to driver
private data structures. This is not a good seperation and abstraction.
Instead, we add a new .setup callback for allocating private data, and
pass the returned pointer to the other callbacks.
Signed-off-by: Chen-Yu Tsai w
The DWMAC has a reset assert line, which is used on some SoCs. Add an
optional reset control to stmmac driver core.
To support reset control deferred probing, this patch changes the driver
probe function to return the actual error, instead of just -EINVAL.
Signed-off-by: Chen-Yu Tsai w
U-Boot will insert MAC address into the device tree image.
It looks up ethernet[0-5] aliases to find the ethernet nodes.
Alias GMAC as ethernet0, as it is the only ethernet controller used.
Signed-off-by: Chen-Yu Tsai w...@csie.org
---
arch/arm/boot/dts/sun7i-a20.dtsi | 2 +-
1 file changed, 1
-by: Chen-Yu Tsai w...@csie.org
---
include/linux/reset.h | 39 +++
1 file changed, 39 insertions(+)
diff --git a/include/linux/reset.h b/include/linux/reset.h
index 6082247..38aa616 100644
--- a/include/linux/reset.h
+++ b/include/linux/reset.h
@@ -4,6 +4,8
The A20 has EMAC and GMAC muxed on the same pins.
Add pin sets with gmac function for MII and RGMII mode to the DTSI.
Signed-off-by: Chen-Yu Tsai w...@csie.org
---
arch/arm/boot/dts/sun7i-a20.dtsi | 26 ++
1 file changed, 26 insertions(+)
diff --git a/arch/arm/boot/dts
Hi,
On Wed, Jan 15, 2014 at 6:02 PM, Maxime Ripard
maxime.rip...@free-electrons.com wrote:
Hi Chen-Yu,
Nice catch :)
On Wed, Jan 15, 2014 at 04:21:12PM +0800, Chen-Yu Tsai wrote:
Hi,
On Wed, Jan 15, 2014 at 8:37 AM, Ma Haijun mahaij...@gmail.com wrote:
Hi,
I think it is better
Some GPIO users, such as fixed-regulator, request GPIO output with
initial value of 1. This was ignored by sunxi driver.
Signed-off-by: Chen-Yu Tsai w...@csie.org
---
Changes since v2:
* Set output value before setting the pin function to avoid a glitch.
drivers/pinctrl/pinctrl-sunxi.c
Hi Hans,
On Wed, Jan 15, 2014 at 11:48 PM, Hans de Goede hdego...@redhat.com wrote:
Hi,
On 01/15/2014 04:00 PM, Kishon Vijay Abraham I wrote:
On Wednesday 15 January 2014 04:28 AM, Hans de Goede wrote:
[...]
+static int sun4i_usb_phy_init(struct phy *_phy)
+{
+ struct sun4i_usb_phy
Some GPIO users, such as fixed-regulator, request GPIO output with
initial value of 1. This was ignored by sunxi driver.
Signed-off-by: Chen-Yu Tsai w...@csie.org
Acked-by: Maxime Ripard maxime.rip...@free-electrons.com
Cc: sta...@vger.kernel.org
---
Resend CCing stable.
Changes since v2
Hi,
On Fri, Jan 10, 2014 at 9:30 PM, Philipp Zabel p.za...@pengutronix.de wrote:
Hi,
[Added Ivan, Stephen and Barry to Cc:]
Am Freitag, den 10.01.2014, 15:00 +0800 schrieb Chen-Yu Tsai:
Some drivers are shared between platforms that may or may not
have RESET_CONTROLLER selected for them
snprintf should be passed the complete size of the buffer, including
the space for '\0'. The previous code resulted in the *_reset and
*_shutdown strings being truncated.
Signed-off-by: Chen-Yu Tsai w...@csie.org
---
net/rfkill/rfkill-gpio.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions
Signed-off-by: Chen-Yu Tsai w...@csie.org
---
.../devicetree/bindings/rfkill/rfkill-gpio.txt | 26 ++
net/rfkill/rfkill-gpio.c | 23 +++
2 files changed, 49 insertions(+)
create mode 100644 Documentation/devicetree/bindings/rfkill
-by: Chen-Yu Tsai w...@csie.org
---
arch/arm/boot/dts/sun7i-a20-cubietruck.dts | 37 ++
1 file changed, 37 insertions(+)
diff --git a/arch/arm/boot/dts/sun7i-a20-cubietruck.dts
b/arch/arm/boot/dts/sun7i-a20-cubietruck.dts
index c8b3ea9..f172a8f 100644
--- a/arch/arm/boot/dts
rfkill-gpio calls clk_enable() without first calling clk_prepare(),
resulting in a warning and no effect. Switch to clk_prepare_enable()
and clk_disable_unprepare.
Signed-off-by: Chen-Yu Tsai w...@csie.org
---
net/rfkill/rfkill-gpio.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions
for the lack of explicit address selection.
Signed-off-by: Chen-Yu Tsai w...@csie.org
---
Documentation/devicetree/bindings/net/stmmac.txt | 1 -
drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c | 9 -
2 files changed, 8 insertions(+), 2 deletions(-)
diff --git a/Documentation
that Allwinner uses is unknown,
thus the exact feature set is unknown.
Signed-off-by: Chen-Yu Tsai w...@csie.org
---
.../bindings/net/allwinner,sun7i-a20-gmac.txt | 27
drivers/net/ethernet/stmicro/stmmac/Kconfig| 11 ++
drivers/net/ethernet/stmicro/stmmac/Makefile | 1
The stmmac driver does not enable the main clock during the probe phase.
If the clock was not enabled by the boot loader or was disabled by the
kernel, hardware features and the MDIO bus would not be probed properly.
Signed-off-by: Chen-Yu Tsai w...@csie.org
---
drivers/net/ethernet/stmicro
The DWMAC has a reset assert line, which is used on some SoCs. Add an
optional reset control to stmmac driver core.
To support reset control deferred probing, this patch changes the driver
probe function to return the actual error, instead of just -EINVAL.
Signed-off-by: Chen-Yu Tsai w
,
instead of platform data, as discussed
* Seperated clock module glue layer into clock driver
Cheers,
ChenYu
Chen-Yu Tsai (8):
net: stmmac: Enable stmmac main clock when probing hardware
net: stmmac: Add support for optional reset control
net: stmmac: Allocate and pass soc/board
The current .init and .exit callbacks requires access to driver
private data structures. This is not a good seperation and abstraction.
Instead, we add a new .setup callback for allocating private data, and
pass the returned pointer to the other callbacks.
Signed-off-by: Chen-Yu Tsai w
On Sat, Jan 18, 2014 at 7:11 AM, Linus Walleij linus.wall...@linaro.org wrote:
On Fri, Jan 17, 2014 at 6:43 PM, Chen-Yu Tsai w...@csie.org wrote:
On Sat, Jan 18, 2014 at 12:47 AM, Arnd Bergmann a...@arndb.de wrote:
+- NAME_shutdown-gpios : GPIO phandle to shutdown control
Hi,
On Thu, Jan 23, 2014 at 3:04 AM, Hans de Goede hdego...@redhat.com wrote:
From: Oliver Schinagl oli...@schinagl.nl
This patch adds sunxi sata support to A10 boards that have such a connector.
Some boards also feature a regulator via a GPIO and support for this is also
added.
Hi,
On Mon, Jan 27, 2014 at 12:34 AM, Hans de Goede hdego...@redhat.com wrote:
Hi,
On 01/24/2014 04:38 AM, Chen-Yu Tsai wrote:
snip
Quick update, I've just tested:
https://github.com/wens/linux/commits/wip/sunxi-next-wifi
About this, I would like to move WiFi power control
On Mon, Jan 27, 2014 at 3:31 PM, Hans de Goede hdego...@redhat.com wrote:
Hi,
On 01/26/2014 05:58 PM, Chen-Yu Tsai wrote:
Hi,
On Mon, Jan 27, 2014 at 12:34 AM, Hans de Goede hdego...@redhat.com
wrote:
Hi,
On 01/24/2014 04:38 AM, Chen-Yu Tsai wrote:
snip
Quick update, I've just
Hi Maxime,
On Fri, Jan 17, 2014 at 10:55 AM, Emilio López emi...@elopez.com.ar wrote:
Hi,
El 09/01/14 05:52, Chen-Yu Tsai escribió:
clock-output-names is now required for most of sunxi clock nodes, to
provide the name of the corresponding clock. Add the new requirements,
exceptions
sunxi clock drivers use dt node name as clock name, but clock
nodes should be named clk@X, so the names would be the same.
Let the drivers read clock names from dt clock-output-names
property.
Signed-off-by: Chen-Yu Tsai w...@csie.org
Acked-by: Maxime Ripard maxime.rip...@free-electrons.com
Acked
clock-output-names is now required for most of sunxi clock nodes, to
provide the name of the corresponding clock. Add the new requirements,
exceptions, as well as examples.
Signed-off-by: Chen-Yu Tsai w...@csie.org
---
Documentation/devicetree/bindings/clock/sunxi.txt | 32
Device tree naming conventions state that node names should match
node function. Change fully functioning clock nodes to match and
add clock-output-names to all sunxi clock nodes.
Signed-off-by: Chen-Yu Tsai w...@csie.org
---
arch/arm/boot/dts/sun5i-a10s.dtsi | 30
Device tree naming conventions state that node names should match
node function. Change fully functioning clock nodes to match and
add clock-output-names to all sunxi clock nodes.
Signed-off-by: Chen-Yu Tsai w...@csie.org
---
arch/arm/boot/dts/sun6i-a31.dtsi | 19 ++-
1 file
with Srinivas
* Used new stmmac_of_data to pass features and callbacks,
instead of platform data, as discussed
* Seperated clock module glue layer into clock driver
Cheers,
ChenYu
Chen-Yu Tsai (8):
clk: sunxi: Add Allwinner A20/A31 GMAC clock unit
ARM: dts: sun7i: Add GMAC clock node
Signed-off-by: Chen-Yu Tsai w...@csie.org
---
arch/arm/boot/dts/sun7i-a20.dtsi | 15 +++
1 file changed, 15 insertions(+)
diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7i-a20.dtsi
index fc7f470..5fbac23 100644
--- a/arch/arm/boot/dts/sun7i-a20.dtsi
+++ b/arch
The GMAC uses 1 of 2 sources for its transmit clock, depending on the
PHY interface mode. Add both sources as dummy clocks, and as parents
to the GMAC clock node.
Signed-off-by: Chen-Yu Tsai w...@csie.org
---
arch/arm/boot/dts/sun7i-a20.dtsi | 28
1 file changed, 28
U-Boot will insert MAC address into the device tree image.
It looks up ethernet[0-5] aliases to find the ethernet nodes.
Alias GMAC as ethernet0, as it is the only ethernet controller used.
Signed-off-by: Chen-Yu Tsai w...@csie.org
---
arch/arm/boot/dts/sun7i-a20.dtsi | 2 +-
1 file changed, 1
GMAC has better performance and fewer hardware issues.
Use the GMAC in MII mode for ethernet instead of the EMAC.
Signed-off-by: Chen-Yu Tsai w...@csie.org
---
arch/arm/boot/dts/sun7i-a20-cubieboard2.dts | 27 ---
1 file changed, 12 insertions(+), 15 deletions(-)
diff
GMAC has better performance and fewer hardware issues.
Use the GMAC in MII mode for ethernet instead of the EMAC.
Signed-off-by: Chen-Yu Tsai w...@csie.org
---
arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts | 27 +++--
1 file changed, 12 insertions(+), 15 deletions(-)
diff
Hi,
On Tue, Feb 4, 2014 at 3:31 AM, Maxime Ripard
maxime.rip...@free-electrons.com wrote:
Hi,
On Mon, Feb 03, 2014 at 11:32:19AM +0800, Chen-Yu Tsai wrote:
The Allwinner A20/A31 clock module controls the transmit clock source
and interface type of the GMAC ethernet controller. Model
On Tue, Feb 4, 2014 at 3:38 AM, Maxime Ripard
maxime.rip...@free-electrons.com wrote:
On Mon, Feb 03, 2014 at 11:32:26AM +0800, Chen-Yu Tsai wrote:
U-Boot will insert MAC address into the device tree image.
It looks up ethernet[0-5] aliases to find the ethernet nodes.
Alias GMAC as ethernet0
On Sat, Feb 8, 2014 at 12:33 AM, Hans de Goede hdego...@redhat.com wrote:
The Allwinner A1x / A2x SoCs have 2 or 3 usb phys which are all accessed
through a single set of registers. Besides this there are also some other
phy related bits which need poking, which are per phy, but shared between
The A20 has EMAC and GMAC muxed on the same pins.
Add pin sets with gmac function for MII and RGMII mode to the DTSI.
Signed-off-by: Chen-Yu Tsai w...@csie.org
---
arch/arm/boot/dts/sun7i-a20.dtsi | 26 ++
1 file changed, 26 insertions(+)
diff --git a/arch/arm/boot/dts
All Allwinner A20 boards we support can only use either EMAC or GMAC,
as they share the same pins. As we have switched all supported to
GMAC, we should alias GMAC (the active controller) as ethernet0,
so u-boot will insert the MAC address for the correct controller.
Signed-off-by: Chen-Yu Tsai w
The CubieTruck uses the GMAC with an RGMII phy.
Signed-off-by: Chen-Yu Tsai w...@csie.org
---
arch/arm/boot/dts/sun7i-a20-cubietruck.dts | 12
1 file changed, 12 insertions(+)
diff --git a/arch/arm/boot/dts/sun7i-a20-cubietruck.dts
b/arch/arm/boot/dts/sun7i-a20-cubietruck.dts
GMAC has better performance and fewer hardware issues.
Use the GMAC in MII mode for ethernet instead of the EMAC.
Signed-off-by: Chen-Yu Tsai w...@csie.org
---
arch/arm/boot/dts/sun7i-a20-cubieboard2.dts | 27 ---
1 file changed, 12 insertions(+), 15 deletions(-)
diff
GMAC has better performance and fewer hardware issues.
Use the GMAC in MII mode for ethernet instead of the EMAC.
Signed-off-by: Chen-Yu Tsai w...@csie.org
---
arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts | 27 +++--
1 file changed, 12 insertions(+), 15 deletions(-)
diff
Signed-off-by: Chen-Yu Tsai w...@csie.org
---
arch/arm/boot/dts/sun7i-a20.dtsi | 15 +++
1 file changed, 15 insertions(+)
diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7i-a20.dtsi
index dd567ea..8eb4d54 100644
--- a/arch/arm/boot/dts/sun7i-a20.dtsi
+++ b/arch
routines for the above change
* Extended callback API, as discussed with Srinivas
* Used new stmmac_of_data to pass features and callbacks,
instead of platform data, as discussed
* Seperated clock module glue layer into clock driver
Cheers,
ChenYu
Chen-Yu Tsai (8):
clk: sunxi: Add Allwinner
The Allwinner A20/A31 clock module controls the transmit clock source
and interface type of the GMAC ethernet controller. Model this as
a single clock for GMAC drivers to use.
Signed-off-by: Chen-Yu Tsai w...@csie.org
---
Documentation/devicetree/bindings/clock/sunxi.txt | 30 +++
drivers
The Allwinner A20/A31 clock module controls the transmit clock source
and interface type of the GMAC ethernet controller. Model this as
a single clock for GMAC drivers to use.
Signed-off-by: Chen-Yu Tsai w...@csie.org
---
Hi,
This is v5 of the Allwinner A20 GMAC clock patch. Hans noted
Hi,
On Wed, Feb 12, 2014 at 3:33 AM, David Lanzendörfer
david.lanzendoer...@o2s.ch wrote:
This is based on the driver Allwinner ships in their Android kernel sources.
Initial porting to upstream kernels done by David Lanzendörfer, additional
fixes and cleanups by Hans de Goede.
It uses dma
Hi,
On Sat, Feb 15, 2014 at 8:02 PM, Hans de Goede hdego...@redhat.com wrote:
Hi All,
Here is a patch series fixing external interrupts, tested only on A20 sofar,
I'll do a version for upstream once I've tested this more thoroughly, but
I wanted to share this right away.
I submitted the
The A31 has the same GMAC found on the A20 SoC, except it has
an extra reset control.
Signed-off-by: Chen-Yu Tsai w...@csie.org
---
arch/arm/boot/dts/sun6i-a31.dtsi | 16
1 file changed, 16 insertions(+)
diff --git a/arch/arm/boot/dts/sun6i-a31.dtsi b/arch/arm/boot/dts/sun6i
The GMAC uses 1 of 2 sources for its transmit clock, depending on the
PHY interface mode. Add both sources as dummy clocks, and as parents
to the GMAC clock node.
Signed-off-by: Chen-Yu Tsai w...@csie.org
---
arch/arm/boot/dts/sun6i-a31.dtsi | 28
1 file changed, 28
give it a try, and let me know if it works or not.
Cheers,
ChenYu
Chen-Yu Tsai (5):
ARM: sun6i: dt: Add pin muxing options for GMAC
ARM: sun6i: dt: Add GMAC clock node to the A31 DTSI
ARM: sun6i: dt: Add A31 GMAC gigabit ethernet controller node
ARM: sun6i: dt: Add ethernet alias for GMAC
The A31 SoC has a GMAC gigabit ethernet controller supporting
MII, GMII, RGMII modes. Add pin muxing options for these modes.
Signed-off-by: Chen-Yu Tsai w...@csie.org
---
arch/arm/boot/dts/sun6i-a31.dtsi | 42
1 file changed, 42 insertions(+)
diff --git
The A31 Colombus board uses the GMAC with a Realtek RTL8211E-VB RGMII phy.
Signed-off-by: Chen-Yu Tsai w...@csie.org
---
arch/arm/boot/dts/sun6i-a31-colombus.dts | 12
1 file changed, 12 insertions(+)
diff --git a/arch/arm/boot/dts/sun6i-a31-colombus.dts
b/arch/arm/boot/dts/sun6i
AXP202 and AXP209 can report voltages and current readings for its
various power inputs, as well as the LiPo battery. There is also an
internal temperature sensor. This patch adds basic support for them.
Signed-off-by: Chen-Yu Tsai w...@csie.org
---
Hi everyone,
This is a basic hwmon driver
On Fri, Mar 7, 2014 at 6:34 PM, Russell King - ARM Linux
li...@arm.linux.org.uk wrote:
On Fri, Mar 07, 2014 at 11:07:51AM +0100, Maxime Ripard wrote:
Hi Russell,
On Fri, Mar 07, 2014 at 09:52:23AM +, Russell King - ARM Linux wrote:
On Tue, Mar 04, 2014 at 05:28:37PM +0100, Maxime Ripard
On Fri, Mar 14, 2014 at 6:33 PM, Ian Campbell i...@hellion.org.uk wrote:
Based linux-sunxi#sunxi commit d854c4de2f57 arm: Handle .gnu.hash section in
ldscripts vs v2014.01.
Signed-off-by: Chen-Yu Tsai w...@csie.org
Signed-off-by: Jens Kuske jensku...@gmail.com
Signed-off-by: Ian Campbell i
On Mon, Mar 17, 2014 at 4:38 AM, Ian Campbell i...@hellion.org.uk wrote:
On Fri, 2014-03-14 at 17:36 +0200, Pantelis Antoniou wrote:
[...]
Thanks for your review. It seems there are still quite a few issues
dating back to the original allwinner dumps here.
@linux-sunxi: if anyone wants to
Use the sunxi gpio driver to configure pins, instead of directly
writing magic numbers.
Signed-off-by: Chen-Yu Tsai w...@csie.org
---
drivers/mmc/sunxi_mmc.c | 56 +++--
1 file changed, 26 insertions(+), 30 deletions(-)
diff --git a/drivers/mmc
Signed-off-by: Chen-Yu Tsai w...@csie.org
---
drivers/net/sunxi_gmac.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/net/sunxi_gmac.c b/drivers/net/sunxi_gmac.c
index b8b9016..98a78c4 100644
--- a/drivers/net/sunxi_gmac.c
+++ b/drivers/net/sunxi_gmac.c
@@ -31,7 +31,7
Signed-off-by: Chen-Yu Tsai w...@csie.org
---
drivers/i2c/sunxi_i2c.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/i2c/sunxi_i2c.c b/drivers/i2c/sunxi_i2c.c
index 5fe790a..5babf06 100644
--- a/drivers/i2c/sunxi_i2c.c
+++ b/drivers/i2c/sunxi_i2c.c
@@ -19,8 +19,8
On Mon, Mar 17, 2014 at 4:28 PM, Ian Campbell i...@hellion.org.uk wrote:
On Mon, 2014-03-17 at 12:05 +0800, Chen-Yu Tsai wrote:
@@ -162,40 +151,47 @@ static int mmc_clk_io_on(int sdc_no)
switch (sdc_no) {
case 0:
/* D1-PF0, D0-PF1, CLK-PF2, CMD-PF3, D3-PF4, D4-PF5
Signed-off-by: Chen-Yu Tsai w...@csie.org
---
drivers/i2c/sunxi_i2c.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/i2c/sunxi_i2c.c b/drivers/i2c/sunxi_i2c.c
index 5fe790a..9a542f6 100644
--- a/drivers/i2c/sunxi_i2c.c
+++ b/drivers/i2c/sunxi_i2c.c
@@ -19,8 +19,8
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