Re: [Mesa-dev] radeon cmask sync with EGL/GBM

On 10/01/2016 19:38, Jay Cornwall wrote: Hi, Using EGL with the GBM platform it is possible to bind a GBM surface to a GL renderbuffer. I believe it's also valid to use the GBM BO as a framebuffer target with drmModeAddFB/drmModePageFlip. I haven't been able to locate a clear statement on sy

Re: [Mesa-dev] [PATCH] glsl: add image_format check in cross_validate_globals()

Reviewed-by: Tapani Pälli On 01/05/2016 03:32 PM, Samuel Iglesias Gonsálvez wrote: Fixes CTS test: ES31-CTS.shader_image_load_store.negative-linkErrors Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=93410 Signed-off-by: Samuel Iglesias Gonsálvez --- src/glsl/linker.cpp | 6 ++

Re: [Mesa-dev] [PATCH 1/7] glsl: enable offset layout qualifier for ARB_enhanced_layouts

This series is, Reviewed-by: Edward O'Callaghan On 2016-01-11 14:13, Timothy Arceri wrote: --- src/glsl/glsl_parser.yy | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/src/glsl/glsl_parser.yy b/src/glsl/glsl_parser.yy index 6b634f2..b2b94f4 100644 --- a/src/glsl/glsl_pars

[Mesa-dev] [Bug 93667] Crash in eglCreateImageKHR with huge texture size

https://bugs.freedesktop.org/show_bug.cgi?id=93667 Bug ID: 93667 Summary: Crash in eglCreateImageKHR with huge texture size Product: Mesa Version: unspecified Hardware: x86-64 (AMD64) OS: Linux (All) Status: NEW

[Mesa-dev] NIR, SCons, and Gallium

FWIW, I updated SCons to build NIR, both with GCC and MSVC: http://cgit.freedesktop.org/~jrfonseca/mesa/log/?h=scons-nir It was actually simpler than I anticipated. But I hit a wall -- there's actually no way to get NIR used with softpipe/llvmpipe, not even as an intermediate IR somewhere be

Re: [Mesa-dev] radeon cmask sync with EGL/GBM

On Mon, Jan 11, 2016 at 9:42 AM, Axel Davy wrote: > On 10/01/2016 19:38, Jay Cornwall wrote: >> >> Hi, >> >> Using EGL with the GBM platform it is possible to bind a GBM surface to a >> GL renderbuffer. I believe it's also valid to use the GBM BO as a >> framebuffer target with drmModeAddFB/drmMod

Re: [Mesa-dev] radeon cmask sync with EGL/GBM

On 11/01/2016 15:39, Marek Olšák wrote: On Mon, Jan 11, 2016 at 9:42 AM, Axel Davy wrote: On 10/01/2016 19:38, Jay Cornwall wrote: Hi, Using EGL with the GBM platform it is possible to bind a GBM surface to a GL renderbuffer. I believe it's also valid to use the GBM BO as a framebuffer target

Re: [Mesa-dev] [PATCH 0/2] trivial cleanups

Ping? On Wed, Dec 16, 2015 at 5:09 PM, Erik Faye-Lund wrote: > Here's some trivial cleanups I found while diving into something else. > > Instead of them collecting dust in my tree, perhaps we could apply them to > the central tree? > > Erik Faye-Lund (2): > gallium/util: removed unused header-

Re: [Mesa-dev] [PATCH] mesa: check that internalformat of CopyTexImage*D is not 1, 2, 3, 4

On Thu, Jan 7, 2016 at 11:49 PM, Ian Romanick wrote: > On 01/07/2016 12:31 PM, Nicolai Hähnle wrote: >> From: Nicolai Hähnle >> >> The piglit copyteximage check has recently been augmented to test this, but >> apparently it hasn't been fixed in Mesa so far. >> --- >> src/mesa/main/teximage.c | 1

[Mesa-dev] [PATCH] nir: special hack for TGSI vs indirect inputs

From: Rob Clark TGSI doesn't know about array input (or output[*]) variables. If the INPUT file is addressed indirectly, we must treat the entire INPUT "register file" as one contiguous array. However tgsi_to_nir cannot declare all the inputs as a single array var, as this would loose varying s

Re: [Mesa-dev] [PATCH] nir: special hack for TGSI vs indirect inputs

Are you looking for PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE perchance? On Mon, Jan 11, 2016 at 11:44 AM, Rob Clark wrote: > From: Rob Clark > > TGSI doesn't know about array input (or output[*]) variables. If the > INPUT file is addressed indirectly, we must treat the entire INPUT > "register

Re: [Mesa-dev] NIR, SCons, and Gallium

On Mon, Jan 11, 2016 at 9:21 AM, Jose Fonseca wrote: > FWIW, I updated SCons to build NIR, both with GCC and MSVC: > > http://cgit.freedesktop.org/~jrfonseca/mesa/log/?h=scons-nir > > It was actually simpler than I anticipated. > > But I hit a wall -- there's actually no way to get NIR used with

Re: [Mesa-dev] [PATCH] nir: special hack for TGSI vs indirect inputs

Quite possibly I am.. although wouldn't I still have the same issue with other state trackers? So in that case I'd have to detect indirect access, but without ArrayID's, and still set this flag. BR, -R On Mon, Jan 11, 2016 at 11:47 AM, Ilia Mirkin wrote: > Are you looking for PIPE_SHADER_CAP_T

Re: [Mesa-dev] [PATCH] nir: special hack for TGSI vs indirect inputs

Yes the countless other state trackers which emit indirect loads on inputs... I think you can safely just assert if it happens :) On Mon, Jan 11, 2016 at 12:07 PM, Rob Clark wrote: > Quite possibly I am.. although wouldn't I still have the same issue > with other state trackers? So in that

[Mesa-dev] [PATCH 1/2] i965/fs: Add debugging to constant combining pass.

--- .../drivers/dri/i965/brw_fs_combine_constants.cpp | 21 - 1 file changed, 20 insertions(+), 1 deletion(-) diff --git a/src/mesa/drivers/dri/i965/brw_fs_combine_constants.cpp b/src/mesa/drivers/dri/i965/brw_fs_combine_constants.cpp index c5280ac..9141907 100644 --- a/src

[Mesa-dev] [PATCH 2/2] i965/fs: Skip assertion on NaN.

A shader in Unreal4 uses the result of divide by zero in its color output, producing NaN and triggering this assertion since NaN is not equal to itself. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=93560 --- src/mesa/drivers/dri/i965/brw_fs_combine_constants.cpp | 2 +- 1 file changed,

Re: [Mesa-dev] [PATCH] nir: special hack for TGSI vs indirect inputs

On Mon, Jan 11, 2016 at 6:07 PM, Rob Clark wrote: > Quite possibly I am.. although wouldn't I still have the same issue > with other state trackers? So in that case I'd have to detect > indirect access, but without ArrayID's, and still set this flag. Yes, PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RAN

Re: [Mesa-dev] [PATCH 7/9] gallium: add a way to store query result into buffer

On 10.01.2016 00:14, Ilia Mirkin wrote: Signed-off-by: Ilia Mirkin --- src/gallium/docs/source/context.rst | 5 + src/gallium/include/pipe/p_context.h | 24 src/gallium/include/pipe/p_defines.h | 2 ++ 3 files changed, 31 insertions(+) diff --git a/src/galli

Re: [Mesa-dev] [PATCH 9/9] st/mesa: add query buffer support

On 10.01.2016 00:14, Ilia Mirkin wrote: Signed-off-by: Ilia Mirkin --- src/mesa/state_tracker/st_cb_bufferobjects.c | 3 + src/mesa/state_tracker/st_cb_queryobj.c | 100 +- src/mesa/state_tracker/st_cb_texturebarrier.c | 3 + src/mesa/state_tracker/st_exte

Re: [Mesa-dev] [PATCH] nir: special hack for TGSI vs indirect inputs

On Mon, Jan 11, 2016 at 1:52 PM, Marek Olšák wrote: > On Mon, Jan 11, 2016 at 6:07 PM, Rob Clark wrote: >> Quite possibly I am.. although wouldn't I still have the same issue >> with other state trackers? So in that case I'd have to detect >> indirect access, but without ArrayID's, and still se

Re: [Mesa-dev] [PATCH 7/9] gallium: add a way to store query result into buffer

On Mon, Jan 11, 2016 at 1:53 PM, Nicolai Hähnle wrote: > On 10.01.2016 00:14, Ilia Mirkin wrote: >> >> Signed-off-by: Ilia Mirkin >> --- >> src/gallium/docs/source/context.rst | 5 + >> src/gallium/include/pipe/p_context.h | 24 >> src/gallium/include/pipe/p_def

Re: [Mesa-dev] [PATCH 3/9] mesa: Add QueryBuffer to context

On Sun, Jan 10, 2016 at 12:14:51AM -0500, Ilia Mirkin wrote: > From: Rafal Mielniczuk > > Add QueryBuffer and initialise it to NullBufferObj on start > > Signed-off-by: Rafal Mielniczuk > [imirkin: also release QueryBuffer on free] > Signed-off-by: Ilia Mirkin > --- > src/mesa/main/bufferobj.

Re: [Mesa-dev] [PATCH 3/9] mesa: Add QueryBuffer to context

On Mon, Jan 11, 2016 at 2:07 PM, Nanley Chery wrote: > On Sun, Jan 10, 2016 at 12:14:51AM -0500, Ilia Mirkin wrote: >> From: Rafal Mielniczuk >> >> Add QueryBuffer and initialise it to NullBufferObj on start >> >> Signed-off-by: Rafal Mielniczuk >> [imirkin: also release QueryBuffer on free] >>

Re: [Mesa-dev] [PATCH 7/9] gallium: add a way to store query result into buffer

On 11.01.2016 14:01, Ilia Mirkin wrote: On Mon, Jan 11, 2016 at 1:53 PM, Nicolai Hähnle wrote: On 10.01.2016 00:14, Ilia Mirkin wrote: Signed-off-by: Ilia Mirkin --- src/gallium/docs/source/context.rst | 5 + src/gallium/include/pipe/p_context.h | 24 sr

Re: [Mesa-dev] [PATCH] Add missing platform information for KBL

On Sat, Jan 09, 2016 at 11:57:38AM -0800, Kristian Høgsberg Kristensen wrote: > Mark Janes writes: > > > Sarah Sharp writes: > > > >> On Fri, Jan 08, 2016 at 04:30:20PM -0800, Mark Janes wrote: > >>> In testing KBL, I found: > >>> > >>> - urb size was not set for slices gt1.5, gt2, and gt3. T

Re: [Mesa-dev] [PATCH] Add missing platform information for KBL

On Mon, Jan 11, 2016 at 11:23 AM Sarah Sharp wrote: > On Sat, Jan 09, 2016 at 11:57:38AM -0800, Kristian Høgsberg Kristensen > wrote: > > Mark Janes writes: > > > > > Sarah Sharp writes: > > > > > >> On Fri, Jan 08, 2016 at 04:30:20PM -0800, Mark Janes wrote: > > >>> In testing KBL, I found: >

[Mesa-dev] [PATCH v2] Add missing platform information for KBL

From: Mark Janes In testing KBL, I found: - urb size was not set for slices gt1.5, gt2, and gt3. The value I used for these slices (384) was taken from an earlier patch authored by Ben Widawsky. - slice count was missing. This field was added by a403ad4f5a034e52a3cd845e91c4aa3e6927

Re: [Mesa-dev] [PATCH 7/9] gallium: add a way to store query result into buffer

On Mon, Jan 11, 2016 at 2:21 PM, Nicolai Hähnle wrote: > On 11.01.2016 14:01, Ilia Mirkin wrote: >> >> On Mon, Jan 11, 2016 at 1:53 PM, Nicolai Hähnle >> wrote: >>> >>> On 10.01.2016 00:14, Ilia Mirkin wrote: Signed-off-by: Ilia Mirkin --- src/gallium/docs/source/cont

Re: [Mesa-dev] [PATCH 7/9] gallium: add a way to store query result into buffer

On 11.01.2016 14:30, Ilia Mirkin wrote: On Mon, Jan 11, 2016 at 2:21 PM, Nicolai Hähnle wrote: On 11.01.2016 14:01, Ilia Mirkin wrote: On Mon, Jan 11, 2016 at 1:53 PM, Nicolai Hähnle wrote: On 10.01.2016 00:14, Ilia Mirkin wrote: Signed-off-by: Ilia Mirkin --- src/gallium/docs/sour

Re: [Mesa-dev] [PATCH] mesa: check that internalformat of CopyTexImage*D is not 1, 2, 3, 4

On 11.01.2016 10:40, Erik Faye-Lund wrote: On Thu, Jan 7, 2016 at 11:49 PM, Ian Romanick wrote: On 01/07/2016 12:31 PM, Nicolai Hähnle wrote: From: Nicolai Hähnle The piglit copyteximage check has recently been augmented to test this, but apparently it hasn't been fixed in Mesa so far. ---

Re: [Mesa-dev] [PATCH v2] Add missing platform information for KBL

Thanks Sarah. I'll turn on KBL testing in the CI. Sarah Sharp writes: > From: Mark Janes > > In testing KBL, I found: > > - urb size was not set for slices gt1.5, gt2, and gt3. The value I >used for these slices (384) was taken from an earlier patch authored >by Ben Widawsky. > > -

Re: [Mesa-dev] [PATCH] nir: special hack for TGSI vs indirect inputs

On Mon, Jan 11, 2016 at 8:00 PM, Rob Clark wrote: > On Mon, Jan 11, 2016 at 1:52 PM, Marek Olšák wrote: >> On Mon, Jan 11, 2016 at 6:07 PM, Rob Clark wrote: >>> Quite possibly I am.. although wouldn't I still have the same issue >>> with other state trackers? So in that case I'd have to detect

[Mesa-dev] [PATCH] configure.ac: always define __STDC_CONSTANT_MACROS

The ISO C99 standard (7.18.4) specifies that C++ implementations should define UINT64_C only when __STDC_CONSTANT_MACROS is defined. ecause we now use UINT64_C in our cpp files (since commit 208bfc493debe0344d0b9cb93975981f14412628), we need to add this define. This also solves compilation errors

Re: [Mesa-dev] [PATCH] configure.ac: always define __STDC_CONSTANT_MACROS

I'm not strictly opposed to passing this in, but... why not just fix it by removing that imho weird macro and instead use ULL suffix on literals? On Mon, Jan 11, 2016 at 4:07 PM, Oded Gabbay wrote: > The ISO C99 standard (7.18.4) specifies that C++ > implementations should define UINT64_C only wh

Re: [Mesa-dev] [PATCH] configure.ac: always define __STDC_CONSTANT_MACROS

On Mon, Jan 11, 2016 at 11:09 PM, Ilia Mirkin wrote: > I'm not strictly opposed to passing this in, but... why not just fix > it by removing that imho weird macro and instead use ULL suffix on > literals? Well, I thought about it, but because I didn't add that macro to the code, I wanted a solutio

Re: [Mesa-dev] [PATCH] configure.ac: always define __STDC_CONSTANT_MACROS

On 11/01/16 21:07, Oded Gabbay wrote: The ISO C99 standard (7.18.4) specifies that C++ implementations should define UINT64_C only when __STDC_CONSTANT_MACROS is defined. ecause we now use UINT64_C in our cpp files (since commit 208bfc493debe0344d0b9cb93975981f14412628), we need to add this defi

Re: [Mesa-dev] [PATCH] configure.ac: always define __STDC_CONSTANT_MACROS

On Mon, Jan 11, 2016 at 11:24 PM, Jose Fonseca wrote: > On 11/01/16 21:07, Oded Gabbay wrote: >> >> The ISO C99 standard (7.18.4) specifies that C++ >> implementations should define UINT64_C only when >> __STDC_CONSTANT_MACROS is defined. >> >> ecause we now use UINT64_C in our cpp files (since co

[Mesa-dev] [PATCH] nvc0: allow fragment shader inputs to use indirect indexing

Signed-off-by: Ilia Mirkin --- src/gallium/drivers/nouveau/nvc0/nvc0_screen.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/gallium/drivers/nouveau/nvc0/nvc0_screen.c b/src/gallium/drivers/nouveau/nvc0/nvc0_screen.c index 1f5e48e..e69e9cb 100644 --- a/src/gallium/driver

[Mesa-dev] [PATCH] nvc0/ir: be careful about propagating very large offsets into const load

Indirect constbuf indexing works by using very large offsets. However if an indirect constbuf index load is const-propagated, it becomes a very large const offset. Take that into account when legalizing the SSA by moving the high parts of that offset into the file index. Also disallow very large (o

Re: [Mesa-dev] [PATCH] glsl: track total amount of uniform locations used

On Mon, 2016-01-11 at 08:24 +0200, Tapani Pälli wrote: > > On 01/08/2016 11:32 AM, Tapani Pälli wrote: > > > > > > On 01/08/2016 11:17 AM, Timothy Arceri wrote: > > > On Fri, 2016-01-08 at 08:20 +0200, Tapani Pälli wrote: > > > > Linker missed a check for situation where we exceed max amount > >

[Mesa-dev] [PATCH 4/9] glsl, nir: Make ir_triop_bitfield_extract a vectorized operation.

From: Kenneth Graunke We would like to be able to combine result.x = bitfieldExtract(src0.x, src1.x, src2.x); result.y = bitfieldExtract(src0.y, src1.y, src2.y); result.z = bitfieldExtract(src0.z, src1.z, src2.z); result.w = bitfieldExtract(src0.w, src1.w, src2.w); into a single ive

[Mesa-dev] [PATCH 7/9] nir: Change bfm's semantics to match Intel/AMD/SM5.

Intel/AMD's hardware instructions do not handle arguments of 32. Constant evaluation should not produce a result different from the hardware instruction. --- src/glsl/nir/nir_opcodes.py | 9 ++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/src/glsl/nir/nir_opcodes.py b/src/g

[Mesa-dev] [PATCH 2/9] glsl: Delete the ir_binop_bfm and ir_triop_bfi opcodes.

From: Kenneth Graunke TGSI doesn't use these - it just translates ir_quadop_bitfield_insert directly. NIR can handle ir_quadop_bitfield_insert as well. These opcodes were only used for i965, and with Jason's recent patches, we can do this lowering in NIR (which also gains us SPIR-V handling). S

[Mesa-dev] [PATCH 5/9] glsl: Handle failure of Python codegen scripts.

If a Python codegen script failed, it would write a zero-byte file, which on subsequent invocations of make would trick it into thinking the file was appropriately generated. --- src/glsl/Makefile.am | 10 +- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/src/glsl/Makefile.a

[Mesa-dev] [PATCH 3/9] glsl, nir: Make ir_quadop_bitfield_insert a vectorized operation.

From: Kenneth Graunke We would like to be able to combine result.x = bitfieldInsert(src0.x, src1.x, src2.x, src3.x); result.y = bitfieldInsert(src0.y, src1.y, src2.y, src3.y); result.z = bitfieldInsert(src0.z, src1.z, src2.z, src3.z); result.w = bitfieldInsert(src0.w, src1.w, src2.w,

[Mesa-dev] [PATCH 9/9] i965: Use nir_fixup_bitfield_insert_extract().

Fixes: ES31-CTS.shader_bitfield_operation.bitfieldInsert.uint_2 ES31-CTS.shader_bitfield_operation.bitfieldInsert.uvec4_3 ES31-CTS.shader_bitfield_operation.bitfieldExtract.uvec3_0 Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=92595 --- src/mesa/drivers/dri/i965/brw_nir.c | 1 +

[Mesa-dev] [PATCH 1/9] nir: Fix constant evaluation of bfm.

NIR's bfm, like Intel/AMD's hardware instructions and GLSL IR's ir_binop_bfm takes as src0 and as src1. --- src/glsl/nir/nir_opcodes.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/glsl/nir/nir_opcodes.py b/src/glsl/nir/nir_opcodes.py index d31507f..398ae50 100644 ---

[Mesa-dev] [PATCH 6/9] glsl: Fix undefined shifts.

Shifting into the sign bit if undefined, as is shifting by 32. Reviewed-by: Jordan Justen --- src/glsl/ir_constant_expression.cpp | 8 src/glsl/nir/nir_opcodes.py | 6 +++--- 2 files changed, 7 insertions(+), 7 deletions(-) diff --git a/src/glsl/ir_constant_expression.cpp b/sr

[Mesa-dev] [PATCH 8/9] nir: Add code to fixup bitfield_insert/extract.

The OpenGL specifications for bitfieldInsert() and bitfieldExtract() says: The result will be undefined if or is negative, or if the sum of and is greater than the number of bits used to store the operand. Therefore passing bits=32, offset=0 is legal and defined in GLSL. But the ear

Re: [Mesa-dev] [PATCH 0/2] trivial cleanups

On Mon, 2016-01-11 at 16:35 +0100, Erik Faye-Lund wrote: > Ping? > The other patch is also now Reviewed-by: Timothy Arceri I take it you don't have commit access? > On Wed, Dec 16, 2015 at 5:09 PM, Erik Faye-Lund > wrote: > > Here's some trivial cleanups I found while diving into something

Re: [Mesa-dev] [PATCH 0/2] trivial cleanups

On Mon, Jan 11, 2016 at 11:50 PM, Timothy Arceri wrote: > On Mon, 2016-01-11 at 16:35 +0100, Erik Faye-Lund wrote: >> Ping? >> > > The other patch is also now > Reviewed-by: Timothy Arceri > > I take it you don't have commit access? Thanks. Yeah, no commit access for me. If you could push it, th

Re: [Mesa-dev] [PATCH 3/9] glsl, nir: Make ir_quadop_bitfield_insert a vectorized operation.

On Mon, Jan 11, 2016 at 5:48 PM, Matt Turner wrote: > From: Kenneth Graunke > > We would like to be able to combine > >result.x = bitfieldInsert(src0.x, src1.x, src2.x, src3.x); >result.y = bitfieldInsert(src0.y, src1.y, src2.y, src3.y); >result.z = bitfieldInsert(src0.z, src1.z, src2

[Mesa-dev] [PATCH] i965: Mark TCS URB writes as having side effects.

This adds barrier dependencies around TCS_OPCODE_URB_WRITE, preventing reads and writes from being incorrectly scheduled. Fixes rendering in GFXBench 4.0's tessellation demo. For some reason, we haven't ever listed URB writes as having side-effects. This hasn't been a problem because in most sta

Re: [Mesa-dev] [PATCH] i965: Mark TCS URB writes as having side effects.

Reviewed-by: Chris Forbes On Tue, Jan 12, 2016 at 12:04 PM, Kenneth Graunke wrote: > This adds barrier dependencies around TCS_OPCODE_URB_WRITE, preventing > reads and writes from being incorrectly scheduled. > > Fixes rendering in GFXBench 4.0's tessellation demo. > > For some reason, we haven

Re: [Mesa-dev] [PATCH 02/18] mesa: Add _mesa_set_sampler_filters method

On 01/09/2016 12:49 PM, Jason Ekstrand wrote: > > On Jan 8, 2016 6:59 PM, "Ian Romanick" > wrote: >> >> From: Ian Romanick > >> >> Signed-off-by: Ian Romanick > >> --- >> src/mesa/main/samplerobj.c |

[Mesa-dev] [PATCH] nvc0: remove useless goto in nvc0_launch_grid()

Trivial. Signed-off-by: Samuel Pitoiset --- src/gallium/drivers/nouveau/nvc0/nvc0_compute.c | 10 -- 1 file changed, 4 insertions(+), 6 deletions(-) diff --git a/src/gallium/drivers/nouveau/nvc0/nvc0_compute.c b/src/gallium/drivers/nouveau/nvc0/nvc0_compute.c index 6ce96ae..795c027 100

Re: [Mesa-dev] [PATCH 3/9] glsl, nir: Make ir_quadop_bitfield_insert a vectorized operation.

On Mon, Jan 11, 2016 at 2:57 PM, Ilia Mirkin wrote: > On Mon, Jan 11, 2016 at 5:48 PM, Matt Turner wrote: >> From: Kenneth Graunke >> >> We would like to be able to combine >> >>result.x = bitfieldInsert(src0.x, src1.x, src2.x, src3.x); >>result.y = bitfieldInsert(src0.y, src1.y, src2.y,

Re: [Mesa-dev] [PATCH 3/9] glsl, nir: Make ir_quadop_bitfield_insert a vectorized operation.

On Mon, Jan 11, 2016 at 6:13 PM, Matt Turner wrote: > On Mon, Jan 11, 2016 at 2:57 PM, Ilia Mirkin wrote: >> On Mon, Jan 11, 2016 at 5:48 PM, Matt Turner wrote: >>> From: Kenneth Graunke >>> >>> We would like to be able to combine >>> >>>result.x = bitfieldInsert(src0.x, src1.x, src2.x, src

Re: [Mesa-dev] [PATCH] nvc0: remove useless goto in nvc0_launch_grid()

Reviewed-by: Ilia Mirkin On Mon, Jan 11, 2016 at 6:12 PM, Samuel Pitoiset wrote: > Trivial. > > Signed-off-by: Samuel Pitoiset > --- > src/gallium/drivers/nouveau/nvc0/nvc0_compute.c | 10 -- > 1 file changed, 4 insertions(+), 6 deletions(-) > > diff --git a/src/gallium/drivers/nouveau

Re: [Mesa-dev] [PATCH 07/18] meta/blit: Save and restore the sampler using gl_sampler_object instead of GL API object handle

On 01/09/2016 12:48 PM, Jason Ekstrand wrote: > > On Jan 8, 2016 6:59 PM, "Ian Romanick" > wrote: >> >> From: Ian Romanick > >> >> Some meta operations can be called recursively. Future changes (the >> "Don't pollute the ... namespac

Re: [Mesa-dev] [PATCH 3/9] glsl, nir: Make ir_quadop_bitfield_insert a vectorized operation.

On Mon, Jan 11, 2016 at 6:18 PM, Ilia Mirkin wrote: > On Mon, Jan 11, 2016 at 6:13 PM, Matt Turner wrote: >> On Mon, Jan 11, 2016 at 2:57 PM, Ilia Mirkin wrote: >>> On Mon, Jan 11, 2016 at 5:48 PM, Matt Turner wrote: From: Kenneth Graunke We would like to be able to combine

[Mesa-dev] [Bug 93673] New account request

https://bugs.freedesktop.org/show_bug.cgi?id=93673 Bug ID: 93673 Summary: New account request Product: Mesa Version: unspecified Hardware: Other OS: All Status: NEW Severity: normal Priority: med

[Mesa-dev] [Bug 93673] New account request

https://bugs.freedesktop.org/show_bug.cgi?id=93673 --- Comment #1 from Erik Faye-Lund --- Created attachment 120971 --> https://bugs.freedesktop.org/attachment.cgi?id=120971&action=edit SSH public key -- You are receiving this mail because: You are the QA Contact for the bug. You are the assi

[Mesa-dev] [Bug 93673] New account request

https://bugs.freedesktop.org/show_bug.cgi?id=93673 Ian Romanick changed: What|Removed |Added Status|NEW |ASSIGNED Assignee|mesa-dev@list

Re: [Mesa-dev] [PATCH 3/9] glsl, nir: Make ir_quadop_bitfield_insert a vectorized operation.

On Mon, Jan 11, 2016 at 3:25 PM, Ilia Mirkin wrote: > On Mon, Jan 11, 2016 at 6:18 PM, Ilia Mirkin wrote: >> On Mon, Jan 11, 2016 at 6:13 PM, Matt Turner wrote: >>> On Mon, Jan 11, 2016 at 2:57 PM, Ilia Mirkin wrote: On Mon, Jan 11, 2016 at 5:48 PM, Matt Turner wrote: > From: Kenneth

Re: [Mesa-dev] [PATCH] nvc0/ir: be careful about propagating very large offsets into const load

On Mon, Jan 11, 2016 at 4:46 PM, Ilia Mirkin wrote: > Indirect constbuf indexing works by using very large offsets. However if > an indirect constbuf index load is const-propagated, it becomes a very > large const offset. Take that into account when legalizing the SSA by > moving the high parts of

Re: [Mesa-dev] NIR, SCons, and Gallium

On 12 January 2016 at 03:04, Rob Clark wrote: > On Mon, Jan 11, 2016 at 9:21 AM, Jose Fonseca wrote: >> FWIW, I updated SCons to build NIR, both with GCC and MSVC: >> >> http://cgit.freedesktop.org/~jrfonseca/mesa/log/?h=scons-nir >> >> It was actually simpler than I anticipated. >> >> But I hi

[Mesa-dev] [PATCH] nvc0: do not force re-binding of compute constbufs on Fermi

Re-binding compute constant buffers after launching a grid have no effects because they are not currently validated and because dirty_cp is not updated accordingly. This might also prevent weird future behaviours when UBOs will be binded for compute. Signed-off-by: Samuel Pitoiset --- src/galliu

Re: [Mesa-dev] [PATCH] nvc0: do not force re-binding of compute constbufs on Fermi

On Mon, Jan 11, 2016 at 6:42 PM, Samuel Pitoiset wrote: > Re-binding compute constant buffers after launching a grid have no effects > because they are not currently validated and because dirty_cp is not updated > accordingly. This might also prevent weird future behaviours when UBOs will > be bin

[Mesa-dev] [Bug 93673] New account request

https://bugs.freedesktop.org/show_bug.cgi?id=93673 Brian Paul changed: What|Removed |Added Component|Other |New Accounts Product|Mesa

Re: [Mesa-dev] [PATCH 1/9] nir: Fix constant evaluation of bfm.

On 01/11/2016 02:48 PM, Matt Turner wrote: > NIR's bfm, like Intel/AMD's hardware instructions and GLSL IR's > ir_binop_bfm takes as src0 and as src1. All the questions... Is the ordering of the operands documented anywhere? I was only able to deduce this by looking at glsl_to_nir.cpp (and the

Re: [Mesa-dev] [PATCH 5/9] glsl: Handle failure of Python codegen scripts.

Yes, please! Reviewed-by: Ian Romanick On 01/11/2016 02:48 PM, Matt Turner wrote: > If a Python codegen script failed, it would write a zero-byte file, > which on subsequent invocations of make would trick it into thinking the > file was appropriately generated. > --- > src/glsl/Makefile.am | 1

Re: [Mesa-dev] NIR, SCons, and Gallium

On Mon, Jan 11, 2016 at 6:33 PM, Dave Airlie wrote: > On 12 January 2016 at 03:04, Rob Clark wrote: >> On Mon, Jan 11, 2016 at 9:21 AM, Jose Fonseca wrote: >>> FWIW, I updated SCons to build NIR, both with GCC and MSVC: >>> >>> http://cgit.freedesktop.org/~jrfonseca/mesa/log/?h=scons-nir >>> >

Re: [Mesa-dev] [PATCH 6/9] glsl: Fix undefined shifts.

On 01/11/2016 02:48 PM, Matt Turner wrote: > Shifting into the sign bit if undefined, as is shifting by 32. > > Reviewed-by: Jordan Justen > --- > src/glsl/ir_constant_expression.cpp | 8 > src/glsl/nir/nir_opcodes.py | 6 +++--- > 2 files changed, 7 insertions(+), 7 deletions(-

Re: [Mesa-dev] [PATCH 7/9] nir: Change bfm's semantics to match Intel/AMD/SM5.

On 01/11/2016 02:48 PM, Matt Turner wrote: > Intel/AMD's hardware instructions do not handle arguments of 32. > Constant evaluation should not produce a result different from the > hardware instruction. > --- > src/glsl/nir/nir_opcodes.py | 9 ++--- > 1 file changed, 6 insertions(+), 3 deletio

Re: [Mesa-dev] [PATCH 1/9] nir: Fix constant evaluation of bfm.

On Mon, Jan 11, 2016 at 3:52 PM, Ian Romanick wrote: > On 01/11/2016 02:48 PM, Matt Turner wrote: >> NIR's bfm, like Intel/AMD's hardware instructions and GLSL IR's >> ir_binop_bfm takes as src0 and as src1. > > All the questions... > > Is the ordering of the operands documented anywhere? I was

Re: [Mesa-dev] [PATCH 3/9] glsl, nir: Make ir_quadop_bitfield_insert a vectorized operation.

On Mon, Jan 11, 2016 at 3:33 PM, Matt Turner wrote: > Thanks. I apparently picked whatever tab completed first and was an > Snorm test, so it didn't trigger the assertion. > > I can reproduce this. I'll look into it. Okay, twas easy. Just needed to sprinkle 'u' around in a few places inside the i

Re: [Mesa-dev] NIR, SCons, and Gallium

On 01/11/2016 06:21 AM, Jose Fonseca wrote: > FWIW, I updated SCons to build NIR, both with GCC and MSVC: > > http://cgit.freedesktop.org/~jrfonseca/mesa/log/?h=scons-nir > > It was actually simpler than I anticipated. > > But I hit a wall -- there's actually no way to get NIR used with > soft

[Mesa-dev] [PATCHv3 3/9] glsl, nir: Make ir_quadop_bitfield_insert a vectorized operation.

From: Kenneth Graunke We would like to be able to combine result.x = bitfieldInsert(src0.x, src1.x, src2.x, src3.x); result.y = bitfieldInsert(src0.y, src1.y, src2.y, src3.y); result.z = bitfieldInsert(src0.z, src1.z, src2.z, src3.z); result.w = bitfieldInsert(src0.w, src1.w, src2.w,

[Mesa-dev] [PATCH] glsl, nir: Make ir_triop_bitfield_extract a vectorized operation.

From: Kenneth Graunke We would like to be able to combine result.x = bitfieldExtract(src0.x, src1.x, src2.x); result.y = bitfieldExtract(src0.y, src1.y, src2.y); result.z = bitfieldExtract(src0.z, src1.z, src2.z); result.w = bitfieldExtract(src0.w, src1.w, src2.w); into a single ive

Re: [Mesa-dev] [PATCH 7/9] nir: Change bfm's semantics to match Intel/AMD/SM5.

On Mon, Jan 11, 2016 at 4:01 PM, Ian Romanick wrote: > On 01/11/2016 02:48 PM, Matt Turner wrote: >> Intel/AMD's hardware instructions do not handle arguments of 32. >> Constant evaluation should not produce a result different from the >> hardware instruction. >> --- >> src/glsl/nir/nir_opcodes.p

[Mesa-dev] [PATCH] glsl: Make read_from_write_only_variable_visitor ignore .length().

.length() on an unsized SSBO variable doesn't actually read any data from the SSBO, and is allowed on variables marked 'writeonly'. Fixes compute shader compilation in Shadow of Mordor. Signed-off-by: Kenneth Graunke --- src/glsl/ast_to_hir.cpp | 9 + 1 file changed, 9 insertions(+) di

Re: [Mesa-dev] NIR, SCons, and Gallium

On 01/11/2016 04:11 PM, Ian Romanick wrote: > On 01/11/2016 06:21 AM, Jose Fonseca wrote: >> So what is exactly the long term plan for NIR in Mesa general, and >> Gallium in particular? >> - replace GLSL IR completely? > > Not likely. GLSL IR has a lot of GLSL-specific semantics that aren't > rea

Re: [Mesa-dev] [PATCH 7/9] nir: Change bfm's semantics to match Intel/AMD/SM5.

On 01/11/2016 04:14 PM, Matt Turner wrote: > On Mon, Jan 11, 2016 at 4:01 PM, Ian Romanick wrote: >> On 01/11/2016 02:48 PM, Matt Turner wrote: >>> Intel/AMD's hardware instructions do not handle arguments of 32. >>> Constant evaluation should not produce a result different from the >>> hardware i

Re: [Mesa-dev] [PATCH] glsl: Make read_from_write_only_variable_visitor ignore .length().

On Mon, Jan 11, 2016 at 4:15 PM, Kenneth Graunke wrote: > .length() on an unsized SSBO variable doesn't actually read any data > from the SSBO, and is allowed on variables marked 'writeonly'. > > Fixes compute shader compilation in Shadow of Mordor. > > Signed-off-by: Kenneth Graunke Reviewed-by

[Mesa-dev] [PATCH] st/mesa: fix incorrect buffer token passed to _mesa_BindFramebuffer()

I added this code right at the end, and got it wrong. Only used by the WGL_ARB_render_texture code. --- src/mesa/state_tracker/st_copytex.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/mesa/state_tracker/st_copytex.c b/src/mesa/state_tracker/st_copytex.c index d246d

[Mesa-dev] [PATCH 06/10] vbo: move vbo_get_minmax_indices into its own source file

From: Nicolai Hähnle We will add more code for caching/memoization. Moving the existing code into its own file helps keep things modular. Reviewed-by: Ian Romanick Reviewed-by: Marek Olšák --- src/mesa/Makefile.sources | 1 + src/mesa/vbo/vbo_exec_array.c | 148 -

[Mesa-dev] [PATCH 00/10] vbo: introduce a minmax_index cache (v3)

Hi, here is a new version of the series. I'm calling it v3 even though I never sent v2 because it contains v3 of the main patch. Changes relative to v1: - disable cache on USAGE_TEXTURE_BUFFER and bool/GLboolean nit - disable cache only temporarily when a persistent writable mapping exists - add

Re: [Mesa-dev] [PATCH] glsl, nir: Make ir_triop_bitfield_extract a vectorized operation.

Reviewed-by: Ilia Mirkin On Mon, Jan 11, 2016 at 7:13 PM, Matt Turner wrote: > From: Kenneth Graunke > > We would like to be able to combine > >result.x = bitfieldExtract(src0.x, src1.x, src2.x); >result.y = bitfieldExtract(src0.y, src1.y, src2.y); >result.z = bitfieldExtract(src0.z

[Mesa-dev] [PATCH 2/3] svga: add num-generate-mipmap HUD query

The actual increment of the num-generate-mipmap counter will be done in a subsequent patch when hw generate mipmap is supported. --- src/gallium/drivers/svga/svga_context.h| 4 +++- src/gallium/drivers/svga/svga_pipe_query.c | 7 +++ src/gallium/drivers/svga/svga_screen.c | 2 ++ 3 fil

[Mesa-dev] [PATCH 07/10] vbo: cache/memoize the result of vbo_get_minmax_indices (v3)

From: Nicolai Hähnle Some games developers are unaware that an index buffer in a VBO still needs to be read by the CPU if some varying data comes from a user pointer (unless glDrawRangeElements and friends are used). This is particularly bad when they tell us that the index buffer should live in

Re: [Mesa-dev] NIR, SCons, and Gallium

On Mon, Jan 11, 2016 at 7:11 PM, Ian Romanick wrote: > On 01/11/2016 06:21 AM, Jose Fonseca wrote: >> FWIW, I updated SCons to build NIR, both with GCC and MSVC: >> >> http://cgit.freedesktop.org/~jrfonseca/mesa/log/?h=scons-nir >> >> It was actually simpler than I anticipated. >> >> But I hit a

Re: [Mesa-dev] [PATCHv3 3/9] glsl, nir: Make ir_quadop_bitfield_insert a vectorized operation.

On Mon, Jan 11, 2016 at 7:12 PM, Matt Turner wrote: > From: Kenneth Graunke > > We would like to be able to combine > >result.x = bitfieldInsert(src0.x, src1.x, src2.x, src3.x); >result.y = bitfieldInsert(src0.y, src1.y, src2.y, src3.y); >result.z = bitfieldInsert(src0.z, src1.z, src2

[Mesa-dev] [PATCH] draw: fix key comparison with uninitialized value

From: Roland Scheidegger Discovered by accident, valgrind was complaining (could have possibly caused us to create redundant geometry shader variants). --- src/gallium/auxiliary/draw/draw_llvm.c | 3 +++ src/gallium/auxiliary/draw/draw_llvm.h | 5 + 2 files changed, 8 insertions(+) diff --g

Re: [Mesa-dev] [PATCH 5/9] glsl: Handle failure of Python codegen scripts.

Thanks! On Jan 11, 2016 3:57 PM, "Ian Romanick" wrote: > Yes, please! > > Reviewed-by: Ian Romanick > > On 01/11/2016 02:48 PM, Matt Turner wrote: > > If a Python codegen script failed, it would write a zero-byte file, > > which on subsequent invocations of make would trick it into thinking the

[Mesa-dev] [PATCH 09/10] vbo: disable the minmax cache when the hit rate is low

From: Nicolai Hähnle When applications stream their index buffers, the caches for those BOs become useless and add overhead, so we want to disable them. The tricky part is coming up with the right heuristic for *when* to disable them. The first question is which hit rate to aim for. Since I'm no

[Mesa-dev] [PATCH 05/10] mesa/main: bail earlier for size == 0 in _mesa_clear_buffer_sub_data

From: Nicolai Hähnle Note that the conversion of the clear data (when data != NULL) can fail due to an out of memory condition, but it does not check any error conditions mandated by the spec. Therefore, it is safe to skip when size == 0. Reviewed-by: Ian Romanick Reviewed-by: Marek Olšák ---

[Mesa-dev] [PATCH 01/10] util/hash_table: add _mesa_hash_table_clear

From: Nicolai Hähnle Reviewed-by: Ian Romanick --- src/util/hash_table.c | 25 ++ src/util/hash_table.h | 2 + src/util/tests/hash_table/Makefile.am | 1 + src/util/tests/hash_table/clear.c | 91 +++ 4 files changed,

[Mesa-dev] [PATCH 03/10] mesa/main: add USAGE_TRANSFORM_FEEDBACK_BUFFER flag to buffer UsageHistory

From: Nicolai Hähnle We will want to disable minmax index caching for buffers that are used in this way. Reviewed-by: Ian Romanick Reviewed-by: Marek Olšák --- src/mesa/main/mtypes.h| 1 + src/mesa/main/transformfeedback.h | 3 +++ 2 files changed, 4 insertions(+) diff --git a/sr

[Mesa-dev] [Bug 27512] Illegal instruction _mesa_x86_64_transform_points4_general

https://bugs.freedesktop.org/show_bug.cgi?id=27512 --- Comment #15 from Michael Harder --- It worked for a few days but now I get this: [Thread debugging using libthread_db enabled] Using host libthread_db library "/lib/x86_64-linux-gnu/libthread_db.so.1". Core was generated by `/usr/lib/x86_64-

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