Re: [Mesa-dev] [PATCH 1/3] mesa/main/shaderapi: Use generate_sha1() unconditionally

[Tapani Pälli]

On 05/17/2018 02:00 PM, Benedikt Schemmer wrote:

Ok I found the commit.
But it says: "Until we have a proper fix."
So this would be a good time I guess ;)


Agreed, using ENABLE_SHADER_CACHE to guard some OS specifics is dirty, 
it should be only guarding shader cache itself.




---

author  Emil Velikov  2017-01-18 19:40:31 +
committer   Emil Velikov    2017-01-18 20:09:01 
+
commit  9f8dc3bf03ec825bae7041858dda6ca2e9a34363 (patch)
treeff9672995474d3c31f027fea8356cb5733e45388
parent  d1efa09d342bff3e5def2978a0bef748d74f9c82 (diff)
utils: build sha1/disk cache only with Android/Autoconf
Earlier commit imported a SHA1 implementation and relaxed the SHA1 and
disk cache handling, broking the Windows builds.

Restrict things for now until we get to a proper fix.

Fixes: d1efa09d342 "util: import sha1 implementation from OpenBSD"
Signed-off-by: Emil Velikov 


Am 17.05.2018 um 12:28 schrieb Tapani Pälli:



On 05/17/2018 11:38 AM, Benedikt Schemmer wrote:

Thanks for reviewing!

Am 17.05.2018 um 08:42 schrieb Tapani Pälli:



On 05/10/2018 12:05 PM, Benedikt Schemmer wrote:

Move shader-cache code from back to front and make generate_sha1() usable
unconditionally to avoid code duplication in the following patch

---
    src/mesa/main/shaderapi.c | 228 
+++---
    1 file changed, 116 insertions(+), 112 deletions(-)

diff --git a/src/mesa/main/shaderapi.c b/src/mesa/main/shaderapi.c
index 44b18af492..e8acca4490 100644
--- a/src/mesa/main/shaderapi.c
+++ b/src/mesa/main/shaderapi.c
@@ -64,6 +64,122 @@
    #include "util/mesa-sha1.h"
    #include "util/crc32.h"

+
+/**
+ * Generate a SHA-1 hash value string for given source string.
+ */
+static void
+generate_sha1(const char *source, char sha_str[64])
+{
+   unsigned char sha[20];
+   _mesa_sha1_compute(source, strlen(source), sha);
+   _mesa_sha1_format(sha_str, sha);
+}


There is one potential problem here. The 'ENABLE_SHADER_CACHE' guard for 
generate_sha1 and others was placed there because the imported sha1 code broke 
windows build, I'm wondering if this is still
the case? If so, then generate_sha1 should be inside ENABLE_SHADER_CACHE guard.



I did a quick
gedit $(grep -Rlsi "_mesa_sha1_compute" | grep -E "\.c|\.h")

and it seems radv and anv use _mesa_sha1_compute (and _mesa_sha1_format) 
without a guard
best example from Intel seems to be brw_disk_cache.c which uses it alot outside 
of the ENABLE_SHADER_CACHE guard

so probably safe?


AFAIK none of those things are compiled on windows. IIUC windows builds are 
about Mesa core and gallium side.


+
+
+#ifdef ENABLE_SHADER_CACHE
+/**
+ * Construct a full path for shader replacement functionality using
+ * following format:
+ *
+ * /_.glsl
+ */
+static char *
+construct_name(const gl_shader_stage stage, const char *source,
+   const char *path)
+{
+   char sha[64];
+   static const char *types[] = {
+  "VS", "TC", "TE", "GS", "FS", "CS",
+   };
+
+   generate_sha1(source, sha);
+   return ralloc_asprintf(NULL, "%s/%s_%s.glsl", path, types[stage], sha);
+}
+
+/**
+ * Write given shader source to a file in MESA_SHADER_DUMP_PATH.
+ */
+static void
+dump_shader(const gl_shader_stage stage, const char *source)
+{
+   static bool path_exists = true;
+   char *dump_path;
+   FILE *f;
+
+   if (!path_exists)
+  return;
+
+   dump_path = getenv("MESA_SHADER_DUMP_PATH");
+   if (!dump_path) {
+  path_exists = false;
+  return;
+   }
+
+   char *name = construct_name(stage, source, dump_path);
+
+   f = fopen(name, "w");
+   if (f) {
+  fputs(source, f);
+  fclose(f);
+   } else {
+  GET_CURRENT_CONTEXT(ctx);
+  _mesa_warning(ctx, "could not open %s for dumping shader (%s)", name,
+    strerror(errno));
+   }
+   ralloc_free(name);
+}
+
+/**
+ * Read shader source code from a file.
+ * Useful for debugging to override an app's shader.
+ */
+static GLcharARB *
+read_shader(const gl_shader_stage stage, const char *source)
+{
+   char *read_path;
+   static bool path_exists = true;
+   int len, shader_size = 0;
+   GLcharARB *buffer;
+   FILE *f;
+
+   if (!path_exists)
+  return NULL;
+
+   read_path = getenv("MESA_SHADER_READ_PATH");
+   if (!read_path) {
+  path_exists = false;
+  return NULL;
+   }
+
+   char *name = construct_name(stage, source, read_path);
+   f = fopen(name, "r");
+   ralloc_free(name);
+   if (!f)
+  return NULL;
+
+   /* allocate enough room for the entire shader */
+   fseek(f, 0, SEEK_END);
+   shader_size = ftell(f);
+   rewind(f);
+   assert(shader_size);
+
+   /* add one for terminating zero */
+   shader_size++;
+
+   buffer = malloc(shader_size);
+   assert(buffer);
+
+   len = fread(buffer, 1, shader_size, f);
+   buffer[len] = 0;
+
+   fclose(f);
+
+   return buffer;
+}
+
+#endif /* ENABLE_SHADER_CACHE */
+
    /**
     * Return mask of GLSL_x flags by examining the 

Re: [Mesa-dev] [PATCH] vulkan: update vk_icd.h to current upstream

[Jason Ekstrand]

Acked-by: Jason Ekstrand 

On Thu, May 17, 2018 at 10:05 PM, Tapani Pälli 
wrote:

> Import from commit eb0c1fd on branch 'master'
> of https://github.com/KhronosGroup/Vulkan-Headers.git.
>
> Signed-off-by: Tapani Pälli 
> ---
>  include/vulkan/vk_icd.h | 67 ++
> ---
>  1 file changed, 53 insertions(+), 14 deletions(-)
>
> diff --git a/include/vulkan/vk_icd.h b/include/vulkan/vk_icd.h
> index 7b54fb5774..b935fa1786 100644
> --- a/include/vulkan/vk_icd.h
> +++ b/include/vulkan/vk_icd.h
> @@ -24,13 +24,34 @@
>  #define VKICD_H
>
>  #include "vulkan.h"
> -
> -/*
> - * Loader-ICD version negotiation API
> - */
> -#define CURRENT_LOADER_ICD_INTERFACE_VERSION 3
> +#include 
> +
> +// Loader-ICD version negotiation API.  Versions add the following
> features:
> +//   Version 0 - Initial.  Doesn't support vk_icdGetInstanceProcAddr
> +//   or vk_icdNegotiateLoaderICDInterfaceVersion.
> +//   Version 1 - Add support for vk_icdGetInstanceProcAddr.
> +//   Version 2 - Add Loader/ICD Interface version negotiation
> +//   via vk_icdNegotiateLoaderICDInterfaceVersion.
> +//   Version 3 - Add ICD creation/destruction of KHR_surface objects.
> +//   Version 4 - Add unknown physical device extension qyering via
> +//   vk_icdGetPhysicalDeviceProcAddr.
> +//   Version 5 - Tells ICDs that the loader is now paying attention to the
> +//   application version of Vulkan passed into the
> ApplicationInfo
> +//   structure during vkCreateInstance.  This will tell the
> ICD
> +//   that if the loader is older, it should automatically
> fail a
> +//   call for any API version > 1.0.  Otherwise, the loader
> will
> +//   manually determine if it can support the expected
> version.
> +#define CURRENT_LOADER_ICD_INTERFACE_VERSION 5
>  #define MIN_SUPPORTED_LOADER_ICD_INTERFACE_VERSION 0
> -typedef VkResult (VKAPI_PTR 
> *PFN_vkNegotiateLoaderICDInterfaceVersion)(uint32_t
> *pVersion);
> +#define MIN_PHYS_DEV_EXTENSION_ICD_INTERFACE_VERSION 4
> +typedef VkResult(VKAPI_PTR 
> *PFN_vkNegotiateLoaderICDInterfaceVersion)(uint32_t
> *pVersion);
> +
> +// This is defined in vk_layer.h which will be found by the loader, but
> if an ICD is building against this
> +// file directly, it won't be found.
> +#ifndef PFN_GetPhysicalDeviceProcAddr
> +typedef PFN_vkVoidFunction(VKAPI_PTR 
> *PFN_GetPhysicalDeviceProcAddr)(VkInstance
> instance, const char *pName);
> +#endif
> +
>  /*
>   * The ICD must reserve space for a pointer for the loader's dispatch
>   * table, at the start of .
> @@ -64,6 +85,9 @@ typedef enum {
>  VK_ICD_WSI_PLATFORM_WIN32,
>  VK_ICD_WSI_PLATFORM_XCB,
>  VK_ICD_WSI_PLATFORM_XLIB,
> +VK_ICD_WSI_PLATFORM_ANDROID,
> +VK_ICD_WSI_PLATFORM_MACOS,
> +VK_ICD_WSI_PLATFORM_IOS,
>  VK_ICD_WSI_PLATFORM_DISPLAY
>  } VkIcdWsiPlatform;
>
> @@ -77,7 +101,7 @@ typedef struct {
>  MirConnection *connection;
>  MirSurface *mirSurface;
>  } VkIcdSurfaceMir;
> -#endif // VK_USE_PLATFORM_MIR_KHR
> +#endif  // VK_USE_PLATFORM_MIR_KHR
>
>  #ifdef VK_USE_PLATFORM_WAYLAND_KHR
>  typedef struct {
> @@ -85,7 +109,7 @@ typedef struct {
>  struct wl_display *display;
>  struct wl_surface *surface;
>  } VkIcdSurfaceWayland;
> -#endif // VK_USE_PLATFORM_WAYLAND_KHR
> +#endif  // VK_USE_PLATFORM_WAYLAND_KHR
>
>  #ifdef VK_USE_PLATFORM_WIN32_KHR
>  typedef struct {
> @@ -93,7 +117,7 @@ typedef struct {
>  HINSTANCE hinstance;
>  HWND hwnd;
>  } VkIcdSurfaceWin32;
> -#endif // VK_USE_PLATFORM_WIN32_KHR
> +#endif  // VK_USE_PLATFORM_WIN32_KHR
>
>  #ifdef VK_USE_PLATFORM_XCB_KHR
>  typedef struct {
> @@ -101,7 +125,7 @@ typedef struct {
>  xcb_connection_t *connection;
>  xcb_window_t window;
>  } VkIcdSurfaceXcb;
> -#endif // VK_USE_PLATFORM_XCB_KHR
> +#endif  // VK_USE_PLATFORM_XCB_KHR
>
>  #ifdef VK_USE_PLATFORM_XLIB_KHR
>  typedef struct {
> @@ -109,13 +133,28 @@ typedef struct {
>  Display *dpy;
>  Window window;
>  } VkIcdSurfaceXlib;
> -#endif // VK_USE_PLATFORM_XLIB_KHR
> +#endif  // VK_USE_PLATFORM_XLIB_KHR
>
>  #ifdef VK_USE_PLATFORM_ANDROID_KHR
>  typedef struct {
> -ANativeWindow* window;
> +VkIcdSurfaceBase base;
> +struct ANativeWindow *window;
>  } VkIcdSurfaceAndroid;
> -#endif //VK_USE_PLATFORM_ANDROID_KHR
> +#endif  // VK_USE_PLATFORM_ANDROID_KHR
> +
> +#ifdef VK_USE_PLATFORM_MACOS_MVK
> +typedef struct {
> +VkIcdSurfaceBase base;
> +const void *pView;
> +} VkIcdSurfaceMacOS;
> +#endif  // VK_USE_PLATFORM_MACOS_MVK
> +
> +#ifdef VK_USE_PLATFORM_IOS_MVK
> +typedef struct {
> +VkIcdSurfaceBase base;
> +const void *pView;
> +} VkIcdSurfaceIOS;
> +#endif  // VK_USE_PLATFORM_IOS_MVK
>
>  typedef struct {
>  VkIcdSurfaceBase base;
> @@ -128,4 +167,4 @@ typedef struct {
>  VkExtent2D imageExtent;
>  } VkIcdSurfaceDisplay;
>
> -#endif // 

[Mesa-dev] [PATCH] vulkan: update vk_icd.h to current upstream

[Tapani Pälli]

Import from commit eb0c1fd on branch 'master'
of https://github.com/KhronosGroup/Vulkan-Headers.git.

Signed-off-by: Tapani Pälli 
---
 include/vulkan/vk_icd.h | 67 ++---
 1 file changed, 53 insertions(+), 14 deletions(-)

diff --git a/include/vulkan/vk_icd.h b/include/vulkan/vk_icd.h
index 7b54fb5774..b935fa1786 100644
--- a/include/vulkan/vk_icd.h
+++ b/include/vulkan/vk_icd.h
@@ -24,13 +24,34 @@
 #define VKICD_H
 
 #include "vulkan.h"
-
-/*
- * Loader-ICD version negotiation API
- */
-#define CURRENT_LOADER_ICD_INTERFACE_VERSION 3
+#include 
+
+// Loader-ICD version negotiation API.  Versions add the following features:
+//   Version 0 - Initial.  Doesn't support vk_icdGetInstanceProcAddr
+//   or vk_icdNegotiateLoaderICDInterfaceVersion.
+//   Version 1 - Add support for vk_icdGetInstanceProcAddr.
+//   Version 2 - Add Loader/ICD Interface version negotiation
+//   via vk_icdNegotiateLoaderICDInterfaceVersion.
+//   Version 3 - Add ICD creation/destruction of KHR_surface objects.
+//   Version 4 - Add unknown physical device extension qyering via
+//   vk_icdGetPhysicalDeviceProcAddr.
+//   Version 5 - Tells ICDs that the loader is now paying attention to the
+//   application version of Vulkan passed into the ApplicationInfo
+//   structure during vkCreateInstance.  This will tell the ICD
+//   that if the loader is older, it should automatically fail a
+//   call for any API version > 1.0.  Otherwise, the loader will
+//   manually determine if it can support the expected version.
+#define CURRENT_LOADER_ICD_INTERFACE_VERSION 5
 #define MIN_SUPPORTED_LOADER_ICD_INTERFACE_VERSION 0
-typedef VkResult (VKAPI_PTR 
*PFN_vkNegotiateLoaderICDInterfaceVersion)(uint32_t *pVersion);
+#define MIN_PHYS_DEV_EXTENSION_ICD_INTERFACE_VERSION 4
+typedef VkResult(VKAPI_PTR *PFN_vkNegotiateLoaderICDInterfaceVersion)(uint32_t 
*pVersion);
+
+// This is defined in vk_layer.h which will be found by the loader, but if an 
ICD is building against this
+// file directly, it won't be found.
+#ifndef PFN_GetPhysicalDeviceProcAddr
+typedef PFN_vkVoidFunction(VKAPI_PTR 
*PFN_GetPhysicalDeviceProcAddr)(VkInstance instance, const char *pName);
+#endif
+
 /*
  * The ICD must reserve space for a pointer for the loader's dispatch
  * table, at the start of .
@@ -64,6 +85,9 @@ typedef enum {
 VK_ICD_WSI_PLATFORM_WIN32,
 VK_ICD_WSI_PLATFORM_XCB,
 VK_ICD_WSI_PLATFORM_XLIB,
+VK_ICD_WSI_PLATFORM_ANDROID,
+VK_ICD_WSI_PLATFORM_MACOS,
+VK_ICD_WSI_PLATFORM_IOS,
 VK_ICD_WSI_PLATFORM_DISPLAY
 } VkIcdWsiPlatform;
 
@@ -77,7 +101,7 @@ typedef struct {
 MirConnection *connection;
 MirSurface *mirSurface;
 } VkIcdSurfaceMir;
-#endif // VK_USE_PLATFORM_MIR_KHR
+#endif  // VK_USE_PLATFORM_MIR_KHR
 
 #ifdef VK_USE_PLATFORM_WAYLAND_KHR
 typedef struct {
@@ -85,7 +109,7 @@ typedef struct {
 struct wl_display *display;
 struct wl_surface *surface;
 } VkIcdSurfaceWayland;
-#endif // VK_USE_PLATFORM_WAYLAND_KHR
+#endif  // VK_USE_PLATFORM_WAYLAND_KHR
 
 #ifdef VK_USE_PLATFORM_WIN32_KHR
 typedef struct {
@@ -93,7 +117,7 @@ typedef struct {
 HINSTANCE hinstance;
 HWND hwnd;
 } VkIcdSurfaceWin32;
-#endif // VK_USE_PLATFORM_WIN32_KHR
+#endif  // VK_USE_PLATFORM_WIN32_KHR
 
 #ifdef VK_USE_PLATFORM_XCB_KHR
 typedef struct {
@@ -101,7 +125,7 @@ typedef struct {
 xcb_connection_t *connection;
 xcb_window_t window;
 } VkIcdSurfaceXcb;
-#endif // VK_USE_PLATFORM_XCB_KHR
+#endif  // VK_USE_PLATFORM_XCB_KHR
 
 #ifdef VK_USE_PLATFORM_XLIB_KHR
 typedef struct {
@@ -109,13 +133,28 @@ typedef struct {
 Display *dpy;
 Window window;
 } VkIcdSurfaceXlib;
-#endif // VK_USE_PLATFORM_XLIB_KHR
+#endif  // VK_USE_PLATFORM_XLIB_KHR
 
 #ifdef VK_USE_PLATFORM_ANDROID_KHR
 typedef struct {
-ANativeWindow* window;
+VkIcdSurfaceBase base;
+struct ANativeWindow *window;
 } VkIcdSurfaceAndroid;
-#endif //VK_USE_PLATFORM_ANDROID_KHR
+#endif  // VK_USE_PLATFORM_ANDROID_KHR
+
+#ifdef VK_USE_PLATFORM_MACOS_MVK
+typedef struct {
+VkIcdSurfaceBase base;
+const void *pView;
+} VkIcdSurfaceMacOS;
+#endif  // VK_USE_PLATFORM_MACOS_MVK
+
+#ifdef VK_USE_PLATFORM_IOS_MVK
+typedef struct {
+VkIcdSurfaceBase base;
+const void *pView;
+} VkIcdSurfaceIOS;
+#endif  // VK_USE_PLATFORM_IOS_MVK
 
 typedef struct {
 VkIcdSurfaceBase base;
@@ -128,4 +167,4 @@ typedef struct {
 VkExtent2D imageExtent;
 } VkIcdSurfaceDisplay;
 
-#endif // VKICD_H
+#endif  // VKICD_H
-- 
2.14.3

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Re: [Mesa-dev] [PATCH] vbo: remove MaxVertexAttribStride assert check.

[Dave Airlie]

On 15 May 2018 at 16:31, Mathias Fröhlich  wrote:
> Hi Dave,
>
> On Tuesday, 15 May 2018 07:44:44 CEST Dave Airlie wrote:
>> From: Dave Airlie 
>>
>> Some drivers (virgl) don't support GL4.4 or GLES3.1 yet,
>> so never fill in this const.
>
> May be I should take care of all of these type of asserts, also the ones
> with MaxVertexAttribRelativeOffset and care for not checking them
> when the extension version is unavailable or checking against the OpenGL
> spec guaranteed minimum values for both constants instead of the actual ones.
> ... means, there are more asserts of this kind.
>
> Well, alternatively since you probably aim for supporting GL4.4 at one point, 
> you
> could alternatively set the constant already? AFAICT the
> PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE is only used to set the
> constant and does not imply anything beyond.

Well it's not just virgl, won't this break things like r300 and i915?

Dave.
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Re: [Mesa-dev] [PATCH 1/2] dri_util: Add R10G10B10{A, X}2 translation between DRI and mesa_format.

[Tapani Pälli]

Series
Reviewed-by: Tapani Pälli 

On 05/07/2018 06:45 PM, Miguel Casas wrote:

Add R10G10B10{A,X}2 translation between mesa_format and DRI format
to driGLFormatToImageFormat() and driImageFormatToGLFormat().

Bug: https://crbug.com/776093
---
  src/mesa/drivers/dri/common/dri_util.c | 8 
  1 file changed, 8 insertions(+)

diff --git a/src/mesa/drivers/dri/common/dri_util.c 
b/src/mesa/drivers/dri/common/dri_util.c
index 7cb6248b13..78c6bbf234 100644
--- a/src/mesa/drivers/dri/common/dri_util.c
+++ b/src/mesa/drivers/dri/common/dri_util.c
@@ -886,6 +886,10 @@ driGLFormatToImageFormat(mesa_format format)
return __DRI_IMAGE_FORMAT_ARGB2101010;
 case MESA_FORMAT_B10G10R10X2_UNORM:
return __DRI_IMAGE_FORMAT_XRGB2101010;
+   case MESA_FORMAT_R10G10B10A2_UNORM:
+  return __DRI_IMAGE_FORMAT_ABGR2101010;
+   case MESA_FORMAT_R10G10B10X2_UNORM:
+  return __DRI_IMAGE_FORMAT_XBGR2101010;
 case MESA_FORMAT_B8G8R8A8_UNORM:
return __DRI_IMAGE_FORMAT_ARGB;
 case MESA_FORMAT_R8G8B8A8_UNORM:
@@ -923,6 +927,10 @@ driImageFormatToGLFormat(uint32_t image_format)
return MESA_FORMAT_B10G10R10A2_UNORM;
 case __DRI_IMAGE_FORMAT_XRGB2101010:
return MESA_FORMAT_B10G10R10X2_UNORM;
+   case __DRI_IMAGE_FORMAT_ABGR2101010:
+  return MESA_FORMAT_R10G10B10A2_UNORM;
+   case __DRI_IMAGE_FORMAT_XBGR2101010:
+  return MESA_FORMAT_R10G10B10X2_UNORM;
 case __DRI_IMAGE_FORMAT_ARGB:
return MESA_FORMAT_B8G8R8A8_UNORM;
 case __DRI_IMAGE_FORMAT_ABGR:


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[Mesa-dev] [RFC PATCH] gallium: add interface for advanced MSAA

[Marek Olšák]

From: Marek Olšák 

The interface only uses general MSAA terms, so it's "advanced MSAA" and not
something vendor-specific.

It's a proper subset of EQAA, and a proper superset of CSAA, so it's neither.

Changes:
- pipe_resource is changed
- is_format_supported is changed
- a new CAP is added
---
 src/gallium/docs/source/screen.rst   | 31 ++--
 src/gallium/include/pipe/p_defines.h |  1 +
 src/gallium/include/pipe/p_screen.h  |  1 +
 src/gallium/include/pipe/p_state.h   | 18 +---
 4 files changed, 46 insertions(+), 5 deletions(-)

diff --git a/src/gallium/docs/source/screen.rst 
b/src/gallium/docs/source/screen.rst
index 5bc6ee99f08..cf4787a1c49 100644
--- a/src/gallium/docs/source/screen.rst
+++ b/src/gallium/docs/source/screen.rst
@@ -398,20 +398,25 @@ The integer capabilities:
 * ``PIPE_CAP_LOAD_CONSTBUF``: True if the driver supports TGSI_OPCODE_LOAD use
   with constant buffers.
 * ``PIPE_CAP_TGSI_ANY_REG_AS_ADDRESS``: Any TGSI register can be used as
   an address for indirect register indexing.
 * ``PIPE_CAP_TILE_RASTER_ORDER``: Whether the driver supports
   GL_MESA_tile_raster_order, using the tile_raster_order_* fields in
   pipe_rasterizer_state.
 * ``PIPE_CAP_MAX_COMBINED_SHADER_OUTPUT_RESOURCES``: Limit on combined shader
   output resources (images + buffers + fragment outputs). If 0 the state
   tracker works it out.
+* ``PIPE_CAP_FRAMEBUFFER_MIXED_SAMPLES``: Framebuffer attachments can have
+  different number of samples each with the following restriction:
+ color.nr_samples >= zs.nr_samples >= color.nr_storage_samples
+  If 0 is returned, the following restriction applies:
+ color.nr_samples == zs.nr_samples >= color.nr_storage_samples
 * ``PIPE_CAP_SIGNED_VERTEX_BUFFER_OFFSET``:
   Whether pipe_vertex_buffer::buffer_offset is treated as signed. The u_vbuf
   module needs this for optimal performance in workstation applications.
 * ``PIPE_CAP_CONTEXT_PRIORITY_MASK``: For drivers that support per-context
   priorities, this returns a bitmask of PIPE_CONTEXT_PRIORITY_x for the
   supported priority levels.  A driver that does not support prioritized
   contexts can return 0.
 * ``PIPE_CAP_FENCE_SIGNAL``: True if the driver supports signaling semaphores
   using fence_server_signal().
 * ``PIPE_CAP_CONSTBUF0_FLAGS``: The bits of pipe_resource::flags that must be
@@ -718,20 +723,23 @@ is_format_supported
 
 Determine if a resource in the given format can be used in a specific manner.
 
 **format** the resource format
 
 **target** one of the PIPE_TEXTURE_x flags
 
 **sample_count** the number of samples. 0 and 1 mean no multisampling,
 the maximum allowed legal value is 32.
 
+**storage_sample_count** the number of storage samples. This must be <=
+sample_count. See the documentation of ``pipe_resource::nr_storage_samples``.
+
 **bindings** is a bitmask of :ref:`PIPE_BIND` flags.
 
 Returns TRUE if all usages can be satisfied.
 
 
 can_create_resource
 ^^^
 
 Check if a resource can actually be created (but don't actually allocate any
 memory).  This is used to implement OpenGL's proxy textures.  Typically, a
@@ -761,22 +769,41 @@ Modern APIs allow using buffers as shader resources.
 (1 for 1D or 1D array textures).
 
 **depth0** the depth of the base mip level of the texture
 (1 for everything else).
 
 **array_size** the array size for 1D and 2D array textures.
 For cube maps this must be 6, for other textures 1.
 
 **last_level** the last mip map level present.
 
-**nr_samples** the nr of msaa samples. 0 (or 1) specifies a resource
-which isn't multisampled.
+**nr_samples**: Number of samples determining quality, driving the rasterizer,
+shading, and framebuffer. It is the number of samples seen by the whole
+graphics pipeline. 0 and 1 specify a resource which isn't multisampled.
+
+**nr_storage_samples**: Only color buffers can set this lower than nr_samples.
+Multiple samples within a pixel can have the same color. ``nr_storage_samples``
+determines how many slots for different colors there are per pixel.
+If there are not enough slots to store all sample colors, some samples will
+have an undefined color (called "undefined samples").
+
+The resolve blit behavior is driver-specific, but can be one of these two:
+1. Only defined samples will be averaged. Undefined samples will be ignored.
+2. Undefined samples will be approximated by looking at surrounding defined
+   samples (even in different pixels).
+
+Blits and MSAA texturing: If the sample being fetched is undefined, one of
+the defined samples is returned instead.
+
+Sample shading (``set_min_samples``) will operate at a sample frequency that
+is at most ``nr_storage_samples``. Greater ``min_samples`` values will be
+replaced by ``nr_storage_samples``.
 
 **usage** one of the :ref:`PIPE_USAGE` flags.
 
 **bind** bitmask of the :ref:`PIPE_BIND` flags.
 
 **flags** bitmask of PIPE_RESOURCE_FLAG flags.
 
 
 
 resource_changed
diff --git 

Re: [Mesa-dev] [PATCH] radeonsi: skip ES output stores for undefined output components

[Dieter Nützel]

Tested-by: Dieter Nützel 

on RX580

with UH, UV, glmark2, Blender 2.79, FreeCAD 0.17, Gimp 2.10, digikam 
5.9.0, Krita 4.0.3 and some Mesa-demos


Dieter

Am 18.05.2018 00:14, schrieb Marek Olšák:

From: Marek Olšák 

---
 src/gallium/drivers/radeonsi/si_shader.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/src/gallium/drivers/radeonsi/si_shader.c
b/src/gallium/drivers/radeonsi/si_shader.c
index e8d08cd8e7f..0d24c3af10a 100644
--- a/src/gallium/drivers/radeonsi/si_shader.c
+++ b/src/gallium/drivers/radeonsi/si_shader.c
@@ -3591,20 +3591,23 @@ static void si_llvm_emit_es_epilogue(struct
ac_shader_abi *abi,
int param;

if (info->output_semantic_name[i] == 
TGSI_SEMANTIC_VIEWPORT_INDEX ||
info->output_semantic_name[i] == TGSI_SEMANTIC_LAYER)
continue;

param = 
si_shader_io_get_unique_index(info->output_semantic_name[i],
  
info->output_semantic_index[i]);

for (chan = 0; chan < 4; chan++) {
+   if (!(info->output_usagemask[i] & (1 << chan)))
+   continue;
+
LLVMValueRef out_val = LLVMBuildLoad(ctx->ac.builder, 
addrs[4 * i
+ chan], "");
out_val = ac_to_integer(>ac, out_val);

/* GFX9 has the ESGS ring in LDS. */
if (ctx->screen->info.chip_class >= GFX9) {
lds_store(ctx, param * 4 + chan, lds_base, 
out_val);
continue;
}

ac_build_buffer_store_dword(>ac,

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Re: [Mesa-dev] [PATCH] draw: get rid of special logic to not emit null tris

[Dieter Nützel]

Tested-by: Dieter Nützel 

on RX580

with UH, UV, glmark2, Blender 2.79, FreeCAD 0.17, Gimp 2.10, digikam 
5.9.0, Krita 4.0.3 and some Mesa-demos


Dieter

Am 17.05.2018 18:30, schrieb srol...@vmware.com:

From: Roland Scheidegger 

I've confirmed after 77554d220d6d74b4d913dc37ea3a874e9dc550e4 we no
longer need this to pass some tests from another api (as we no longer
generate the bogus extra null tris in the first place).
---
 src/gallium/auxiliary/draw/draw_pipe_clip.c | 38 
-

 1 file changed, 38 deletions(-)

diff --git a/src/gallium/auxiliary/draw/draw_pipe_clip.c
b/src/gallium/auxiliary/draw/draw_pipe_clip.c
index 46118b6..2a9c944 100644
--- a/src/gallium/auxiliary/draw/draw_pipe_clip.c
+++ b/src/gallium/auxiliary/draw/draw_pipe_clip.c
@@ -210,30 +210,6 @@ static void interp(const struct clip_stage *clip,
 }

 /**
- * Checks whether the specified triangle is empty and if it is returns
- * true, otherwise returns false.
- * Triangle is considered null/empty if its area is equal to zero.
- */
-static inline boolean
-is_tri_null(const struct clip_stage *clip, const struct prim_header 
*header)

-{
-   const unsigned pos_attr = clip->pos_attr;
-   float x1 = header->v[1]->data[pos_attr][0] -
header->v[0]->data[pos_attr][0];
-   float y1 = header->v[1]->data[pos_attr][1] -
header->v[0]->data[pos_attr][1];
-   float z1 = header->v[1]->data[pos_attr][2] -
header->v[0]->data[pos_attr][2];
-
-   float x2 = header->v[2]->data[pos_attr][0] -
header->v[0]->data[pos_attr][0];
-   float y2 = header->v[2]->data[pos_attr][1] -
header->v[0]->data[pos_attr][1];
-   float z2 = header->v[2]->data[pos_attr][2] -
header->v[0]->data[pos_attr][2];
-
-   float vx = y1 * z2 - z1 * y2;
-   float vy = x1 * z2 - z1 * x2;
-   float vz = x1 * y2 - y1 * x2;
-
-   return (vx*vx  + vy*vy + vz*vz) == 0.f;
-}
-
-/**
  * Emit a post-clip polygon to the next pipeline stage.  The polygon
  * will be convex and the provoking vertex will always be vertex[0].
  */
@@ -247,7 +223,6 @@ static void emit_poly(struct draw_stage *stage,
struct prim_header header;
unsigned i;
ushort edge_first, edge_middle, edge_last;
-   boolean tri_emitted = FALSE;

if (stage->draw->rasterizer->flatshade_first) {
   edge_first  = DRAW_PIPE_EDGE_FLAG_0;
@@ -269,7 +244,6 @@ static void emit_poly(struct draw_stage *stage,
header.pad = 0;

for (i = 2; i < n; i++, header.flags = edge_middle) {
-  boolean tri_null;
   /* order the triangle verts to respect the provoking vertex mode 
*/

   if (stage->draw->rasterizer->flatshade_first) {
  header.v[0] = inlist[0];  /* the provoking vertex */
@@ -282,18 +256,6 @@ static void emit_poly(struct draw_stage *stage,
  header.v[2] = inlist[0];  /* the provoking vertex */
   }

-  tri_null = is_tri_null(clipper, );
-  /*
-   * If we ever generated a tri (regardless if it had area or 
not),

-   * skip all subsequent null tris.
-   * FIXME: I think this logic was hiding bugs elsewhere. It 
should

-   * be possible now to always emit all tris.
-   */
-  if (tri_null && tri_emitted) {
- continue;
-  }
-  tri_emitted = TRUE;
-
   if (!edgeflags[i-1]) {
  header.flags &= ~edge_middle;
   }

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Re: [Mesa-dev] [PATCH 6/6] radeonsi: set DB_EQAA.MAX_ANCHOR_SAMPLES correctly

[Dieter Nützel]

For the series:

Tested-by: Dieter Nützel 

on RX580

with UH, UV, glmark2, Blender 2.79, FreeCAD 0.17, Gimp 2.10, digikam 
5.9.0, Krita 4.0.3 and some Mesa-demos


Dieter

 17.05.2018 03:47, schrieb Marek Olšák:

From: Marek Olšák 

---
 src/gallium/drivers/radeonsi/si_state.c | 16 
 1 file changed, 12 insertions(+), 4 deletions(-)

diff --git a/src/gallium/drivers/radeonsi/si_state.c
b/src/gallium/drivers/radeonsi/si_state.c
index f4e29f68b29..3a7e928df53 100644
--- a/src/gallium/drivers/radeonsi/si_state.c
+++ b/src/gallium/drivers/radeonsi/si_state.c
@@ -,21 +,21 @@ static void si_emit_msaa_config(struct 
si_context *sctx)

S_028A4C_WALK_ALIGN8_PRIM_FITS_ST(1) |
S_028A4C_SUPERTILE_WALK_ORDER_ENABLE(1) |
S_028A4C_TILE_WALK_ORDER_ENABLE(1) |
S_028A4C_MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE(1) |
S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1) |
S_028A4C_FORCE_EOV_REZ_ENABLE(1);
unsigned db_eqaa = S_028804_HIGH_QUALITY_INTERSECTIONS(1) |
   S_028804_INCOHERENT_EQAA_READS(1) |
   S_028804_INTERPOLATE_COMP_Z(1) |
   S_028804_STATIC_ANCHOR_ASSOCIATIONS(1);
-   unsigned coverage_samples, color_samples;
+   unsigned coverage_samples, color_samples, z_samples;

/* S: Coverage samples (up to 16x):
 * - Scan conversion samples (PA_SC_AA_CONFIG.MSAA_NUM_SAMPLES)
 * - CB FMASK samples (CB_COLORi_ATTRIB.NUM_SAMPLES)
 *
 * Z: Z/S samples (up to 8x, must be <= coverage samples and >=
color samples):
 * - Value seen by DB (DB_Z_INFO.NUM_SAMPLES)
 * - Value seen by CB, must be correct even if Z/S is unbound
(DB_EQAA.MAX_ANCHOR_SAMPLES)
 * # Missing samples are derived from Z planes if Z is compressed
(up to 16x quality), or
 * # from the closest defined sample if Z is uncompressed (same
quality as the number of
@@ -3379,24 +3379,31 @@ static void si_emit_msaa_config(struct 
si_context *sctx)
 	 *   EQAA  8s 8z 2f - might look the same as 8x MSAA with low-density 
geometry
 	 *   EQAA  8s 4z 4f - might look the same as 8x MSAA if Z is 
compressed

 *   EQAA  8s 4z 2f - might look the same as 8x MSAA with
low-density geometry if Z is compressed
 *   EQAA  4s 4z 4f = 4x MSAA
 	 *   EQAA  4s 4z 2f - might look the same as 4x MSAA with low-density 
geometry

 *   EQAA  2s 2z 2f = 2x MSAA
 */
if (sctx->framebuffer.nr_samples > 1) {
coverage_samples = sctx->framebuffer.nr_samples;
color_samples = sctx->framebuffer.nr_color_samples;
+
+   if (sctx->framebuffer.state.zsbuf) {
+   z_samples = 
sctx->framebuffer.state.zsbuf->texture->nr_samples;
+   z_samples = MAX2(1, z_samples);
+   } else {
+   z_samples = coverage_samples;
+   }
} else if (sctx->smoothing_enabled) {
-   coverage_samples = color_samples = SI_NUM_SMOOTH_AA_SAMPLES;
+		coverage_samples = color_samples = z_samples = 
SI_NUM_SMOOTH_AA_SAMPLES;

} else {
-   coverage_samples = color_samples = 1;
+   coverage_samples = color_samples = z_samples = 1;
}

/* Required by OpenGL line rasterization.
 *
 * TODO: We should also enable perpendicular endcaps for AA lines,
 *   but that requires implementing line stippling in the pixel
 *   shader. SC can only do line stippling with axis-aligned
 *   endcaps.
 */
unsigned sc_line_cntl = S_028BDC_DX10_DIAMOND_TEST_ENA(1);
@@ -3404,34 +3411,35 @@ static void si_emit_msaa_config(struct 
si_context *sctx)

if (coverage_samples > 1) {
/* distance from the pixel center, indexed by log2(nr_samples) 
*/
static unsigned max_dist[] = {
0, /* unused */
4, /* 2x MSAA */
6, /* 4x MSAA */
7, /* 8x MSAA */
8, /* 16x MSAA */
};
unsigned log_samples = util_logbase2(coverage_samples);
+   unsigned log_z_samples = util_logbase2(z_samples);
unsigned ps_iter_samples = si_get_ps_iter_samples(sctx);
unsigned log_ps_iter_samples = util_logbase2(ps_iter_samples);

radeon_set_context_reg_seq(cs, R_028BDC_PA_SC_LINE_CNTL, 2);
radeon_emit(cs, sc_line_cntl |
S_028BDC_EXPAND_LINE_WIDTH(1)); /* 
R_028BDC_PA_SC_LINE_CNTL */
radeon_emit(cs, S_028BE0_MSAA_NUM_SAMPLES(log_samples) |
S_028BE0_MAX_SAMPLE_DIST(max_dist[log_samples]) |
S_028BE0_MSAA_EXPOSED_SAMPLES(log_samples)); /*

[Mesa-dev] [PATCH 1/1] travis: Adapt to radeonsi dropping support for LLVM 4

[Jan Vesely]

meson Vulkan, Clover, and autotools Vulkan need to be switched to llvm 5

Fixes: f9eb1ef870eba9fdacf9a8cbd815ec3bff81db05
Signed-off-by: Jan Vesely 
---
 .travis.yml | 14 +++---
 1 file changed, 7 insertions(+), 7 deletions(-)

diff --git a/.travis.yml b/.travis.yml
index c8b68a6696..e3471d47ac 100644
--- a/.travis.yml
+++ b/.travis.yml
@@ -34,17 +34,17 @@ matrix:
 - LABEL="meson Vulkan"
 - BUILD=meson
 - MESON_OPTIONS="-Ddri-drivers= -Dgallium-drivers="
-- LLVM_VERSION=4.0
+- LLVM_VERSION=5.0
 - LLVM_CONFIG="llvm-config-${LLVM_VERSION}"
   addons:
 apt:
   sources:
-- llvm-toolchain-trusty-4.0
+- llvm-toolchain-trusty-5.0
   packages:
 # LLVM packaging is broken and misses these dependencies
 - libedit-dev
 # From sources above
-- llvm-4.0-dev
+- llvm-5.0-dev
 # Common
 - xz-utils
 - libexpat1-dev
@@ -231,7 +231,7 @@ matrix:
 - DRI_LOADERS="--disable-glx --disable-gbm --disable-egl"
 - DRI_DRIVERS=""
 - GALLIUM_ST="--disable-dri --enable-opencl --enable-opencl-icd 
--enable-llvm --disable-xa --disable-nine --disable-xvmc --disable-vdpau 
--disable-va --disable-omx-bellagio --disable-gallium-osmesa"
-- GALLIUM_DRIVERS="r600,radeonsi"
+- GALLIUM_DRIVERS="r600"
 - VULKAN_DRIVERS=""
 - LIBUNWIND_FLAGS="--enable-libunwind"
   addons:
@@ -331,7 +331,7 @@ matrix:
 - BUILD=make
 - MAKEFLAGS="-j4"
 - MAKE_CHECK_COMMAND="make -C src/gtest check && make -C src/intel 
check"
-- LLVM_VERSION=4.0
+- LLVM_VERSION=5.0
 - LLVM_CONFIG="llvm-config-${LLVM_VERSION}"
 - DRI_LOADERS="--disable-glx --disable-gbm --disable-egl 
--with-platforms=x11,wayland"
 - DRI_DRIVERS=""
@@ -342,12 +342,12 @@ matrix:
   addons:
 apt:
   sources:
-- llvm-toolchain-trusty-4.0
+- llvm-toolchain-trusty-5.0
   packages:
 # LLVM packaging is broken and misses these dependencies
 - libedit-dev
 # From sources above
-- llvm-4.0-dev
+- llvm-5.0-dev
 # Common
 - xz-utils
 - x11proto-xf86vidmode-dev
-- 
2.17.0

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[Mesa-dev] [PATCH 1/2] r600/compute: Remove unused compute_memory_pool functions

[Aaron Watry]

Signed-off-by: Aaron Watry 
---
 .../drivers/r600/compute_memory_pool.c| 92 ---
 .../drivers/r600/compute_memory_pool.h| 11 ---
 2 files changed, 103 deletions(-)

diff --git a/src/gallium/drivers/r600/compute_memory_pool.c 
b/src/gallium/drivers/r600/compute_memory_pool.c
index 4b0e0044f5..d1ef25ae1e 100644
--- a/src/gallium/drivers/r600/compute_memory_pool.c
+++ b/src/gallium/drivers/r600/compute_memory_pool.c
@@ -101,83 +101,6 @@ void compute_memory_pool_delete(struct 
compute_memory_pool* pool)
free(pool);
 }
 
-/**
- * Searches for an empty space in the pool, return with the pointer to the
- * allocatable space in the pool.
- * \param size_in_dw   The size of the space we are looking for.
- * \return -1 on failure
- */
-int64_t compute_memory_prealloc_chunk(
-   struct compute_memory_pool* pool,
-   int64_t size_in_dw)
-{
-   struct compute_memory_item *item;
-
-   int last_end = 0;
-
-   assert(size_in_dw <= pool->size_in_dw);
-
-   COMPUTE_DBG(pool->screen, "* compute_memory_prealloc_chunk() size_in_dw 
= %"PRIi64"\n",
-   size_in_dw);
-
-   LIST_FOR_EACH_ENTRY(item, pool->item_list, link) {
-   if (last_end + size_in_dw <= item->start_in_dw) {
-   return last_end;
-   }
-
-   last_end = item->start_in_dw + align(item->size_in_dw, 
ITEM_ALIGNMENT);
-   }
-
-   if (pool->size_in_dw - last_end < size_in_dw) {
-   return -1;
-   }
-
-   return last_end;
-}
-
-/**
- *  Search for the chunk where we can link our new chunk after it.
- *  \param start_in_dw The position of the item we want to add to the pool.
- *  \return The item that is just before the passed position
- */
-struct list_head *compute_memory_postalloc_chunk(
-   struct compute_memory_pool* pool,
-   int64_t start_in_dw)
-{
-   struct compute_memory_item *item;
-   struct compute_memory_item *next;
-   struct list_head *next_link;
-
-   COMPUTE_DBG(pool->screen, "* compute_memory_postalloc_chunck() 
start_in_dw = %"PRIi64"\n",
-   start_in_dw);
-
-   /* Check if we can insert it in the front of the list */
-   item = LIST_ENTRY(struct compute_memory_item, pool->item_list->next, 
link);
-   if (LIST_IS_EMPTY(pool->item_list) || item->start_in_dw > start_in_dw) {
-   return pool->item_list;
-   }
-
-   LIST_FOR_EACH_ENTRY(item, pool->item_list, link) {
-   next_link = item->link.next;
-
-   if (next_link != pool->item_list) {
-   next = container_of(next_link, item, link);
-   if (item->start_in_dw < start_in_dw
-   && next->start_in_dw > start_in_dw) {
-   return >link;
-   }
-   }
-   else {
-   /* end of chain */
-   assert(item->start_in_dw < start_in_dw);
-   return >link;
-   }
-   }
-
-   assert(0 && "unreachable");
-   return NULL;
-}
-
 /**
  * Reallocates and defragments the pool, conserves data.
  * \returns -1 if it fails, 0 otherwise
@@ -686,18 +609,3 @@ void compute_memory_transfer(
pipe->transfer_unmap(pipe, xfer);
}
 }
-
-/**
- * Transfer data between chunk<->data, it is for VRAM<->GART transfers
- */
-void compute_memory_transfer_direct(
-   struct compute_memory_pool* pool,
-   int chunk_to_data,
-   struct compute_memory_item* chunk,
-   struct r600_resource* data,
-   int offset_in_chunk,
-   int offset_in_data,
-   int size)
-{
-   ///TODO: DMA
-}
diff --git a/src/gallium/drivers/r600/compute_memory_pool.h 
b/src/gallium/drivers/r600/compute_memory_pool.h
index 161ddd53ea..3a17c5176b 100644
--- a/src/gallium/drivers/r600/compute_memory_pool.h
+++ b/src/gallium/drivers/r600/compute_memory_pool.h
@@ -86,12 +86,6 @@ struct compute_memory_pool* compute_memory_pool_new(struct 
r600_screen *rscreen)
 
 void compute_memory_pool_delete(struct compute_memory_pool* pool);
 
-int64_t compute_memory_prealloc_chunk(struct compute_memory_pool* pool,
-   int64_t size_in_dw);
-
-struct list_head *compute_memory_postalloc_chunk(struct compute_memory_pool* 
pool,
-   int64_t start_in_dw);
-
 int compute_memory_grow_defrag_pool(struct compute_memory_pool* pool,
struct pipe_context *pipe, int new_size_in_dw);
 
@@ -127,9 +121,4 @@ void compute_memory_transfer(struct compute_memory_pool* 
pool,
struct compute_memory_item* chunk, void* data,
int offset_in_chunk, int size);
 
-void compute_memory_transfer_direct(struct compute_memory_pool* pool,
-   int chunk_to_data, struct compute_memory_item* chunk,
-   struct r600_resource* data, int offset_in_chunk,
-   int offset_in_data, int size);
-
 #endif
-- 
2.17.0

___

[Mesa-dev] [PATCH 2/2] r600/compute: Mark several functions as static

[Aaron Watry]

They're not used anywhere else, so keep them private

Signed-off-by: Aaron Watry 
---
 .../drivers/r600/compute_memory_pool.c| 35 +++
 .../drivers/r600/compute_memory_pool.h| 24 -
 2 files changed, 29 insertions(+), 30 deletions(-)

diff --git a/src/gallium/drivers/r600/compute_memory_pool.c 
b/src/gallium/drivers/r600/compute_memory_pool.c
index d1ef25ae1e..981d944b8d 100644
--- a/src/gallium/drivers/r600/compute_memory_pool.c
+++ b/src/gallium/drivers/r600/compute_memory_pool.c
@@ -43,6 +43,29 @@
 #include 
 
 #define ITEM_ALIGNMENT 1024
+
+/* A few forward declarations of static functions */
+static void compute_memory_shadow(struct compute_memory_pool* pool,
+   struct pipe_context *pipe, int device_to_host);
+
+static void compute_memory_defrag(struct compute_memory_pool *pool,
+   struct pipe_resource *src, struct pipe_resource *dst,
+   struct pipe_context *pipe);
+
+static int compute_memory_promote_item(struct compute_memory_pool *pool,
+   struct compute_memory_item *item, struct pipe_context *pipe,
+   int64_t allocated);
+
+static void compute_memory_move_item(struct compute_memory_pool *pool,
+   struct pipe_resource *src, struct pipe_resource *dst,
+   struct compute_memory_item *item, uint64_t new_start_in_dw,
+   struct pipe_context *pipe);
+
+static void compute_memory_transfer(struct compute_memory_pool* pool,
+   struct pipe_context * pipe, int device_to_host,
+   struct compute_memory_item* chunk, void* data,
+   int offset_in_chunk, int size);
+
 /**
  * Creates a new pool.
  */
@@ -106,7 +129,7 @@ void compute_memory_pool_delete(struct compute_memory_pool* 
pool)
  * \returns -1 if it fails, 0 otherwise
  * \see compute_memory_finalize_pending
  */
-int compute_memory_grow_defrag_pool(struct compute_memory_pool *pool,
+static int compute_memory_grow_defrag_pool(struct compute_memory_pool *pool,
struct pipe_context *pipe, int new_size_in_dw)
 {
new_size_in_dw = align(new_size_in_dw, ITEM_ALIGNMENT);
@@ -168,7 +191,7 @@ int compute_memory_grow_defrag_pool(struct 
compute_memory_pool *pool,
  * \param device_to_host 1 for device->host, 0 for host->device
  * \see compute_memory_grow_defrag_pool
  */
-void compute_memory_shadow(struct compute_memory_pool* pool,
+static void compute_memory_shadow(struct compute_memory_pool* pool,
struct pipe_context * pipe, int device_to_host)
 {
struct compute_memory_item chunk;
@@ -262,7 +285,7 @@ int compute_memory_finalize_pending(struct 
compute_memory_pool* pool,
  * \param dst  The destination resource
  * \see compute_memory_grow_defrag_pool and compute_memory_finalize_pending
  */
-void compute_memory_defrag(struct compute_memory_pool *pool,
+static void compute_memory_defrag(struct compute_memory_pool *pool,
struct pipe_resource *src, struct pipe_resource *dst,
struct pipe_context *pipe)
 {
@@ -292,7 +315,7 @@ void compute_memory_defrag(struct compute_memory_pool *pool,
  * \return -1 if it fails, 0 otherwise
  * \see compute_memory_finalize_pending
  */
-int compute_memory_promote_item(struct compute_memory_pool *pool,
+static int compute_memory_promote_item(struct compute_memory_pool *pool,
struct compute_memory_item *item, struct pipe_context *pipe,
int64_t start_in_dw)
 {
@@ -397,7 +420,7 @@ void compute_memory_demote_item(struct compute_memory_pool 
*pool,
  * \param new_start_in_dw  The new position of the item in \a item_list
  * \see compute_memory_defrag
  */
-void compute_memory_move_item(struct compute_memory_pool *pool,
+static void compute_memory_move_item(struct compute_memory_pool *pool,
struct pipe_resource *src, struct pipe_resource *dst,
struct compute_memory_item *item, uint64_t new_start_in_dw,
struct pipe_context *pipe)
@@ -569,7 +592,7 @@ struct compute_memory_item* compute_memory_alloc(
  * \param device_to_host 1 for device->host, 0 for host->device.
  * \see compute_memory_shadow
  */
-void compute_memory_transfer(
+static void compute_memory_transfer(
struct compute_memory_pool* pool,
struct pipe_context * pipe,
int device_to_host,
diff --git a/src/gallium/drivers/r600/compute_memory_pool.h 
b/src/gallium/drivers/r600/compute_memory_pool.h
index 3a17c5176b..2064e56352 100644
--- a/src/gallium/drivers/r600/compute_memory_pool.h
+++ b/src/gallium/drivers/r600/compute_memory_pool.h
@@ -86,39 +86,15 @@ struct compute_memory_pool* compute_memory_pool_new(struct 
r600_screen *rscreen)
 
 void compute_memory_pool_delete(struct compute_memory_pool* pool);
 
-int compute_memory_grow_defrag_pool(struct compute_memory_pool* pool,
-   struct pipe_context *pipe, int new_size_in_dw);
-
-void compute_memory_shadow(struct compute_memory_pool* pool,
-   struct pipe_context *pipe, int device_to_host);
-
 int compute_memory_finalize_pending(struct compute_memory_pool* pool,
struct 

Re: [Mesa-dev] [PATCH] Revert "st/nir: use NIR for asm programs"

[Timothy Arceri]

On 18/05/18 00:53, Eric Anholt wrote:

This reverts commit 5c33e8c7729edd5e16020ebb8703be96523e04f2.  It broke
fixed function vertex programs on vc4 and v3d, and apparently caused
trouble for radeonsi's NIR paths as well.


Has someone reported trouble with radeonsi NIR? I'm not aware of any 
issues. Dave's patch [1] was for fixing iris, I had no way to test so 
didn't try send it out myself after you confirmed it fixed your issue.


The only comment I have for the patch is that maybe we want:

ralloc_strdup(c->parameters, prog->Parameters->Parameters[0].Name);

rather than

strdup(prog->Parameters->Parameters[0].Name);

Otherwise it seems fine to me.

[1] 
https://cgit.freedesktop.org/~airlied/mesa/commit/?h=iris=00446d8b6b35f8bf0b491a4ad0359111f549ffdb

---
  src/mesa/state_tracker/st_program.c | 65 -
  1 file changed, 7 insertions(+), 58 deletions(-)

diff --git a/src/mesa/state_tracker/st_program.c 
b/src/mesa/state_tracker/st_program.c
index a7671b7fd1d8..8117f4ff8dbb 100644
--- a/src/mesa/state_tracker/st_program.c
+++ b/src/mesa/state_tracker/st_program.c
@@ -37,7 +37,6 @@
  #include "main/mtypes.h"
  #include "program/prog_parameter.h"
  #include "program/prog_print.h"
-#include "program/prog_to_nir.h"
  #include "program/programopt.h"
  
  #include "compiler/nir/nir.h"

@@ -378,28 +377,6 @@ st_release_cp_variants(struct st_context *st, struct 
st_compute_program *stcp)
 }
  }
  
-/**

- * Translate ARB (asm) program to NIR
- */
-static nir_shader *
-st_translate_prog_to_nir(struct st_context *st, struct gl_program *prog,
- gl_shader_stage stage)
-{
-   const struct gl_shader_compiler_options *options =
-  >ctx->Const.ShaderCompilerOptions[stage];
-
-   /* Translate to NIR */
-   nir_shader *nir = prog_to_nir(prog, options->NirOptions);
-   NIR_PASS_V(nir, nir_lower_regs_to_ssa); /* turn registers into SSA */
-   nir_validate_shader(nir);
-
-   /* Optimise NIR */
-   st_nir_opts(nir);
-   nir_validate_shader(nir);
-
-   return nir;
-}
-
  /**
   * Translate a vertex program.
   */
@@ -481,28 +458,15 @@ st_translate_vertex_program(struct st_context *st,
/* No samplers are allowed in ARB_vp. */
 }
  
-   enum pipe_shader_ir preferred_ir = (enum pipe_shader_ir)

-  st->pipe->screen->get_shader_param(st->pipe->screen, PIPE_SHADER_VERTEX,
- PIPE_SHADER_CAP_PREFERRED_IR);
-
-   if (preferred_ir == PIPE_SHADER_IR_NIR) {
-  if (stvp->shader_program) {
- struct gl_program *prog = stvp->shader_program->last_vert_prog;
- if (prog) {
-st_translate_stream_output_info2(prog->sh.LinkedTransformFeedback,
- stvp->result_to_output,
- >tgsi.stream_output);
- }
-
- st_store_ir_in_disk_cache(st, >Base, true);
-  } else {
- nir_shader *nir = st_translate_prog_to_nir(st, >Base,
-MESA_SHADER_VERTEX);
-
- stvp->tgsi.type = PIPE_SHADER_IR_NIR;
- stvp->tgsi.ir.nir = nir;
+   if (stvp->shader_program) {
+  struct gl_program *prog = stvp->shader_program->last_vert_prog;
+  if (prog) {
+ st_translate_stream_output_info2(prog->sh.LinkedTransformFeedback,
+  stvp->result_to_output,
+  >tgsi.stream_output);
}
  
+  st_store_ir_in_disk_cache(st, >Base, true);

return true;
 }
  
@@ -742,21 +706,6 @@ st_translate_fragment_program(struct st_context *st,

}
 }
  
-   enum pipe_shader_ir preferred_ir = (enum pipe_shader_ir)

-  st->pipe->screen->get_shader_param(st->pipe->screen,
- PIPE_SHADER_FRAGMENT,
- PIPE_SHADER_CAP_PREFERRED_IR);
-
-   if (preferred_ir == PIPE_SHADER_IR_NIR) {
-  nir_shader *nir = st_translate_prog_to_nir(st, >Base,
- MESA_SHADER_FRAGMENT);
-
-  stfp->tgsi.type = PIPE_SHADER_IR_NIR;
-  stfp->tgsi.ir.nir = nir;
-
-  return true;
-   }
-
 /*
  * Convert Mesa program inputs to TGSI input register semantics.
  */


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[Mesa-dev] [Bug 106556] Upgrade to 18.0 completely breaks gnome-shell

[bugzilla-daemon]

https://bugs.freedesktop.org/show_bug.cgi?id=106556

Timothy Arceri  changed:

   What|Removed |Added

 QA Contact|mesa-dev@lists.freedesktop. |intel-3d-bugs@lists.freedes
   |org |ktop.org
  Component|Mesa core   |Drivers/DRI/i965
   Assignee|mesa-dev@lists.freedesktop. |intel-3d-bugs@lists.freedes
   |org |ktop.org

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[Mesa-dev] [Bug 61761] glPolygonOffsetEXT, OFFSET_BIAS incorrectly set to a huge number

[bugzilla-daemon]

https://bugs.freedesktop.org/show_bug.cgi?id=61761

Timothy Arceri  changed:

   What|Removed |Added

 Status|NEW |RESOLVED
 Resolution|--- |FIXED

--- Comment #5 from Timothy Arceri  ---
Extension dropped with:

commit c0c69bd8ddf384379863d8b4bcbc670e86984ae5
Author: Timothy Arceri 
Date:   Fri May 11 15:33:22 2018 +1000

mesa: drop GL_EXT_polygon_offset support

glPolygonOffset() has been part of the GL standard since 1.1. Also
niether AMD or Nvidia support this in their binary drivers.

Reviewed-by: Marek Olšák 
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=61761

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[Mesa-dev] [PATCH] v3d: Include v3d_drm.h path.

[Vinson Lee]

Fix build error.

  CC   v3d_blit.lo
In file included from v3d_blit.c:27:0:
v3d_context.h:39:10: fatal error: v3d_drm.h: No such file or directory
 #include "v3d_drm.h"
  ^~~

Fixes: 8a793d42f1cc ("v3d: Switch the vc5 driver to using the finalized V3D 
UABI.")
Signed-off-by: Vinson Lee 
---
 src/gallium/drivers/v3d/Makefile.am | 1 +
 1 file changed, 1 insertion(+)

diff --git a/src/gallium/drivers/v3d/Makefile.am 
b/src/gallium/drivers/v3d/Makefile.am
index 2b4c364c24..ff0334a239 100644
--- a/src/gallium/drivers/v3d/Makefile.am
+++ b/src/gallium/drivers/v3d/Makefile.am
@@ -24,6 +24,7 @@ include $(top_srcdir)/src/gallium/Automake.inc
 
 AM_CFLAGS = \
-I$(top_builddir)/src/compiler/nir \
+   -I$(top_srcdir)/include/drm-uapi \
-I$(top_builddir)/src/broadcom \
$(LIBDRM_CFLAGS) \
$(V3D_SIMULATOR_CFLAGS) \
-- 
2.17.0

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[Mesa-dev] [Bug 106558] lower_x86.cpp:125:53: error: ‘x86_avx512_mask_permvar_sf_256’ is not a member of ‘llvm::Intrinsic’

[bugzilla-daemon]

https://bugs.freedesktop.org/show_bug.cgi?id=106558

Bug ID: 106558
   Summary: lower_x86.cpp:125:53: error:
‘x86_avx512_mask_permvar_sf_256’ is not a member of
‘llvm::Intrinsic’
   Product: Mesa
   Version: git
  Hardware: x86-64 (AMD64)
OS: All
Status: NEW
  Severity: normal
  Priority: medium
 Component: Drivers/Gallium/swr
  Assignee: mesa-dev@lists.freedesktop.org
  Reporter: v...@freedesktop.org
QA Contact: mesa-dev@lists.freedesktop.org

Build error after llvm-7.0.0svn r332170.

  CXX  rasterizer/jitter/functionpasses/libmesaswr_la-lower_x86.lo
rasterizer/jitter/functionpasses/lower_x86.cpp:125:53: error:
‘x86_avx512_mask_permvar_sf_256’ is not a member of ‘llvm::Intrinsic’
 {"meta.intrinsic.VPERMPS",
{{Intrinsic::x86_avx512_mask_permvar_sf_256, 
Intrinsic::x86_avx512_mask_permvar_sf_512}, NO_EMU}},

^~
rasterizer/jitter/functionpasses/lower_x86.cpp:125:53: note: suggested
alternative: ‘x86_avx512_mask_permvar_df_256’

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[Mesa-dev] [PATCH] radeonsi: skip ES output stores for undefined output components

[Marek Olšák]

From: Marek Olšák 

---
 src/gallium/drivers/radeonsi/si_shader.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/src/gallium/drivers/radeonsi/si_shader.c 
b/src/gallium/drivers/radeonsi/si_shader.c
index e8d08cd8e7f..0d24c3af10a 100644
--- a/src/gallium/drivers/radeonsi/si_shader.c
+++ b/src/gallium/drivers/radeonsi/si_shader.c
@@ -3591,20 +3591,23 @@ static void si_llvm_emit_es_epilogue(struct 
ac_shader_abi *abi,
int param;
 
if (info->output_semantic_name[i] == 
TGSI_SEMANTIC_VIEWPORT_INDEX ||
info->output_semantic_name[i] == TGSI_SEMANTIC_LAYER)
continue;
 
param = 
si_shader_io_get_unique_index(info->output_semantic_name[i],
  
info->output_semantic_index[i]);
 
for (chan = 0; chan < 4; chan++) {
+   if (!(info->output_usagemask[i] & (1 << chan)))
+   continue;
+
LLVMValueRef out_val = LLVMBuildLoad(ctx->ac.builder, 
addrs[4 * i + chan], "");
out_val = ac_to_integer(>ac, out_val);
 
/* GFX9 has the ESGS ring in LDS. */
if (ctx->screen->info.chip_class >= GFX9) {
lds_store(ctx, param * 4 + chan, lds_base, 
out_val);
continue;
}
 
ac_build_buffer_store_dword(>ac,
-- 
2.17.0

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Re: [Mesa-dev] [PATCH mesa] i965: Check result of make_surface() for miptree_create

[Nanley Chery]

On Thu, May 17, 2018 at 01:05:13PM +0100, Eric Engestrom wrote:
> From: Andrea Azzarone 
> 
> Since make_surface() can fail we need to check the result before 
> dereferencing it.
> 

This line should be wrapped to 75 characters or less
(see https://www.mesa3d.org/submittingpatches.html).

> Bug: https://github.com/mesa3d/mesa/pull/5
> Bug: https://bugs.launchpad.net/ubuntu/+source/gnome-shell/+bug/1760415

I'd also add

Fixes: 67b53ee4183 "i965: Represent depth surfaces with isl"

With those changes, this patch is
Reviewed-by: Nanley Chery 

> Reviewed-by: Eric Engestrom 
> ---
> Andrea: We don't use github, I only happened to notice your pull request :)
> Next time you want to send us something, send it here :P
> ---
>  src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 3 +++
>  1 file changed, 3 insertions(+)
> 
> diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c 
> b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
> index 67086ee6c0e8d6b6feb0..43687ea77abfe9989882 100644
> --- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
> +++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
> @@ -718,6 +718,9 @@ miptree_create(struct brw_context *brw,
>   ISL_SURF_USAGE_DEPTH_BIT | ISL_SURF_USAGE_TEXTURE_BIT,
>   BO_ALLOC_BUSY, 0, NULL);
>  
> +  if (!mt)
> + return NULL;
> +
>if (needs_separate_stencil(brw, mt, format) &&
>!make_separate_stencil_surface(brw, mt)) {
>   intel_miptree_release();
> -- 
> Cheers,
>   Eric
> 
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Re: [Mesa-dev] [Mesa-stable] [PATCH 01/17] i965/miptree: Fix handling of uninitialized MCS buffers

[Nanley Chery]

On Thu, May 17, 2018 at 09:25:18AM -0700, Dylan Baker wrote:
> Quoting Nanley Chery (2018-05-03 12:03:48)
> > Before this patch, if we failed to initialize an MCS buffer, we'd
> > end up in a state in which the miptree thinks it has an MCS buffer,
> > but doesn't. We also leaked the clear_color_bo if it existed.
> > 
> > With this patch, we now free the miptree aux buffer resources and let
> > intel_miptree_alloc_mcs() know that the MCS buffer no longer exists.
> > 
> > Cc: 
> > ---
> >  src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 14 +++---
> >  1 file changed, 7 insertions(+), 7 deletions(-)
> > 
> > diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c 
> > b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
> > index b9a564552df..377efae32c9 100644
> > --- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
> > +++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
> > @@ -1658,7 +1658,7 @@ intel_miptree_copy_teximage(struct brw_context *brw,
> > intel_obj->needs_validate = true;
> >  }
> >  
> > -static void
> > +static bool
> >  intel_miptree_init_mcs(struct brw_context *brw,
> > struct intel_mipmap_tree *mt,
> > int init_value)
> > @@ -1678,13 +1678,14 @@ intel_miptree_init_mcs(struct brw_context *brw,
> > void *map = brw_bo_map(brw, mt->aux_buf->bo, MAP_WRITE | MAP_RAW);
> > if (unlikely(map == NULL)) {
> >fprintf(stderr, "Failed to map mcs buffer into GTT\n");
> > -  brw_bo_unreference(mt->aux_buf->bo);
> > -  free(mt->aux_buf);
> > -  return;
> > +  intel_miptree_aux_buffer_free(mt->aux_buf);
> > +  mt->aux_buf = NULL;
> > +  return false;
> > }
> > void *data = map;
> > memset(data, init_value, mt->aux_buf->size);
> > brw_bo_unmap(mt->aux_buf->bo);
> > +   return true;
> >  }
> >  
> >  static struct intel_miptree_aux_buffer *
> > @@ -1764,15 +1765,14 @@ intel_miptree_alloc_mcs(struct brw_context *brw,
> > const uint32_t alloc_flags = 0;
> > mt->aux_buf = intel_alloc_aux_buffer(brw, "mcs-miptree",
> >  _mcs_surf, alloc_flags, mt);
> > -   if (!mt->aux_buf) {
> > +   if (!mt->aux_buf ||
> > +   !intel_miptree_init_mcs(brw, mt, 0xFF)) {
> >free(aux_state);
> >return false;
> > }
> >  
> > mt->aux_state = aux_state;
> >  
> > -   intel_miptree_init_mcs(brw, mt, 0xFF);
> > -
> > return true;
> >  }
> >  
> > -- 
> > 2.16.2
> > 
> > ___
> > mesa-stable mailing list
> > mesa-sta...@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/mesa-stable
> 
> 
> Hi Nanley,
> 
> Neither this patch or the next one cleanly apply to the 18.1 branch (or, I
> assume, 18.0), it looks like this depends on
> af4e9295febe966ace7793e43ba35705521749e8, which was not CC'd to stable. I'm 
> not
> sure how to resolve the rebase conflicts, what would you like to do?
> 

Hi Dylan,

I'd like to cherry-pick af4e9295febe966ace7793e43ba35705521749e8 and
it's parent for 18.1. We can ignore 18.0. Sorry for not checking on this
in advance.

-Nanley

> Dylan


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Re: [Mesa-dev] [PATCH] tgsi: fix incorrect tgsi_shader_info::num_tokens computation

[Roland Scheidegger]

Oh yes, that looks quite wrong.
Reviewed-by: Roland Scheidegger 

Am 17.05.2018 um 22:06 schrieb Brian Paul:
> We were incrementing num_tokens in each loop iteration while parsing
> the shader.  But each call to tgsi_parse_token() can consume more than
> one token (and often does).  Instead, just call the tgsi_num_tokens()
> function.
> 
> Luckily, this issue doesn't seem to effect any current users of this
> field (llvmpipe just checks for <= 1, for example).
> ---
>  src/gallium/auxiliary/tgsi/tgsi_scan.c | 3 +--
>  1 file changed, 1 insertion(+), 2 deletions(-)
> 
> diff --git a/src/gallium/auxiliary/tgsi/tgsi_scan.c 
> b/src/gallium/auxiliary/tgsi/tgsi_scan.c
> index 18488d7..685a413 100644
> --- a/src/gallium/auxiliary/tgsi/tgsi_scan.c
> +++ b/src/gallium/auxiliary/tgsi/tgsi_scan.c
> @@ -836,13 +836,12 @@ tgsi_scan_shader(const struct tgsi_token *tokens,
>procType == PIPE_SHADER_TESS_EVAL ||
>procType == PIPE_SHADER_COMPUTE);
> info->processor = procType;
> +   info->num_tokens = tgsi_num_tokens(parse.Tokens);
>  
> /**
>  ** Loop over incoming program tokens/instructions
>  */
> while (!tgsi_parse_end_of_tokens()) {
> -  info->num_tokens++;
> -
>tgsi_parse_token(  );
>  
>switch( parse.FullToken.Token.Type ) {
> 

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Re: [Mesa-dev] [PATCH] draw: get rid of special logic to not emit null tris

[Brian Paul]

On 05/17/2018 10:30 AM, srol...@vmware.com wrote:

From: Roland Scheidegger 

I've confirmed after 77554d220d6d74b4d913dc37ea3a874e9dc550e4 we no
longer need this to pass some tests from another api (as we no longer
generate the bogus extra null tris in the first place).
---
  src/gallium/auxiliary/draw/draw_pipe_clip.c | 38 -
  1 file changed, 38 deletions(-)

diff --git a/src/gallium/auxiliary/draw/draw_pipe_clip.c 
b/src/gallium/auxiliary/draw/draw_pipe_clip.c
index 46118b6..2a9c944 100644
--- a/src/gallium/auxiliary/draw/draw_pipe_clip.c
+++ b/src/gallium/auxiliary/draw/draw_pipe_clip.c
@@ -210,30 +210,6 @@ static void interp(const struct clip_stage *clip,
  }
  
  /**

- * Checks whether the specified triangle is empty and if it is returns
- * true, otherwise returns false.
- * Triangle is considered null/empty if its area is equal to zero.
- */
-static inline boolean
-is_tri_null(const struct clip_stage *clip, const struct prim_header *header)
-{
-   const unsigned pos_attr = clip->pos_attr;
-   float x1 = header->v[1]->data[pos_attr][0] - 
header->v[0]->data[pos_attr][0];
-   float y1 = header->v[1]->data[pos_attr][1] - 
header->v[0]->data[pos_attr][1];
-   float z1 = header->v[1]->data[pos_attr][2] - 
header->v[0]->data[pos_attr][2];
-
-   float x2 = header->v[2]->data[pos_attr][0] - 
header->v[0]->data[pos_attr][0];
-   float y2 = header->v[2]->data[pos_attr][1] - 
header->v[0]->data[pos_attr][1];
-   float z2 = header->v[2]->data[pos_attr][2] - 
header->v[0]->data[pos_attr][2];
-
-   float vx = y1 * z2 - z1 * y2;
-   float vy = x1 * z2 - z1 * x2;
-   float vz = x1 * y2 - y1 * x2;
-
-   return (vx*vx  + vy*vy + vz*vz) == 0.f;
-}
-
-/**
   * Emit a post-clip polygon to the next pipeline stage.  The polygon
   * will be convex and the provoking vertex will always be vertex[0].
   */
@@ -247,7 +223,6 @@ static void emit_poly(struct draw_stage *stage,
 struct prim_header header;
 unsigned i;
 ushort edge_first, edge_middle, edge_last;
-   boolean tri_emitted = FALSE;
  
 if (stage->draw->rasterizer->flatshade_first) {

edge_first  = DRAW_PIPE_EDGE_FLAG_0;
@@ -269,7 +244,6 @@ static void emit_poly(struct draw_stage *stage,
 header.pad = 0;
  
 for (i = 2; i < n; i++, header.flags = edge_middle) {

-  boolean tri_null;
/* order the triangle verts to respect the provoking vertex mode */
if (stage->draw->rasterizer->flatshade_first) {
   header.v[0] = inlist[0];  /* the provoking vertex */
@@ -282,18 +256,6 @@ static void emit_poly(struct draw_stage *stage,
   header.v[2] = inlist[0];  /* the provoking vertex */
}
  
-  tri_null = is_tri_null(clipper, );

-  /*
-   * If we ever generated a tri (regardless if it had area or not),
-   * skip all subsequent null tris.
-   * FIXME: I think this logic was hiding bugs elsewhere. It should
-   * be possible now to always emit all tris.
-   */
-  if (tri_null && tri_emitted) {
- continue;
-  }
-  tri_emitted = TRUE;
-
if (!edgeflags[i-1]) {
   header.flags &= ~edge_middle;
}



Reviewed-by: Brian Paul 
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Re: [Mesa-dev] [PATCH] tgsi: fix incorrect tgsi_shader_info::num_tokens computation

[Neha Bhende]

Reviewed-by: Neha Bhende


Regards,

Neha


From: Brian Paul 
Sent: Thursday, May 17, 2018 1:06:26 PM
To: mesa-dev@lists.freedesktop.org
Cc: Charmaine Lee; Neha Bhende; Roland Scheidegger
Subject: [PATCH] tgsi: fix incorrect tgsi_shader_info::num_tokens computation

We were incrementing num_tokens in each loop iteration while parsing
the shader.  But each call to tgsi_parse_token() can consume more than
one token (and often does).  Instead, just call the tgsi_num_tokens()
function.

Luckily, this issue doesn't seem to effect any current users of this
field (llvmpipe just checks for <= 1, for example).
---
 src/gallium/auxiliary/tgsi/tgsi_scan.c | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/src/gallium/auxiliary/tgsi/tgsi_scan.c 
b/src/gallium/auxiliary/tgsi/tgsi_scan.c
index 18488d7..685a413 100644
--- a/src/gallium/auxiliary/tgsi/tgsi_scan.c
+++ b/src/gallium/auxiliary/tgsi/tgsi_scan.c
@@ -836,13 +836,12 @@ tgsi_scan_shader(const struct tgsi_token *tokens,
   procType == PIPE_SHADER_TESS_EVAL ||
   procType == PIPE_SHADER_COMPUTE);
info->processor = procType;
+   info->num_tokens = tgsi_num_tokens(parse.Tokens);

/**
 ** Loop over incoming program tokens/instructions
 */
while (!tgsi_parse_end_of_tokens()) {
-  info->num_tokens++;
-
   tgsi_parse_token(  );

   switch( parse.FullToken.Token.Type ) {
--
2.7.4

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[Mesa-dev] [PATCH] tgsi: fix incorrect tgsi_shader_info::num_tokens computation

[Brian Paul]

We were incrementing num_tokens in each loop iteration while parsing
the shader.  But each call to tgsi_parse_token() can consume more than
one token (and often does).  Instead, just call the tgsi_num_tokens()
function.

Luckily, this issue doesn't seem to effect any current users of this
field (llvmpipe just checks for <= 1, for example).
---
 src/gallium/auxiliary/tgsi/tgsi_scan.c | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/src/gallium/auxiliary/tgsi/tgsi_scan.c 
b/src/gallium/auxiliary/tgsi/tgsi_scan.c
index 18488d7..685a413 100644
--- a/src/gallium/auxiliary/tgsi/tgsi_scan.c
+++ b/src/gallium/auxiliary/tgsi/tgsi_scan.c
@@ -836,13 +836,12 @@ tgsi_scan_shader(const struct tgsi_token *tokens,
   procType == PIPE_SHADER_TESS_EVAL ||
   procType == PIPE_SHADER_COMPUTE);
info->processor = procType;
+   info->num_tokens = tgsi_num_tokens(parse.Tokens);
 
/**
 ** Loop over incoming program tokens/instructions
 */
while (!tgsi_parse_end_of_tokens()) {
-  info->num_tokens++;
-
   tgsi_parse_token(  );
 
   switch( parse.FullToken.Token.Type ) {
-- 
2.7.4

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Re: [Mesa-dev] [PATCH] cmake: Bump minimum version to 3.2.

[Dylan Baker]

I think this is a reasonable thing to do, 3.2 is from early 2015, so it
shouldn't be too much to ask for.

Reviewed-by: Dylan Baker 

Quoting Vinson Lee (2018-05-17 11:37:12)
> This build error occurs with cmake 2.8.12.
> /bin/sh: BYPRODUCTS: command not found
> 
> BYPRODUCTS is not available until cmake 3.2.
> https://cmake.org/cmake/help/v3.2/release/3.2.html
> 
> Fixes: 2f02cf0d4c2d ("Generate xml for builtin profiles")
> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=106370
> Signed-off-by: Vinson Lee 
> ---
>  CMakeLists.txt |2 +-
>  1 files changed, 1 insertions(+), 1 deletions(-)
> 
> diff --git a/CMakeLists.txt b/CMakeLists.txt
> index 8c7d162..e56aafb 100644
> --- a/CMakeLists.txt
> +++ b/CMakeLists.txt
> @@ -1,4 +1,4 @@
> -cmake_minimum_required(VERSION 2.8.5)
> +cmake_minimum_required(VERSION 3.2)
>  
>  list(APPEND CMAKE_MODULE_PATH "${CMAKE_SOURCE_DIR}/cmake/Modules")
>  
> -- 
> 1.7.1
> 


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[Mesa-dev] [Bug 106556] Upgrade to 18.0 completely breaks gnome-shell

[bugzilla-daemon]

https://bugs.freedesktop.org/show_bug.cgi?id=106556

Bug ID: 106556
   Summary: Upgrade to 18.0 completely breaks gnome-shell
   Product: Mesa
   Version: 18.0
  Hardware: x86-64 (AMD64)
OS: Linux (All)
Status: NEW
  Severity: major
  Priority: medium
 Component: Mesa core
  Assignee: mesa-dev@lists.freedesktop.org
  Reporter: dustinbphi...@gmail.com
QA Contact: mesa-dev@lists.freedesktop.org

After upgrading to mesa 18.0, gnome-shell crashes immediately upon starting
(before the GDM login prompt). I'm running Arch Linux with Gnome 3.28 on a
Lenovo P51 with hybrid graphics. Here are the relevant bits from lspci:

01:00.0 3D controller: NVIDIA Corporation GM206GLM [Quadro M2200 Mobile] (rev
a1)
00:02.0 VGA compatible controller: Intel Corporation Device 591b (rev 04)

The following is a stack trace captured from journalctl:

May 17 11:34:07 bubo systemd-coredump[882]: Process 778 (gnome-shell) of user
120 dumped core.

Stack trace of thread 778:
#0  0x7f627934f860 raise
(libc.so.6)
#1  0x7f6279350ec9 abort
(libc.so.6)
#2  0x7f6279392437
__libc_message (libc.so.6)
#3  0x7f627939878b
malloc_printerr (libc.so.6)
#4  0x7f6279398c3c munmap_chunk
(libc.so.6)
#5  0x7f625267ee84 n/a
(i965_dri.so)
#6  0x7f62524ecad8 n/a
(i965_dri.so)
#7  0x7f6252595530 n/a
(i965_dri.so)
#8  0x7f6253ddce18 n/a
(libEGL_mesa.so.0)
#9  0x7f6253dd405b
eglCreateContext (libEGL_mesa.so.0)
#10 0x7f6275ba799e n/a
(libmutter-cogl-2.so)
#11 0x7f6275b5dcd6
cogl_display_setup (libmutter-cogl-2.so)
#12 0x7f6275b5d01b
cogl_renderer_check_onscreen_template (libmutter-cogl-2.so)
#13 0x7f62772af0ff n/a
(libmutter-clutter-2.so)
#14 0x7f62772c8765 n/a
(libmutter-clutter-2.so)
#15 0x7f62772dc6cb n/a
(libmutter-clutter-2.so)
#16 0x7f62772dc898 n/a
(libmutter-clutter-2.so)
#17 0x7f6278622aef
g_option_context_parse (libglib-2.0.so.0)
#18 0x7f62772dd6c5 clutter_init
(libmutter-clutter-2.so)
#19 0x7f6276ac9d78
meta_clutter_init (libmutter-2.so.0)
#20 0x7f6276b12e2e meta_init
(libmutter-2.so.0)
#21 0x56395e8aecda n/a
(gnome-shell)
#22 0x7f627933bf4a
__libc_start_main (libc.so.6)
#23 0x56395e8af14a n/a
(gnome-shell)

Stack trace of thread 806:
#0  0x7f627940697b __poll
(libc.so.6)
#1  0x7f6278616523 n/a
(libglib-2.0.so.0)
#2  0x7f627861663e
g_main_context_iteration (libglib-2.0.so.0)
#3  0x7f6278616692 n/a
(libglib-2.0.so.0)
#4  0x7f627863ea2a n/a
(libglib-2.0.so.0)
#5  0x7f62796d908c start_thread
(libpthread.so.0)
#6  0x7f6279410e7f __clone
(libc.so.6)

Stack trace of thread 871:
#0  0x7f627940697b __poll
(libc.so.6)
#1  0x7f6278616523 n/a
(libglib-2.0.so.0)
#2  0x7f627861663e
g_main_context_iteration (libglib-2.0.so.0)
#3  0x7f6260963f4e n/a
(libdconfsettings.so)
#4  0x7f627863ea2a n/a
(libglib-2.0.so.0)
#5  0x7f62796d908c start_thread
(libpthread.so.0)
#6  0x7f6279410e7f __clone
(libc.so.6)

Stack trace of thread 870:
#0  

Re: [Mesa-dev] [PATCH 2/2] radv: add radv_emit_shader_pointer() helper

[Samuel Pitoiset]

On 05/17/2018 04:31 PM, Bas Nieuwenhuizen wrote:

Do we want the new function inlined?


Yeah, we can inline it. 32-bit GPU pointers won't be too intrusive in 
this function.




Reviewed-by: Bas Nieuwenhuizen 

On Thu, May 17, 2018 at 2:16 PM, Samuel Pitoiset
 wrote:

For future work (support for 32-bit GPU pointers).

Signed-off-by: Samuel Pitoiset 
---
  src/amd/vulkan/radv_cmd_buffer.c | 13 ++---
  src/amd/vulkan/radv_device.c | 17 +++--
  src/amd/vulkan/radv_private.h|  3 +++
  3 files changed, 20 insertions(+), 13 deletions(-)

diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c
index 1ca687494a..a8359ac092 100644
--- a/src/amd/vulkan/radv_cmd_buffer.c
+++ b/src/amd/vulkan/radv_cmd_buffer.c
@@ -587,9 +587,9 @@ radv_emit_userdata_address(struct radv_cmd_buffer 
*cmd_buffer,
 return;
 assert(loc->num_sgprs == 2);
 assert(!loc->indirect);
-   radeon_set_sh_reg_seq(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, 2);
-   radeon_emit(cmd_buffer->cs, va);
-   radeon_emit(cmd_buffer->cs, va >> 32);
+
+   radv_emit_shader_pointer(cmd_buffer->cs,
+base_reg + loc->sgpr_idx * 4, va);
  }

  static void
@@ -1442,10 +1442,9 @@ emit_stage_descriptor_set_userdata(struct 
radv_cmd_buffer *cmd_buffer,

 assert(!desc_set_loc->indirect);
 assert(desc_set_loc->num_sgprs == 2);
-   radeon_set_sh_reg_seq(cmd_buffer->cs,
- base_reg + desc_set_loc->sgpr_idx * 4, 2);
-   radeon_emit(cmd_buffer->cs, va);
-   radeon_emit(cmd_buffer->cs, va >> 32);
+
+   radv_emit_shader_pointer(cmd_buffer->cs,
+base_reg + desc_set_loc->sgpr_idx * 4, va);
  }

  static void
diff --git a/src/amd/vulkan/radv_device.c b/src/amd/vulkan/radv_device.c
index fa07ec40f3..91ab729d86 100644
--- a/src/amd/vulkan/radv_device.c
+++ b/src/amd/vulkan/radv_device.c
@@ -1941,6 +1941,15 @@ radv_emit_compute_scratch(struct radv_queue *queue, 
struct radeon_winsys_cs *cs,
 S_008F04_SWIZZLE_ENABLE(1));
  }

+void
+radv_emit_shader_pointer(struct radeon_winsys_cs *cs,
+uint32_t sh_offset, uint64_t va)
+{
+   radeon_set_sh_reg_seq(cs, sh_offset, 2);
+   radeon_emit(cs, va);
+   radeon_emit(cs, va >> 32);
+}
+
  static void
  radv_emit_global_shader_pointers(struct radv_queue *queue,
  struct radeon_winsys_cs *cs,
@@ -1962,9 +1971,7 @@ radv_emit_global_shader_pointers(struct radv_queue *queue,
R_00B408_SPI_SHADER_USER_DATA_ADDR_LO_HS};

 for (int i = 0; i < ARRAY_SIZE(regs); ++i) {
-   radeon_set_sh_reg_seq(cs, regs[i], 2);
-   radeon_emit(cs, va);
-   radeon_emit(cs, va >> 32);
+   radv_emit_shader_pointer(cs, regs[i], va);
 }
 } else {
 uint32_t regs[] = {R_00B030_SPI_SHADER_USER_DATA_PS_0,
@@ -1975,9 +1982,7 @@ radv_emit_global_shader_pointers(struct radv_queue *queue,
R_00B530_SPI_SHADER_USER_DATA_LS_0};

 for (int i = 0; i < ARRAY_SIZE(regs); ++i) {
-   radeon_set_sh_reg_seq(cs, regs[i], 2);
-   radeon_emit(cs, va);
-   radeon_emit(cs, va >> 32);
+   radv_emit_shader_pointer(cs, regs[i], va);
 }
 }
  }
diff --git a/src/amd/vulkan/radv_private.h b/src/amd/vulkan/radv_private.h
index 304ed17f01..05733c7eb9 100644
--- a/src/amd/vulkan/radv_private.h
+++ b/src/amd/vulkan/radv_private.h
@@ -1128,6 +1128,9 @@ bool radv_get_memory_fd(struct radv_device *device,
 struct radv_device_memory *memory,
 int *pFD);

+void radv_emit_shader_pointer(struct radeon_winsys_cs *cs,
+ uint32_t sh_offset, uint64_t va);
+
  static inline struct radv_descriptor_state *
  radv_get_descriptors_state(struct radv_cmd_buffer *cmd_buffer,
VkPipelineBindPoint bind_point)
--
2.17.0

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[Mesa-dev] [Bug 106251] [PATCH] SWR driver doesn't compile with LLVM 7.0 snapshots

[bugzilla-daemon]

https://bugs.freedesktop.org/show_bug.cgi?id=106251

George Kyriazis  changed:

   What|Removed |Added

 Resolution|--- |FIXED
 Status|NEW |RESOLVED

--- Comment #1 from George Kyriazis  ---
fixed with various checkins over time.

Among others:
cd5319a64fb1a9b080521a03e08202e48aca448e
79487c427ee2f82bc947ac1dffd6e2374efaa90f

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[Mesa-dev] [Bug 101614] OSMesa 17.1.3 simd16intrin build FAIL on Win/MinGW - 'expected initializer before _simd16_setzero_ps ...'

[bugzilla-daemon]

https://bugs.freedesktop.org/show_bug.cgi?id=101614

George Kyriazis  changed:

   What|Removed |Added

 Status|REOPENED|RESOLVED
 Resolution|--- |WONTFIX

--- Comment #16 from George Kyriazis  ---
Closing, since realistically we won't do any more work pre mesa-18.

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[Mesa-dev] [ANNOUNCE] mesa 18.0.4

[Juan A. Suarez Romero]

Mesa 18.0.4 is now available.

In this release we have:

r600 driver gets a fix for constant buffer boounds, which fixes rendering bugs
in Trine and Witcher 1.

Several fixes for RADV driver: fixes around alpha channel in Pre-Vega, fix in
multisample image copies, and fixes around multilayer images in compute path.

For the case of ANV/i965 drivers, also a couple of fixes, all of them around
ISP. On top, there are a couple of fixes relative to code emission around 16-bit
integers, and a a fix for a leak in blorp for Gen4 and Gen5.

Speaking of leaks, there are also fixes for winsys/radeon/amdgpu and
pipe-loader.gets a couple of patches to fix a couple of leaks.

SPIR-V part gets a patch to apply OriginUpperLeft to FragCoord.

Mesa core gets a couple of patches to fix error handling in
get_framebuffer_parameteriv, and to add missing support for
glFogiv(GL_FOG_DISTANCE_MODE_NV).


Bas Nieuwenhuizen (3):
  radv: Translate logic ops.
  radv: Fix up 2_10_10_10 alpha sign.
  radv: Disable texel buffers with A2 SNORM/SSCALED/SINT for pre-vega.

Dave Airlie (3):
  r600: fix constant buffer bounds.
  radv: resolve all layers in compute resolve path.
  radv: use compute path for multi-layer images.

Deepak Rawat (1):
  egl/x11: Send invalidate to driver on copy_region path in swap_buffer

Ian Romanick (1):
  mesa: Add missing support for glFogiv(GL_FOG_DISTANCE_MODE_NV)

Jan Vesely (8):
  clover: Add explicit virtual destructor to argument class
  eg/compute: Drop reference on code_bo in destructor.
  r600: Cleanup constant buffers on context destruction
  eg/compute: Drop reference to kernel_param bo in destructor
  pipe-loader: Free driver_name in error path
  gallium/auxiliary: Add helper function to count the number of entries in 
hash table
  winsys/radeon: Destroy fd_hash table when the last winsys is removed.
  winsys/amdgpu: Destroy dev_hash table when the last winsys is removed.

Jason Ekstrand (1):
  i965,anv: Set the CS stall bit on the ISP disable PIPE_CONTROL

Jose Maria Casanova Crespo (2):
  intel/compiler: fix 16-bit int brw_negate_immediate and brw_abs_immediate
  intel/compiler: fix brw_imm_w for negative 16-bit integers

Juan A. Suarez Romero (8):
  docs: add sha256 checksums for 18.0.3
  cherry-ignore: add explicit 18.1 only nominations
  cherry-ignore: glsl: change ast_type_qualifier bitset size to work around 
GCC 5.4 bug
  cherry-ignore: mesa: fix glGetInteger/Float/etc queries for vertex arrays 
attribs
  cherry-ignore: mesa: revert GL_[SECONDARY_]COLOR_ARRAY_SIZE glGet type to 
TYPE_INT
  cherry-ignore: radv/resolve: do fmask decompress on all layers.
  Update version to 18.0.4
  docs: add release notes for 18.0.4

Kai Wasserbäch (1):
  opencl: autotools: Fix linking order for OpenCL target

Kenneth Graunke (1):
  i965: Don't leak blorp on Gen4-5.

Lionel Landwerlin (2):
  i965: require pixel scoreboard stall prior to ISP disable
  anv: emit pixel scoreboard stall before ISP disable

Matthew Nicholls (1):
  radv: fix multisample image copies

Neil Roberts (1):
  spirv: Apply OriginUpperLeft to FragCoord

Rhys Perry (1):
  mesa: fix error handling in get_framebuffer_parameteriv

Ross Burton (1):
  src/intel/Makefile.vulkan.am: add missing MKDIR_GEN

git tag: mesa-18.0.4

https://mesa.freedesktop.org/archive/mesa-18.0.4.tar.gz
MD5:  d47abf2d1b272b4ab936a7addf34cd00  mesa-18.0.4.tar.gz
SHA1: c58887e20ed7cdd6decdc552294da8db485d5e32  mesa-18.0.4.tar.gz
SHA256: d1dc3469faccdd73439479426952d71a9e8f684e8d03b6687063c12b13430801  
mesa-18.0.4.tar.gz
SHA512: 
7339d1e552475792a5f8e9f5374080e16774af50fd2cb9e960b987b0c6bdf14941b0927d5c882f473e5659d51bfb974cd0023d5f990fb95c3d0015dd7a342922
  mesa-18.0.4.tar.gz
PGP:  https://mesa.freedesktop.org/archive/mesa-18.0.4.tar.gz.sig

https://mesa.freedesktop.org/archive/mesa-18.0.4.tar.xz
MD5:  ef525adaff7f31bedd4c5134bc313da9  mesa-18.0.4.tar.xz
SHA1: 4bbee07d8eb42625f215f49d39a657fabdc2f29d  mesa-18.0.4.tar.xz
SHA256: 1f3bcfe7cef0a5c20dae2b41df5d7e0a985e06be0183fa4d43b6068fcba2920f  
mesa-18.0.4.tar.xz
SHA512: 
f9a14be46c209661ceb318add1611481445d13b47e95c7a5d2a5e5ecfdd5d2c3fa9c2b16b30035bbb8d61ccc7cb65bfa6698ac8b040273e5ab045a951a67752c
  mesa-18.0.4.tar.xz
PGP:  https://mesa.freedesktop.org/archive/mesa-18.0.4.tar.xz.sig


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[Mesa-dev] [PATCH] cmake: Bump minimum version to 3.2.

[Vinson Lee]

This build error occurs with cmake 2.8.12.
/bin/sh: BYPRODUCTS: command not found

BYPRODUCTS is not available until cmake 3.2.
https://cmake.org/cmake/help/v3.2/release/3.2.html

Fixes: 2f02cf0d4c2d ("Generate xml for builtin profiles")
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=106370
Signed-off-by: Vinson Lee 
---
 CMakeLists.txt |2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/CMakeLists.txt b/CMakeLists.txt
index 8c7d162..e56aafb 100644
--- a/CMakeLists.txt
+++ b/CMakeLists.txt
@@ -1,4 +1,4 @@
-cmake_minimum_required(VERSION 2.8.5)
+cmake_minimum_required(VERSION 3.2)
 
 list(APPEND CMAKE_MODULE_PATH "${CMAKE_SOURCE_DIR}/cmake/Modules")
 
-- 
1.7.1

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Re: [Mesa-dev] [PATCH 2/4] mesa: Remove flush_vertrices argument from VAO methods.

[Mathias Fröhlich]

Hi,

On Thursday, 17 May 2018 16:03:39 CEST Brian Paul wrote:
> In the subject line "flush_vertices"
> 
> For this series, Reviewed-by: Brian Paul 
> 
> More nice clean-ups!

Thank you!
I have changed the subject ...
And that part is pushed - thanks for the review!

best

Mathias


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[Mesa-dev] [PATCH] draw: get rid of special logic to not emit null tris

[sroland]

From: Roland Scheidegger 

I've confirmed after 77554d220d6d74b4d913dc37ea3a874e9dc550e4 we no
longer need this to pass some tests from another api (as we no longer
generate the bogus extra null tris in the first place).
---
 src/gallium/auxiliary/draw/draw_pipe_clip.c | 38 -
 1 file changed, 38 deletions(-)

diff --git a/src/gallium/auxiliary/draw/draw_pipe_clip.c 
b/src/gallium/auxiliary/draw/draw_pipe_clip.c
index 46118b6..2a9c944 100644
--- a/src/gallium/auxiliary/draw/draw_pipe_clip.c
+++ b/src/gallium/auxiliary/draw/draw_pipe_clip.c
@@ -210,30 +210,6 @@ static void interp(const struct clip_stage *clip,
 }
 
 /**
- * Checks whether the specified triangle is empty and if it is returns
- * true, otherwise returns false.
- * Triangle is considered null/empty if its area is equal to zero.
- */
-static inline boolean
-is_tri_null(const struct clip_stage *clip, const struct prim_header *header)
-{
-   const unsigned pos_attr = clip->pos_attr;
-   float x1 = header->v[1]->data[pos_attr][0] - 
header->v[0]->data[pos_attr][0];
-   float y1 = header->v[1]->data[pos_attr][1] - 
header->v[0]->data[pos_attr][1];
-   float z1 = header->v[1]->data[pos_attr][2] - 
header->v[0]->data[pos_attr][2];
-
-   float x2 = header->v[2]->data[pos_attr][0] - 
header->v[0]->data[pos_attr][0];
-   float y2 = header->v[2]->data[pos_attr][1] - 
header->v[0]->data[pos_attr][1];
-   float z2 = header->v[2]->data[pos_attr][2] - 
header->v[0]->data[pos_attr][2];
-
-   float vx = y1 * z2 - z1 * y2;
-   float vy = x1 * z2 - z1 * x2;
-   float vz = x1 * y2 - y1 * x2;
-
-   return (vx*vx  + vy*vy + vz*vz) == 0.f;
-}
-
-/**
  * Emit a post-clip polygon to the next pipeline stage.  The polygon
  * will be convex and the provoking vertex will always be vertex[0].
  */
@@ -247,7 +223,6 @@ static void emit_poly(struct draw_stage *stage,
struct prim_header header;
unsigned i;
ushort edge_first, edge_middle, edge_last;
-   boolean tri_emitted = FALSE;
 
if (stage->draw->rasterizer->flatshade_first) {
   edge_first  = DRAW_PIPE_EDGE_FLAG_0;
@@ -269,7 +244,6 @@ static void emit_poly(struct draw_stage *stage,
header.pad = 0;
 
for (i = 2; i < n; i++, header.flags = edge_middle) {
-  boolean tri_null;
   /* order the triangle verts to respect the provoking vertex mode */
   if (stage->draw->rasterizer->flatshade_first) {
  header.v[0] = inlist[0];  /* the provoking vertex */
@@ -282,18 +256,6 @@ static void emit_poly(struct draw_stage *stage,
  header.v[2] = inlist[0];  /* the provoking vertex */
   }
 
-  tri_null = is_tri_null(clipper, );
-  /*
-   * If we ever generated a tri (regardless if it had area or not),
-   * skip all subsequent null tris.
-   * FIXME: I think this logic was hiding bugs elsewhere. It should
-   * be possible now to always emit all tris.
-   */
-  if (tri_null && tri_emitted) {
- continue;
-  }
-  tri_emitted = TRUE;
-
   if (!edgeflags[i-1]) {
  header.flags &= ~edge_middle;
   }
-- 
2.7.4

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Re: [Mesa-dev] [Mesa-stable] [PATCH 01/17] i965/miptree: Fix handling of uninitialized MCS buffers

[Dylan Baker]

Quoting Nanley Chery (2018-05-03 12:03:48)
> Before this patch, if we failed to initialize an MCS buffer, we'd
> end up in a state in which the miptree thinks it has an MCS buffer,
> but doesn't. We also leaked the clear_color_bo if it existed.
> 
> With this patch, we now free the miptree aux buffer resources and let
> intel_miptree_alloc_mcs() know that the MCS buffer no longer exists.
> 
> Cc: 
> ---
>  src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 14 +++---
>  1 file changed, 7 insertions(+), 7 deletions(-)
> 
> diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c 
> b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
> index b9a564552df..377efae32c9 100644
> --- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
> +++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
> @@ -1658,7 +1658,7 @@ intel_miptree_copy_teximage(struct brw_context *brw,
> intel_obj->needs_validate = true;
>  }
>  
> -static void
> +static bool
>  intel_miptree_init_mcs(struct brw_context *brw,
> struct intel_mipmap_tree *mt,
> int init_value)
> @@ -1678,13 +1678,14 @@ intel_miptree_init_mcs(struct brw_context *brw,
> void *map = brw_bo_map(brw, mt->aux_buf->bo, MAP_WRITE | MAP_RAW);
> if (unlikely(map == NULL)) {
>fprintf(stderr, "Failed to map mcs buffer into GTT\n");
> -  brw_bo_unreference(mt->aux_buf->bo);
> -  free(mt->aux_buf);
> -  return;
> +  intel_miptree_aux_buffer_free(mt->aux_buf);
> +  mt->aux_buf = NULL;
> +  return false;
> }
> void *data = map;
> memset(data, init_value, mt->aux_buf->size);
> brw_bo_unmap(mt->aux_buf->bo);
> +   return true;
>  }
>  
>  static struct intel_miptree_aux_buffer *
> @@ -1764,15 +1765,14 @@ intel_miptree_alloc_mcs(struct brw_context *brw,
> const uint32_t alloc_flags = 0;
> mt->aux_buf = intel_alloc_aux_buffer(brw, "mcs-miptree",
>  _mcs_surf, alloc_flags, mt);
> -   if (!mt->aux_buf) {
> +   if (!mt->aux_buf ||
> +   !intel_miptree_init_mcs(brw, mt, 0xFF)) {
>free(aux_state);
>return false;
> }
>  
> mt->aux_state = aux_state;
>  
> -   intel_miptree_init_mcs(brw, mt, 0xFF);
> -
> return true;
>  }
>  
> -- 
> 2.16.2
> 
> ___
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> mesa-sta...@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/mesa-stable


Hi Nanley,

Neither this patch or the next one cleanly apply to the 18.1 branch (or, I
assume, 18.0), it looks like this depends on
af4e9295febe966ace7793e43ba35705521749e8, which was not CC'd to stable. I'm not
sure how to resolve the rebase conflicts, what would you like to do?

Dylan


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Re: [Mesa-dev] [PATCH] mesa: drop GL_EXT_polygon_offset support

[Marek Olšák]

Reviewed-by: Marek Olšák 

Marek

On Fri, May 11, 2018 at 1:38 AM, Timothy Arceri 
wrote:

> glPolygonOffset() has been part of the GL standard since 1.1. Also
> niether AMD or Nvidia support this in their binary drivers.
>
> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=61761
> ---
>  docs/relnotes/18.2.0.html   | 64 +
>  src/mapi/glapi/gen/gl_API.xml   | 10 
>  src/mapi/glapi/tests/check_table.cpp|  1 -
>  src/mesa/main/dlist.c   | 11 -
>  src/mesa/main/extensions_table.h|  1 -
>  src/mesa/main/get_hash_params.py|  1 -
>  src/mesa/main/polygon.c |  8 
>  src/mesa/main/polygon.h |  3 --
>  src/mesa/main/tests/dispatch_sanity.cpp |  1 -
>  9 files changed, 64 insertions(+), 36 deletions(-)
>  create mode 100644 docs/relnotes/18.2.0.html
>
> diff --git a/docs/relnotes/18.2.0.html b/docs/relnotes/18.2.0.html
> new file mode 100644
> index 000..f3bdb6605c4
> --- /dev/null
> +++ b/docs/relnotes/18.2.0.html
> @@ -0,0 +1,64 @@
> + http://www.w3.org/TR/html4/loose.dtd;>
> +
> +
> +  
> +  Mesa Release Notes
> +  
> +
> +
> +
> +
> +  The Mesa 3D Graphics Library
> +
> +
> +
> +
> +
> +Mesa 18.2.0 Release Notes / TBD
> +
> +
> +Mesa 18.2.0 is a new development release. People who are concerned
> +with stability and reliability should stick with a previous release or
> +wait for Mesa 18.2.1.
> +
> +
> +Mesa 18.2.0 implements the OpenGL 4.5 API, but the version reported by
> +glGetString(GL_VERSION) or glGetIntegerv(GL_MAJOR_VERSION) /
> +glGetIntegerv(GL_MINOR_VERSION) depends on the particular driver being
> used.
> +Some drivers don't support all the features required in OpenGL 4.5.
> OpenGL
> +4.5 is only available if requested at context creation.
> +Compatibility contexts may report a lower version depending on each
> driver.
> +
> +
> +
> +SHA256 checksums
> +
> +TBD.
> +
> +
> +
> +New features
> +
> +
> +Note: some of the new features are only available with certain drivers.
> +
> +
> +
> +TBD
> +
> +
> +Bug fixes
> +
> +
> +TBD
> +
> +
> +Changes
> +
> +
> +Removed GL_EXT_polygon_offset applications should use glPolygonOffset
> instead.
> +
> +
> +
> +
> +
> diff --git a/src/mapi/glapi/gen/gl_API.xml b/src/mapi/glapi/gen/gl_API.xml
> index db312370b1d..8ad45970c9c 100644
> --- a/src/mapi/glapi/gen/gl_API.xml
> +++ b/src/mapi/glapi/gen/gl_API.xml
> @@ -8423,16 +8423,6 @@
>  
>  
>
> -
> -
> -
> -
> -
> -
> -
> -
> -
> -
>  
>  
>  
> diff --git a/src/mapi/glapi/tests/check_table.cpp
> b/src/mapi/glapi/tests/check_table.cpp
> index 6230f1273f3..761f2a24e09 100644
> --- a/src/mapi/glapi/tests/check_table.cpp
> +++ b/src/mapi/glapi/tests/check_table.cpp
> @@ -1260,7 +1260,6 @@ const struct name_offset known_dispatch[] = {
> { "glTextureStorage1DEXT", _O(TextureStorage1DEXT) },
> { "glTextureStorage2DEXT", _O(TextureStorage2DEXT) },
> { "glTextureStorage3DEXT", _O(TextureStorage3DEXT) },
> -   { "glPolygonOffsetEXT", _O(PolygonOffsetEXT) },
> { "glSampleMaskSGIS", _O(SampleMaskSGIS) },
> { "glSamplePatternSGIS", _O(SamplePatternSGIS) },
> { "glColorPointerEXT", _O(ColorPointerEXT) },
> diff --git a/src/mesa/main/dlist.c b/src/mesa/main/dlist.c
> index 9e6cb725f54..8be223559ab 100644
> --- a/src/mesa/main/dlist.c
> +++ b/src/mesa/main/dlist.c
> @@ -3485,14 +3485,6 @@ save_PolygonOffset(GLfloat factor, GLfloat units)
>  }
>
>
> -static void GLAPIENTRY
> -save_PolygonOffsetEXT(GLfloat factor, GLfloat bias)
> -{
> -   GET_CURRENT_CONTEXT(ctx);
> -   /* XXX mult by DepthMaxF here??? */
> -   save_PolygonOffset(factor, ctx->DrawBuffer->_DepthMaxF * bias);
> -}
> -
>  static void GLAPIENTRY
>  save_PolygonOffsetClampEXT(GLfloat factor, GLfloat units, GLfloat clamp)
>  {
> @@ -9839,9 +9831,6 @@ _mesa_initialize_save_table(const struct gl_context
> *ctx)
> SET_BlendColorEXT(table, save_BlendColorEXT);
>  #endif
>
> -   /* 3. GL_EXT_polygon_offset */
> -   SET_PolygonOffsetEXT(table, save_PolygonOffsetEXT);
> -
> /* 6. GL_EXT_texture3d */
>  #if 0
> SET_CopyTexSubImage3DEXT(table, save_CopyTexSubImage3D);
> diff --git a/src/mesa/main/extensions_table.h b/src/mesa/main/extensions_
> table.h
> index 945b462122c..38d241db529 100644
> --- a/src/mesa/main/extensions_table.h
> +++ b/src/mesa/main/extensions_table.h
> @@ -240,7 +240,6 @@ EXT(EXT_packed_float,
> EXT_packed_float
>  EXT(EXT_packed_pixels   , dummy_true
>, GLL,  x ,  x ,  x , 1997)
>  EXT(EXT_pixel_buffer_object , EXT_pixel_buffer_object
> , GLL, GLC,  x ,  x , 2004)
>  EXT(EXT_point_parameters, EXT_point_parameters
>, GLL,  x ,  x ,  x , 1997)
> -EXT(EXT_polygon_offset  , dummy_true
>, GLL,  x ,  x ,  x , 1995)
>  EXT(EXT_polygon_offset_clamp

Re: [Mesa-dev] [PATCH 2/6] radeonsi: disable primitive binning for all blitter ops

[Marek Olšák]

On Thu, May 17, 2018 at 4:35 AM, Grazvydas Ignotas 
wrote:

> On Thu, May 17, 2018 at 4:47 AM, Marek Olšák  wrote:
> > From: Marek Olšák 
> >
> > same as Vulkan.
>
> Ambiguous. Did you mean amdvlk?
>

Of course.

Marek
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[Mesa-dev] [Bug 78097] glUniform1ui and friends not supported by display lists

[bugzilla-daemon]

https://bugs.freedesktop.org/show_bug.cgi?id=78097

--- Comment #4 from Lionel Landwerlin  ---
Arg apologies, I was running against the wrong version of Mesa.

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Re: [Mesa-dev] [PATCH 1/5] swr/rast: Remove unneeded virtual from methods

[Kyriazis, George]

Whole series

Reviewed-By: George Kyriazis 
>

Thanks!


On May 16, 2018, at 11:14 AM, Alok Hota 
> wrote:

---
src/gallium/drivers/swr/rasterizer/jitter/JitManager.h | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/gallium/drivers/swr/rasterizer/jitter/JitManager.h 
b/src/gallium/drivers/swr/rasterizer/jitter/JitManager.h
index 54a25d8..152776a 100644
--- a/src/gallium/drivers/swr/rasterizer/jitter/JitManager.h
+++ b/src/gallium/drivers/swr/rasterizer/jitter/JitManager.h
@@ -108,12 +108,12 @@ public:
}

/// notifyObjectCompiled - Provides a pointer to compiled code for Module M.
-virtual void notifyObjectCompiled(const llvm::Module *M, 
llvm::MemoryBufferRef Obj);
+void notifyObjectCompiled(const llvm::Module *M, llvm::MemoryBufferRef 
Obj) override;

/// Returns a pointer to a newly allocated MemoryBuffer that contains the
/// object which corresponds with Module M, or 0 if an object is not
/// available.
-virtual std::unique_ptr getObject(const llvm::Module* 
M);
+std::unique_ptr getObject(const llvm::Module* M) 
override;

private:
std::string mCpu;
--
2.7.4

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[Mesa-dev] [Bug 78097] glUniform1ui and friends not supported by display lists

[bugzilla-daemon]

https://bugs.freedesktop.org/show_bug.cgi?id=78097

Lionel Landwerlin  changed:

   What|Removed |Added

 Resolution|--- |FIXED
 QA Contact||t_arc...@yahoo.com.au
 Status|REOPENED|RESOLVED

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[Mesa-dev] [Bug 78097] glUniform1ui and friends not supported by display lists

[bugzilla-daemon]

https://bugs.freedesktop.org/show_bug.cgi?id=78097

--- Comment #3 from Lionel Landwerlin  ---
$ ./bin/gl-3.0-dlist-uint-uniforms -auto -fbo
Testing glUniformui
GL_COMPILE: scalar mode
pre-initialize
compiling
post-compile verify
s data does not match.
v2 data does not match.
v3 data does not match.
v4 data does not match.
restore original values
post-glCallList verify
s data does not match.
v2 data does not match.
v3 data does not match.
v4 data does not match.
GL_COMPILE: vector mode
pre-initialize
compiling
post-compile verify
s data does not match.
v2 data does not match.
v3 data does not match.
v4 data does not match.
restore original values
post-glCallList verify
s data does not match.
v2 data does not match.
v3 data does not match.
v4 data does not match.
GL_COMPILE_AND_EXECUTE: scalar mode
pre-initialize
compiling
post-compile verify
restore original values
post-glCallList verify
s data does not match.
v2 data does not match.
v3 data does not match.
v4 data does not match.
GL_COMPILE_AND_EXECUTE: vector mode
pre-initialize
compiling
post-compile verify
restore original values
post-glCallList verify
s data does not match.
v2 data does not match.
v3 data does not match.
v4 data does not match.
PIGLIT: {"result": "fail" }

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[Mesa-dev] [Bug 78097] glUniform1ui and friends not supported by display lists

[bugzilla-daemon]

https://bugs.freedesktop.org/show_bug.cgi?id=78097

Lionel Landwerlin  changed:

   What|Removed |Added

 Status|RESOLVED|REOPENED
 Resolution|FIXED   |---

--- Comment #2 from Lionel Landwerlin  ---
Those new piglit tests are now failing on i965 :(

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Re: [Mesa-dev] [PATCH v2 0/6] broadcom/vc4: Native fence fd support

[Eric Anholt]

Stefan Schake  writes:

> v2 drops the submit flags, directly moves in fence handling to the
> job submit function and queries for the syncobj cap instead of using
> a separate support parameter.
>
> This series adds support for the native fence fd extension to vc4.
> The implementation relies on a newly introduced kernel interface that
> allows submitting syncobjs for in/out fences during job submission.
>
> Since syncobjs are relatively new, patches 1 and 3 have build changes
> for automake and meson to require a recent libdrm version.
>
> There is some scope here to replace the previous sequence number based
> implementation with only syncobjs, but given that we need to continue
> supporting older kernels I felt it would have only added complexity.
>
> This has been tested with piglit and kmscube -A(tomic). In particular,
> I checked that the fd numbers weren't increasing during the kmscube run.
>
> Should not be merged until the kernel side lands. In particular, patch 2
> is purely provisional.

Now that the kernel is in drm-next, I've merged the Mesa patches.  I
updated the UABI patch for the finalized version with pad2, and I
tweaked the meson.build patch so that we don't need a libdrm_vc4.

Thanks so much for working on this!


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[Mesa-dev] [PATCH] Revert "st/nir: use NIR for asm programs"

[Eric Anholt]

This reverts commit 5c33e8c7729edd5e16020ebb8703be96523e04f2.  It broke
fixed function vertex programs on vc4 and v3d, and apparently caused
trouble for radeonsi's NIR paths as well.
---
 src/mesa/state_tracker/st_program.c | 65 -
 1 file changed, 7 insertions(+), 58 deletions(-)

diff --git a/src/mesa/state_tracker/st_program.c 
b/src/mesa/state_tracker/st_program.c
index a7671b7fd1d8..8117f4ff8dbb 100644
--- a/src/mesa/state_tracker/st_program.c
+++ b/src/mesa/state_tracker/st_program.c
@@ -37,7 +37,6 @@
 #include "main/mtypes.h"
 #include "program/prog_parameter.h"
 #include "program/prog_print.h"
-#include "program/prog_to_nir.h"
 #include "program/programopt.h"
 
 #include "compiler/nir/nir.h"
@@ -378,28 +377,6 @@ st_release_cp_variants(struct st_context *st, struct 
st_compute_program *stcp)
}
 }
 
-/**
- * Translate ARB (asm) program to NIR
- */
-static nir_shader *
-st_translate_prog_to_nir(struct st_context *st, struct gl_program *prog,
- gl_shader_stage stage)
-{
-   const struct gl_shader_compiler_options *options =
-  >ctx->Const.ShaderCompilerOptions[stage];
-
-   /* Translate to NIR */
-   nir_shader *nir = prog_to_nir(prog, options->NirOptions);
-   NIR_PASS_V(nir, nir_lower_regs_to_ssa); /* turn registers into SSA */
-   nir_validate_shader(nir);
-
-   /* Optimise NIR */
-   st_nir_opts(nir);
-   nir_validate_shader(nir);
-
-   return nir;
-}
-
 /**
  * Translate a vertex program.
  */
@@ -481,28 +458,15 @@ st_translate_vertex_program(struct st_context *st,
   /* No samplers are allowed in ARB_vp. */
}
 
-   enum pipe_shader_ir preferred_ir = (enum pipe_shader_ir)
-  st->pipe->screen->get_shader_param(st->pipe->screen, PIPE_SHADER_VERTEX,
- PIPE_SHADER_CAP_PREFERRED_IR);
-
-   if (preferred_ir == PIPE_SHADER_IR_NIR) {
-  if (stvp->shader_program) {
- struct gl_program *prog = stvp->shader_program->last_vert_prog;
- if (prog) {
-st_translate_stream_output_info2(prog->sh.LinkedTransformFeedback,
- stvp->result_to_output,
- >tgsi.stream_output);
- }
-
- st_store_ir_in_disk_cache(st, >Base, true);
-  } else {
- nir_shader *nir = st_translate_prog_to_nir(st, >Base,
-MESA_SHADER_VERTEX);
-
- stvp->tgsi.type = PIPE_SHADER_IR_NIR;
- stvp->tgsi.ir.nir = nir;
+   if (stvp->shader_program) {
+  struct gl_program *prog = stvp->shader_program->last_vert_prog;
+  if (prog) {
+ st_translate_stream_output_info2(prog->sh.LinkedTransformFeedback,
+  stvp->result_to_output,
+  >tgsi.stream_output);
   }
 
+  st_store_ir_in_disk_cache(st, >Base, true);
   return true;
}
 
@@ -742,21 +706,6 @@ st_translate_fragment_program(struct st_context *st,
   }
}
 
-   enum pipe_shader_ir preferred_ir = (enum pipe_shader_ir)
-  st->pipe->screen->get_shader_param(st->pipe->screen,
- PIPE_SHADER_FRAGMENT,
- PIPE_SHADER_CAP_PREFERRED_IR);
-
-   if (preferred_ir == PIPE_SHADER_IR_NIR) {
-  nir_shader *nir = st_translate_prog_to_nir(st, >Base,
- MESA_SHADER_FRAGMENT);
-
-  stfp->tgsi.type = PIPE_SHADER_IR_NIR;
-  stfp->tgsi.ir.nir = nir;
-
-  return true;
-   }
-
/*
 * Convert Mesa program inputs to TGSI input register semantics.
 */
-- 
2.17.0

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Re: [Mesa-dev] [PATCH 2/2] radv: add radv_emit_shader_pointer() helper

[Bas Nieuwenhuizen]

Do we want the new function inlined?

Reviewed-by: Bas Nieuwenhuizen 

On Thu, May 17, 2018 at 2:16 PM, Samuel Pitoiset
 wrote:
> For future work (support for 32-bit GPU pointers).
>
> Signed-off-by: Samuel Pitoiset 
> ---
>  src/amd/vulkan/radv_cmd_buffer.c | 13 ++---
>  src/amd/vulkan/radv_device.c | 17 +++--
>  src/amd/vulkan/radv_private.h|  3 +++
>  3 files changed, 20 insertions(+), 13 deletions(-)
>
> diff --git a/src/amd/vulkan/radv_cmd_buffer.c 
> b/src/amd/vulkan/radv_cmd_buffer.c
> index 1ca687494a..a8359ac092 100644
> --- a/src/amd/vulkan/radv_cmd_buffer.c
> +++ b/src/amd/vulkan/radv_cmd_buffer.c
> @@ -587,9 +587,9 @@ radv_emit_userdata_address(struct radv_cmd_buffer 
> *cmd_buffer,
> return;
> assert(loc->num_sgprs == 2);
> assert(!loc->indirect);
> -   radeon_set_sh_reg_seq(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, 
> 2);
> -   radeon_emit(cmd_buffer->cs, va);
> -   radeon_emit(cmd_buffer->cs, va >> 32);
> +
> +   radv_emit_shader_pointer(cmd_buffer->cs,
> +base_reg + loc->sgpr_idx * 4, va);
>  }
>
>  static void
> @@ -1442,10 +1442,9 @@ emit_stage_descriptor_set_userdata(struct 
> radv_cmd_buffer *cmd_buffer,
>
> assert(!desc_set_loc->indirect);
> assert(desc_set_loc->num_sgprs == 2);
> -   radeon_set_sh_reg_seq(cmd_buffer->cs,
> - base_reg + desc_set_loc->sgpr_idx * 4, 2);
> -   radeon_emit(cmd_buffer->cs, va);
> -   radeon_emit(cmd_buffer->cs, va >> 32);
> +
> +   radv_emit_shader_pointer(cmd_buffer->cs,
> +base_reg + desc_set_loc->sgpr_idx * 4, va);
>  }
>
>  static void
> diff --git a/src/amd/vulkan/radv_device.c b/src/amd/vulkan/radv_device.c
> index fa07ec40f3..91ab729d86 100644
> --- a/src/amd/vulkan/radv_device.c
> +++ b/src/amd/vulkan/radv_device.c
> @@ -1941,6 +1941,15 @@ radv_emit_compute_scratch(struct radv_queue *queue, 
> struct radeon_winsys_cs *cs,
> S_008F04_SWIZZLE_ENABLE(1));
>  }
>
> +void
> +radv_emit_shader_pointer(struct radeon_winsys_cs *cs,
> +uint32_t sh_offset, uint64_t va)
> +{
> +   radeon_set_sh_reg_seq(cs, sh_offset, 2);
> +   radeon_emit(cs, va);
> +   radeon_emit(cs, va >> 32);
> +}
> +
>  static void
>  radv_emit_global_shader_pointers(struct radv_queue *queue,
>  struct radeon_winsys_cs *cs,
> @@ -1962,9 +1971,7 @@ radv_emit_global_shader_pointers(struct radv_queue 
> *queue,
>R_00B408_SPI_SHADER_USER_DATA_ADDR_LO_HS};
>
> for (int i = 0; i < ARRAY_SIZE(regs); ++i) {
> -   radeon_set_sh_reg_seq(cs, regs[i], 2);
> -   radeon_emit(cs, va);
> -   radeon_emit(cs, va >> 32);
> +   radv_emit_shader_pointer(cs, regs[i], va);
> }
> } else {
> uint32_t regs[] = {R_00B030_SPI_SHADER_USER_DATA_PS_0,
> @@ -1975,9 +1982,7 @@ radv_emit_global_shader_pointers(struct radv_queue 
> *queue,
>R_00B530_SPI_SHADER_USER_DATA_LS_0};
>
> for (int i = 0; i < ARRAY_SIZE(regs); ++i) {
> -   radeon_set_sh_reg_seq(cs, regs[i], 2);
> -   radeon_emit(cs, va);
> -   radeon_emit(cs, va >> 32);
> +   radv_emit_shader_pointer(cs, regs[i], va);
> }
> }
>  }
> diff --git a/src/amd/vulkan/radv_private.h b/src/amd/vulkan/radv_private.h
> index 304ed17f01..05733c7eb9 100644
> --- a/src/amd/vulkan/radv_private.h
> +++ b/src/amd/vulkan/radv_private.h
> @@ -1128,6 +1128,9 @@ bool radv_get_memory_fd(struct radv_device *device,
> struct radv_device_memory *memory,
> int *pFD);
>
> +void radv_emit_shader_pointer(struct radeon_winsys_cs *cs,
> + uint32_t sh_offset, uint64_t va);
> +
>  static inline struct radv_descriptor_state *
>  radv_get_descriptors_state(struct radv_cmd_buffer *cmd_buffer,
>VkPipelineBindPoint bind_point)
> --
> 2.17.0
>
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Re: [Mesa-dev] [PATCH v2] android: enable VK_ANDROID_native_buffer

[Jason Ekstrand]

Whatever.  If there isn't too much of a rush, my preference would be to 
pull in the vk_icd.h fix as a pull from upstream and then do this 
afterwards.  I guess this doesn't help anyone without the vk_icd.h fix.  If 
we are in a rush, I'd be ok with making the fix in our tree so long as it's 
in its own patch and the commit message references the upstream PR.


On May 17, 2018 00:37:13 Tapani Pälli  wrote:


On 05/17/2018 10:23 AM, Jason Ekstrand wrote:

Ok, so long as the current build isn't broken without it, rb.


Well TBH it does not compile but I thought you wanted the change to come
as a pull from upstream header. I can put it back here temporarily or
just later update the header.


On May 17, 2018 00:16:44 Tapani Pälli  wrote:


On 05/17/2018 09:38 AM, Jason Ekstrand wrote:

What happened to the vk_icd.h bit?


That's going here:
https://github.com/KhronosGroup/Vulkan-Headers/pull/2


On May 16, 2018 22:30:55 Tapani Pälli  wrote:


Patch changes entrypoints generator to not skip this extension even
though it is set as disabled in the xml. We also need compilation
flag VK_USE_PLATFORM_ANDROID_KHR to be enabled.

It looks like this extension got disabled in commit 69f447553c.

v2: just remove the whole 'supported' attrib check + remove
   vk_icd.h compilation fix (fix in VulkanHeaders instead)

Signed-off-by: Tapani Pälli 
---
Android.common.mk   | 1 +
src/intel/vulkan/anv_entrypoints_gen.py | 3 ---
2 files changed, 1 insertion(+), 3 deletions(-)

diff --git a/Android.common.mk b/Android.common.mk
index e8aed48c31..999e17789b 100644
--- a/Android.common.mk
+++ b/Android.common.mk
@@ -73,6 +73,7 @@ LOCAL_CFLAGS += \
-DHAVE_ENDIAN_H \
-DHAVE_ZLIB \
-DMAJOR_IN_SYSMACROS \
+-DVK_USE_PLATFORM_ANDROID_KHR \
-fvisibility=hidden \
-Wno-sign-compare

diff --git a/src/intel/vulkan/anv_entrypoints_gen.py
b/src/intel/vulkan/anv_entrypoints_gen.py
index d603ac1b20..230671d36a 100644
--- a/src/intel/vulkan/anv_entrypoints_gen.py
+++ b/src/intel/vulkan/anv_entrypoints_gen.py
@@ -495,9 +495,6 @@ def get_entrypoints(doc, entrypoints_to_defines,
start_index):
if ext_name not in supported_exts:
continue

-if extension.attrib['supported'] != 'vulkan':
-continue
-
ext = supported_exts[ext_name]
ext.type = extension.attrib['type']

--
2.14.3

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Re: [Mesa-dev] [PATCH 06/22] compiler/nir: support 16-bit float in nir_imm_floatN_t

[Jason Ekstrand]

After sending this, I realized that it's probably because you depend on 
nir_imm_intN_t().  Alternatively, we could make a nir_imm_float16() helper 
which may be nicer for cases where you know you need 16-bit floats.  This 
is fine though.  Rb.


On May 17, 2018 07:01:53 Jason Ekstrand  wrote:


Why did the function move?

On May 17, 2018 01:47:51 Iago Toral Quiroga  wrote:


---
src/compiler/nir/nir_builder.h | 29 -
1 file changed, 16 insertions(+), 13 deletions(-)

diff --git a/src/compiler/nir/nir_builder.h b/src/compiler/nir/nir_builder.h
index 02a9dbfb040..198c42dd823 100644
--- a/src/compiler/nir/nir_builder.h
+++ b/src/compiler/nir/nir_builder.h
@@ -25,6 +25,7 @@
#define NIR_BUILDER_H

#include "nir_control_flow.h"
+#include "util/half_float.h"

struct exec_list;

@@ -227,19 +228,6 @@ nir_imm_double(nir_builder *build, double x)
return nir_build_imm(build, 1, 64, v);
}

-static inline nir_ssa_def *
-nir_imm_floatN_t(nir_builder *build, double x, unsigned bit_size)
-{
-   switch (bit_size) {
-   case 32:
-  return nir_imm_float(build, x);
-   case 64:
-  return nir_imm_double(build, x);
-   }
-
-   unreachable("unknown float immediate bit size");
-}
-
static inline nir_ssa_def *
nir_imm_vec4(nir_builder *build, float x, float y, float z, float w)
{
@@ -288,6 +276,21 @@ nir_imm_intN_t(nir_builder *build, uint64_t x,
unsigned bit_size)
return nir_build_imm(build, 1, bit_size, v);
}

+static inline nir_ssa_def *
+nir_imm_floatN_t(nir_builder *build, double x, unsigned bit_size)
+{
+   switch (bit_size) {
+   case 16:
+  return nir_imm_intN_t(build, _mesa_float_to_half((float)x), 16);
+   case 32:
+  return nir_imm_float(build, x);
+   case 64:
+  return nir_imm_double(build, x);
+   }
+
+   unreachable("unknown float immediate bit size");
+}
+
static inline nir_ssa_def *
nir_imm_ivec4(nir_builder *build, int x, int y, int z, int w)
{
--
2.14.1

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Re: [Mesa-dev] [PATCH 9.5/17] squash! i965/miptree: Unify aux buffer allocation

[Nanley Chery]

On Thu, May 17, 2018 at 07:44:34AM +0300, Pohjolainen, Topi wrote:
> On Wed, May 16, 2018 at 09:33:34AM -0700, Nanley Chery wrote:
> > On Wed, May 16, 2018 at 09:11:38AM +0300, Pohjolainen, Topi wrote:
> > > On Wed, May 09, 2018 at 10:47:24AM -0700, Nanley Chery wrote:
> > > > v2: Inline the switch statement (Jason)
> > > > 
> > > > Reviewed-by: Jason Ekstrand 
> > > > ---
> > > >  src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 90 ---
> > > >  1 file changed, 38 insertions(+), 52 deletions(-)
> > > > 
> > > > diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c 
> > > > b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
> > > > index f78b862a702..b5d7d691ecc 100644
> > > > --- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
> > > > +++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
> > > > @@ -1777,30 +1777,37 @@ intel_miptree_level_enable_hiz(struct 
> > > > brw_context *brw,
> > > >  }
> > > >  
> > > >  
> > > > -/* Returns true iff all params are successfully filled. */
> > > > -static bool
> > > > -get_aux_buf_params(const struct brw_context *brw,
> > > > -   const struct intel_mipmap_tree *mt,
> > > > -   enum isl_aux_state *initial_state,
> > > > -   uint8_t *memset_value,
> > > > -   struct isl_surf *aux_surf)
> > > > +/**
> > > > + * Allocate the initial aux surface for a miptree based on 
> > > > mt->aux_usage
> > > > + *
> > > > + * Since MCS, HiZ, and CCS_E can compress more than just clear color, 
> > > > we
> > > > + * create the auxiliary surfaces up-front.  CCS_D, on the other hand, 
> > > > can only
> > > > + * compress clear color so we wait until an actual fast-clear to 
> > > > allocate it.
> > > > + */
> > > > +bool
> > > > +intel_miptree_alloc_aux(struct brw_context *brw,
> > > > +struct intel_mipmap_tree *mt)
> > > >  {
> > > > -   assert(initial_state && memset_value && aux_surf);
> > > > +   assert(mt->aux_buf == NULL);
> > > > +
> > > > +   /* Get the aux buf allocation parameters for this miptree. */
> > > > +   enum isl_aux_state initial_state;
> > > > +   uint8_t memset_value;
> > > > +   struct isl_surf aux_surf;
> > > > +   bool aux_surf_ok;
> > > >  
> > > > switch (mt->aux_usage) {
> > > > case ISL_AUX_USAGE_NONE:
> > > > -  aux_surf->size = 0;
> > > > -  return true;
> > > > +  aux_surf.size = 0;
> > > > +  aux_surf_ok = true;
> > > > +  break;
> > > > case ISL_AUX_USAGE_HIZ:
> > > >assert(!_mesa_is_format_color_format(mt->format));
> > > >  
> > > > -  *initial_state = ISL_AUX_STATE_AUX_INVALID;
> > > > -  {
> > > > - MAYBE_UNUSED bool ok =
> > > > -isl_surf_get_hiz_surf(>isl_dev, >surf, aux_surf);
> > > > - assert(ok);
> > > > -  }
> > > > -  return true;
> > > > +  initial_state = ISL_AUX_STATE_AUX_INVALID;
> > > > +  aux_surf_ok = isl_surf_get_hiz_surf(>isl_dev, >surf, 
> > > > _surf);
> > > > +  assert(aux_surf_ok);
> > > > +  break;
> > > > case ISL_AUX_USAGE_MCS:
> > > >assert(_mesa_is_format_color_format(mt->format));
> > > >assert(brw->screen->devinfo.gen >= 7); /* MCS only used on Gen7+ 
> > > > */
> > > > @@ -1817,14 +1824,11 @@ get_aux_buf_params(const struct brw_context 
> > > > *brw,
> > > > * Note: the clear value for MCS buffers is all 1's, so we 
> > > > memset to
> > > > * 0xff.
> > > > */
> > > > -  *initial_state = ISL_AUX_STATE_CLEAR;
> > > > -  *memset_value = 0xFF;
> > > > -  {
> > > > - MAYBE_UNUSED bool ok =
> > > > -isl_surf_get_mcs_surf(>isl_dev, >surf, aux_surf);
> > > > - assert(ok);
> > > > -  }
> > > > -  return true;
> > > > +  initial_state = ISL_AUX_STATE_CLEAR;
> > > > +  memset_value = 0xFF;
> > > > +  aux_surf_ok = isl_surf_get_mcs_surf(>isl_dev, >surf, 
> > > > _surf);
> > > > +  assert(aux_surf_ok);
> > > > +  break;
> > > > case ISL_AUX_USAGE_CCS_D:
> > > > case ISL_AUX_USAGE_CCS_E:
> > > >assert(_mesa_is_format_color_format(mt->format));
> > > > @@ -1839,36 +1843,18 @@ get_aux_buf_params(const struct brw_context 
> > > > *brw,
> > > > * A CCS value of 0 indicates that the corresponding block is in 
> > > > the
> > > > * pass-through state which is what we want.
> > > > *
> > > > -   * For CCS_D, do the same thing. On gen9+, this avoids having 
> > > > any undefined
> > > > -   * bits in the aux buffer.
> > > > +   * For CCS_D, do the same thing. On gen9+, this avoids having any
> > > > +   * undefined bits in the aux buffer.
> > > > */
> > > > -  *initial_state = ISL_AUX_STATE_PASS_THROUGH;
> > > > -  *memset_value = 0;
> > > > -  return isl_surf_get_ccs_surf(>isl_dev, >surf, aux_surf, 
> > > > 0);
> > > > +  initial_state = ISL_AUX_STATE_PASS_THROUGH;
> > > > +  memset_value = 0;
> > > > +  aux_surf_ok =
> > 

Re: [Mesa-dev] [PATCH 21/22] intel/compiler: lower 16-bit flrp

[Jason Ekstrand]

Rb

On May 17, 2018 01:48:43 Iago Toral Quiroga  wrote:


---
src/intel/compiler/brw_compiler.c | 1 +
1 file changed, 1 insertion(+)

diff --git a/src/intel/compiler/brw_compiler.c 
b/src/intel/compiler/brw_compiler.c

index 36a870ece0d..250e4695ded 100644
--- a/src/intel/compiler/brw_compiler.c
+++ b/src/intel/compiler/brw_compiler.c
@@ -33,6 +33,7 @@
   .lower_sub = true, \
   .lower_fdiv = true,\
   .lower_scmp = true,\
+   .lower_flrp16 = true,   
   \

   .lower_fmod16 = true,  \
   .lower_fmod32 = true,  \
   .lower_fmod64 = false, \
--
2.14.1

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Re: [Mesa-dev] [PATCH 19/22] intel/compiler: lower 16-bit fmod

[Jason Ekstrand]

Rb

On May 17, 2018 01:48:33 Iago Toral Quiroga  wrote:


---
src/intel/compiler/brw_compiler.c | 1 +
1 file changed, 1 insertion(+)

diff --git a/src/intel/compiler/brw_compiler.c 
b/src/intel/compiler/brw_compiler.c

index 6480dbefbf6..36a870ece0d 100644
--- a/src/intel/compiler/brw_compiler.c
+++ b/src/intel/compiler/brw_compiler.c
@@ -33,6 +33,7 @@
   .lower_sub = true, \
   .lower_fdiv = true,\
   .lower_scmp = true,\
+   .lower_fmod16 = true,   
   \

   .lower_fmod32 = true,  \
   .lower_fmod64 = false, \
   .lower_bitfield_extract = true,\
--
2.14.1

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Re: [Mesa-dev] [PATCH 20/22] compiler/nir: add lowering for 16-bit flrp

[Jason Ekstrand]

Rb

On May 17, 2018 01:49:07 Iago Toral Quiroga  wrote:


---
src/compiler/nir/nir.h| 1 +
src/compiler/nir/nir_opt_algebraic.py | 1 +
2 files changed, 2 insertions(+)

diff --git a/src/compiler/nir/nir.h b/src/compiler/nir/nir.h
index 59c84bde268..7e4c78cc1b7 100644
--- a/src/compiler/nir/nir.h
+++ b/src/compiler/nir/nir.h
@@ -1871,6 +1871,7 @@ typedef struct nir_shader_compiler_options {
   bool lower_fdiv;
   bool lower_ffma;
   bool fuse_ffma;
+   bool lower_flrp16;
   bool lower_flrp32;
   /** Lowers flrp when it does not support doubles */
   bool lower_flrp64;
diff --git a/src/compiler/nir/nir_opt_algebraic.py 
b/src/compiler/nir/nir_opt_algebraic.py

index 1033a42a06c..75e71efcc6b 100644
--- a/src/compiler/nir/nir_opt_algebraic.py
+++ b/src/compiler/nir/nir_opt_algebraic.py
@@ -113,6 +113,7 @@ optimizations = [
   (('~flrp', 0.0, a, b), ('fmul', a, b)),
   (('~flrp', a, b, ('b2f', c)), ('bcsel', c, b, a), 'options->lower_flrp32'),
   (('~flrp', a, 0.0, c), ('fadd', ('fmul', ('fneg', a), c), a)),
+   (('flrp@16', a, b, c), ('fadd', ('fmul', c, ('fsub', b, a)), a), 
'options->lower_flrp16'),
   (('flrp@32', a, b, c), ('fadd', ('fmul', c, ('fsub', b, a)), a), 
   'options->lower_flrp32'),
   (('flrp@64', a, b, c), ('fadd', ('fmul', c, ('fsub', b, a)), a), 
   'options->lower_flrp64'),

   (('ffract', a), ('fsub', a, ('ffloor', a)), 'options->lower_ffract'),
--
2.14.1

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Re: [Mesa-dev] [PATCH 18/22] compiler/nir: add lowering option for 16-bit fmod

[Jason Ekstrand]

Rb

On May 17, 2018 01:48:27 Iago Toral Quiroga  wrote:


---
src/compiler/nir/nir.h| 1 +
src/compiler/nir/nir_opt_algebraic.py | 1 +
2 files changed, 2 insertions(+)

diff --git a/src/compiler/nir/nir.h b/src/compiler/nir/nir.h
index a379928cdcd..59c84bde268 100644
--- a/src/compiler/nir/nir.h
+++ b/src/compiler/nir/nir.h
@@ -1877,6 +1877,7 @@ typedef struct nir_shader_compiler_options {
   bool lower_fpow;
   bool lower_fsat;
   bool lower_fsqrt;
+   bool lower_fmod16;
   bool lower_fmod32;
   bool lower_fmod64;
   bool lower_bitfield_extract;
diff --git a/src/compiler/nir/nir_opt_algebraic.py 
b/src/compiler/nir/nir_opt_algebraic.py

index 96232f0e549..1033a42a06c 100644
--- a/src/compiler/nir/nir_opt_algebraic.py
+++ b/src/compiler/nir/nir_opt_algebraic.py
@@ -481,6 +481,7 @@ optimizations = [
   (('bcsel', ('ine', a, -1), ('ifind_msb', a), -1), ('ifind_msb', a)),

   # Misc. lowering
+   (('fmod@16', a, b), ('fsub', a, ('fmul', b, ('ffloor', ('fdiv', a, 
b, 'options->lower_fmod16'),
   (('fmod@32', a, b), ('fsub', a, ('fmul', b, ('ffloor', ('fdiv', a, b, 
   'options->lower_fmod32'),
   (('fmod@64', a, b), ('fsub', a, ('fmul', b, ('ffloor', ('fdiv', a, b, 
   'options->lower_fmod64'),
   (('frem', a, b), ('fsub', a, ('fmul', b, ('ftrunc', ('fdiv', a, b, 
   'options->lower_fmod32'),

--
2.14.1

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Re: [Mesa-dev] [PATCH 15/22] compiler/spirv: implement 16-bit exp and log

[Jason Ekstrand]

Rb

On May 17, 2018 01:48:43 Iago Toral Quiroga  wrote:


---
src/compiler/spirv/vtn_glsl450.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/src/compiler/spirv/vtn_glsl450.c 
b/src/compiler/spirv/vtn_glsl450.c

index 70e3eb80c4c..324e8b5874a 100644
--- a/src/compiler/spirv/vtn_glsl450.c
+++ b/src/compiler/spirv/vtn_glsl450.c
@@ -194,7 +194,7 @@ build_fclamp(nir_builder *b,
static nir_ssa_def *
build_exp(nir_builder *b, nir_ssa_def *x)
{
-   return nir_fexp2(b, nir_fmul(b, x, nir_imm_float(b, M_LOG2E)));
+   return nir_fexp2(b, nir_fmul(b, x, nir_imm_floatN_t(b, M_LOG2E, 
x->bit_size)));

}

/**
@@ -203,7 +203,8 @@ build_exp(nir_builder *b, nir_ssa_def *x)
static nir_ssa_def *
build_log(nir_builder *b, nir_ssa_def *x)
{
-   return nir_fmul(b, nir_flog2(b, x), nir_imm_float(b, 1.0 / M_LOG2E));
+   return nir_fmul(b, nir_flog2(b, x),
+  nir_imm_floatN_t(b, 1.0 / M_LOG2E, x->bit_size));
}

/**
--
2.14.1

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Re: [Mesa-dev] [PATCH 2/4] mesa: Remove flush_vertrices argument from VAO methods.

[Brian Paul]

In the subject line "flush_vertices"

For this series, Reviewed-by: Brian Paul 

More nice clean-ups!

-Brian


On 05/17/2018 12:37 AM, mathias.froehl...@gmx.net wrote:

From: Mathias Fröhlich 

The flush_vertices argument is now unused, remove it.

Signed-off-by: Mathias Fröhlich 
---
  src/mesa/drivers/common/meta.c   | 32 ++-
  src/mesa/main/bufferobj.c|  2 +-
  src/mesa/main/enable.c   |  4 +--
  src/mesa/main/varray.c   | 44 +++-
  src/mesa/main/varray.h   |  8 +++---
  src/mesa/state_tracker/st_cb_rasterpos.c |  4 +--
  src/mesa/vbo/vbo_context.c   |  2 +-
  src/mesa/vbo/vbo_exec_draw.c |  6 ++---
  src/mesa/vbo/vbo_save_api.c  |  6 ++---
  9 files changed, 51 insertions(+), 57 deletions(-)


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Re: [Mesa-dev] [PATCH 07/22] compiler/spirv: handle 16-bit float in radians() and degrees()

[Jason Ekstrand]

Rb

On May 17, 2018 01:48:03 Iago Toral Quiroga  wrote:


---
src/compiler/spirv/vtn_glsl450.c | 10 --
1 file changed, 8 insertions(+), 2 deletions(-)

diff --git a/src/compiler/spirv/vtn_glsl450.c 
b/src/compiler/spirv/vtn_glsl450.c

index 6fa759b1bba..ffe12a71818 100644
--- a/src/compiler/spirv/vtn_glsl450.c
+++ b/src/compiler/spirv/vtn_glsl450.c
@@ -540,11 +540,17 @@ handle_glsl450_alu(struct vtn_builder *b, enum 
GLSLstd450 entrypoint,


   switch (entrypoint) {
   case GLSLstd450Radians:
-  val->ssa->def = nir_fmul(nb, src[0], nir_imm_float(nb, 0.01745329251));
+  val->ssa->def = nir_fmul(nb, src[0],
+   nir_imm_floatN_t(nb, 0.01745329251,
+src[0]->bit_size));
  return;
+
   case GLSLstd450Degrees:
-  val->ssa->def = nir_fmul(nb, src[0], nir_imm_float(nb, 57.2957795131));
+  val->ssa->def = nir_fmul(nb, src[0],
+   nir_imm_floatN_t(nb, 57.2957795131,
+src[0]->bit_size));
  return;
+
   case GLSLstd450Tan:
  val->ssa->def = nir_fdiv(nb, nir_fsin(nb, src[0]),
   nir_fcos(nb, src[0]));
--
2.14.1

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Re: [Mesa-dev] [PATCH 06/22] compiler/nir: support 16-bit float in nir_imm_floatN_t

[Jason Ekstrand]

Why did the function move?

On May 17, 2018 01:47:51 Iago Toral Quiroga  wrote:


---
src/compiler/nir/nir_builder.h | 29 -
1 file changed, 16 insertions(+), 13 deletions(-)

diff --git a/src/compiler/nir/nir_builder.h b/src/compiler/nir/nir_builder.h
index 02a9dbfb040..198c42dd823 100644
--- a/src/compiler/nir/nir_builder.h
+++ b/src/compiler/nir/nir_builder.h
@@ -25,6 +25,7 @@
#define NIR_BUILDER_H

#include "nir_control_flow.h"
+#include "util/half_float.h"

struct exec_list;

@@ -227,19 +228,6 @@ nir_imm_double(nir_builder *build, double x)
   return nir_build_imm(build, 1, 64, v);
}

-static inline nir_ssa_def *
-nir_imm_floatN_t(nir_builder *build, double x, unsigned bit_size)
-{
-   switch (bit_size) {
-   case 32:
-  return nir_imm_float(build, x);
-   case 64:
-  return nir_imm_double(build, x);
-   }
-
-   unreachable("unknown float immediate bit size");
-}
-
static inline nir_ssa_def *
nir_imm_vec4(nir_builder *build, float x, float y, float z, float w)
{
@@ -288,6 +276,21 @@ nir_imm_intN_t(nir_builder *build, uint64_t x, 
unsigned bit_size)

   return nir_build_imm(build, 1, bit_size, v);
}

+static inline nir_ssa_def *
+nir_imm_floatN_t(nir_builder *build, double x, unsigned bit_size)
+{
+   switch (bit_size) {
+   case 16:
+  return nir_imm_intN_t(build, _mesa_float_to_half((float)x), 16);
+   case 32:
+  return nir_imm_float(build, x);
+   case 64:
+  return nir_imm_double(build, x);
+   }
+
+   unreachable("unknown float immediate bit size");
+}
+
static inline nir_ssa_def *
nir_imm_ivec4(nir_builder *build, int x, int y, int z, int w)
{
--
2.14.1

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Re: [Mesa-dev] [PATCH 03/22] compiler/spirv: fix SpvOpIsInf for 16-bit float

[Jason Ekstrand]

On May 17, 2018 01:47:11 Iago Toral Quiroga  wrote:


---
src/compiler/spirv/vtn_alu.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/src/compiler/spirv/vtn_alu.c b/src/compiler/spirv/vtn_alu.c
index 5f9cc97fdfb..62a5149797a 100644
--- a/src/compiler/spirv/vtn_alu.c
+++ b/src/compiler/spirv/vtn_alu.c
@@ -578,7 +578,9 @@ vtn_handle_alu(struct vtn_builder *b, SpvOp opcode,
  break;

   case SpvOpIsInf: {
-  nir_ssa_def *inf = nir_imm_floatN_t(>nb, INFINITY, src[0]->bit_size);
+  nir_ssa_def *inf = src[0]->bit_size > 16 ?
+ nir_imm_floatN_t(>nb, INFINITY, src[0]->bit_size) :
+ nir_imm_intN_t(>nb, 0x7c00, 16);


We should just make nir_imm_floatN_t handle 16-bit floats with 
_mesa_float_to_half().



  val->ssa->def = nir_ieq(>nb, nir_fabs(>nb, src[0]), inf);
  break;
   }
--
2.14.1

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[Mesa-dev] [PATCH 2/2] radv: add radv_emit_shader_pointer() helper

[Samuel Pitoiset]

For future work (support for 32-bit GPU pointers).

Signed-off-by: Samuel Pitoiset 
---
 src/amd/vulkan/radv_cmd_buffer.c | 13 ++---
 src/amd/vulkan/radv_device.c | 17 +++--
 src/amd/vulkan/radv_private.h|  3 +++
 3 files changed, 20 insertions(+), 13 deletions(-)

diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c
index 1ca687494a..a8359ac092 100644
--- a/src/amd/vulkan/radv_cmd_buffer.c
+++ b/src/amd/vulkan/radv_cmd_buffer.c
@@ -587,9 +587,9 @@ radv_emit_userdata_address(struct radv_cmd_buffer 
*cmd_buffer,
return;
assert(loc->num_sgprs == 2);
assert(!loc->indirect);
-   radeon_set_sh_reg_seq(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, 2);
-   radeon_emit(cmd_buffer->cs, va);
-   radeon_emit(cmd_buffer->cs, va >> 32);
+
+   radv_emit_shader_pointer(cmd_buffer->cs,
+base_reg + loc->sgpr_idx * 4, va);
 }
 
 static void
@@ -1442,10 +1442,9 @@ emit_stage_descriptor_set_userdata(struct 
radv_cmd_buffer *cmd_buffer,
 
assert(!desc_set_loc->indirect);
assert(desc_set_loc->num_sgprs == 2);
-   radeon_set_sh_reg_seq(cmd_buffer->cs,
- base_reg + desc_set_loc->sgpr_idx * 4, 2);
-   radeon_emit(cmd_buffer->cs, va);
-   radeon_emit(cmd_buffer->cs, va >> 32);
+
+   radv_emit_shader_pointer(cmd_buffer->cs,
+base_reg + desc_set_loc->sgpr_idx * 4, va);
 }
 
 static void
diff --git a/src/amd/vulkan/radv_device.c b/src/amd/vulkan/radv_device.c
index fa07ec40f3..91ab729d86 100644
--- a/src/amd/vulkan/radv_device.c
+++ b/src/amd/vulkan/radv_device.c
@@ -1941,6 +1941,15 @@ radv_emit_compute_scratch(struct radv_queue *queue, 
struct radeon_winsys_cs *cs,
S_008F04_SWIZZLE_ENABLE(1));
 }
 
+void
+radv_emit_shader_pointer(struct radeon_winsys_cs *cs,
+uint32_t sh_offset, uint64_t va)
+{
+   radeon_set_sh_reg_seq(cs, sh_offset, 2);
+   radeon_emit(cs, va);
+   radeon_emit(cs, va >> 32);
+}
+
 static void
 radv_emit_global_shader_pointers(struct radv_queue *queue,
 struct radeon_winsys_cs *cs,
@@ -1962,9 +1971,7 @@ radv_emit_global_shader_pointers(struct radv_queue *queue,
   R_00B408_SPI_SHADER_USER_DATA_ADDR_LO_HS};
 
for (int i = 0; i < ARRAY_SIZE(regs); ++i) {
-   radeon_set_sh_reg_seq(cs, regs[i], 2);
-   radeon_emit(cs, va);
-   radeon_emit(cs, va >> 32);
+   radv_emit_shader_pointer(cs, regs[i], va);
}
} else {
uint32_t regs[] = {R_00B030_SPI_SHADER_USER_DATA_PS_0,
@@ -1975,9 +1982,7 @@ radv_emit_global_shader_pointers(struct radv_queue *queue,
   R_00B530_SPI_SHADER_USER_DATA_LS_0};
 
for (int i = 0; i < ARRAY_SIZE(regs); ++i) {
-   radeon_set_sh_reg_seq(cs, regs[i], 2);
-   radeon_emit(cs, va);
-   radeon_emit(cs, va >> 32);
+   radv_emit_shader_pointer(cs, regs[i], va);
}
}
 }
diff --git a/src/amd/vulkan/radv_private.h b/src/amd/vulkan/radv_private.h
index 304ed17f01..05733c7eb9 100644
--- a/src/amd/vulkan/radv_private.h
+++ b/src/amd/vulkan/radv_private.h
@@ -1128,6 +1128,9 @@ bool radv_get_memory_fd(struct radv_device *device,
struct radv_device_memory *memory,
int *pFD);
 
+void radv_emit_shader_pointer(struct radeon_winsys_cs *cs,
+ uint32_t sh_offset, uint64_t va);
+
 static inline struct radv_descriptor_state *
 radv_get_descriptors_state(struct radv_cmd_buffer *cmd_buffer,
   VkPipelineBindPoint bind_point)
-- 
2.17.0

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[Mesa-dev] [PATCH 1/2] radv: add some helpers for cleaning up radv_get_preamble_cs()

[Samuel Pitoiset]

Because this function looks a bit ugly to me.

Signed-off-by: Samuel Pitoiset 
---
 src/amd/vulkan/radv_device.c | 214 +--
 1 file changed, 128 insertions(+), 86 deletions(-)

diff --git a/src/amd/vulkan/radv_device.c b/src/amd/vulkan/radv_device.c
index e24b8c2a76..fa07ec40f3 100644
--- a/src/amd/vulkan/radv_device.c
+++ b/src/amd/vulkan/radv_device.c
@@ -1860,6 +1860,128 @@ radv_get_hs_offchip_param(struct radv_device *device, 
uint32_t *max_offchip_buff
return hs_offchip_param;
 }
 
+static void
+radv_emit_gs_ring_sizes(struct radv_queue *queue, struct radeon_winsys_cs *cs,
+   struct radeon_winsys_bo *esgs_ring_bo,
+   uint32_t esgs_ring_size,
+   struct radeon_winsys_bo *gsvs_ring_bo,
+   uint32_t gsvs_ring_size)
+{
+   if (!esgs_ring_bo && !gsvs_ring_bo)
+   return;
+
+   if (esgs_ring_bo)
+   radv_cs_add_buffer(queue->device->ws, cs, esgs_ring_bo, 8);
+
+   if (gsvs_ring_bo)
+   radv_cs_add_buffer(queue->device->ws, cs, gsvs_ring_bo, 8);
+
+   if (queue->device->physical_device->rad_info.chip_class >= CIK) {
+   radeon_set_uconfig_reg_seq(cs, R_030900_VGT_ESGS_RING_SIZE, 2);
+   radeon_emit(cs, esgs_ring_size >> 8);
+   radeon_emit(cs, gsvs_ring_size >> 8);
+   } else {
+   radeon_set_config_reg_seq(cs, R_0088C8_VGT_ESGS_RING_SIZE, 2);
+   radeon_emit(cs, esgs_ring_size >> 8);
+   radeon_emit(cs, gsvs_ring_size >> 8);
+   }
+}
+
+static void
+radv_emit_tess_factor_ring(struct radv_queue *queue, struct radeon_winsys_cs 
*cs,
+  unsigned hs_offchip_param, unsigned tf_ring_size,
+  struct radeon_winsys_bo *tess_rings_bo)
+{
+   uint64_t tf_va;
+
+   if (!tess_rings_bo)
+   return;
+
+   tf_va = radv_buffer_get_va(tess_rings_bo);
+
+   radv_cs_add_buffer(queue->device->ws, cs, tess_rings_bo, 8);
+
+   if (queue->device->physical_device->rad_info.chip_class >= CIK) {
+   radeon_set_uconfig_reg(cs, R_030938_VGT_TF_RING_SIZE,
+  S_030938_SIZE(tf_ring_size / 4));
+   radeon_set_uconfig_reg(cs, R_030940_VGT_TF_MEMORY_BASE,
+  tf_va >> 8);
+   if (queue->device->physical_device->rad_info.chip_class >= 
GFX9) {
+   radeon_set_uconfig_reg(cs, 
R_030944_VGT_TF_MEMORY_BASE_HI,
+  S_030944_BASE_HI(tf_va >> 40));
+   }
+   radeon_set_uconfig_reg(cs, R_03093C_VGT_HS_OFFCHIP_PARAM,
+  hs_offchip_param);
+   } else {
+   radeon_set_config_reg(cs, R_008988_VGT_TF_RING_SIZE,
+ S_008988_SIZE(tf_ring_size / 4));
+   radeon_set_config_reg(cs, R_0089B8_VGT_TF_MEMORY_BASE,
+ tf_va >> 8);
+   radeon_set_config_reg(cs, R_0089B0_VGT_HS_OFFCHIP_PARAM,
+hs_offchip_param);
+   }
+}
+
+static void
+radv_emit_compute_scratch(struct radv_queue *queue, struct radeon_winsys_cs 
*cs,
+ struct radeon_winsys_bo *compute_scratch_bo)
+{
+   uint64_t scratch_va;
+
+   if (!compute_scratch_bo)
+   return;
+
+   scratch_va = radv_buffer_get_va(compute_scratch_bo);
+
+   radv_cs_add_buffer(queue->device->ws, cs, compute_scratch_bo, 8);
+
+   radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0, 2);
+   radeon_emit(cs, scratch_va);
+   radeon_emit(cs, S_008F04_BASE_ADDRESS_HI(scratch_va >> 32) |
+   S_008F04_SWIZZLE_ENABLE(1));
+}
+
+static void
+radv_emit_global_shader_pointers(struct radv_queue *queue,
+struct radeon_winsys_cs *cs,
+struct radeon_winsys_bo *descriptor_bo)
+{
+   uint64_t va;
+
+   if (!descriptor_bo)
+   return;
+
+   va = radv_buffer_get_va(descriptor_bo);
+
+   radv_cs_add_buffer(queue->device->ws, cs, descriptor_bo, 8);
+
+   if (queue->device->physical_device->rad_info.chip_class >= GFX9) {
+   uint32_t regs[] = {R_00B030_SPI_SHADER_USER_DATA_PS_0,
+  R_00B130_SPI_SHADER_USER_DATA_VS_0,
+  R_00B208_SPI_SHADER_USER_DATA_ADDR_LO_GS,
+  R_00B408_SPI_SHADER_USER_DATA_ADDR_LO_HS};
+
+   for (int i = 0; i < ARRAY_SIZE(regs); ++i) {
+   radeon_set_sh_reg_seq(cs, regs[i], 2);
+   radeon_emit(cs, va);
+   radeon_emit(cs, va >> 32);
+   }
+   } else {
+   uint32_t regs[] = {R_00B030_SPI_SHADER_USER_DATA_PS_0,
+   

[Mesa-dev] [PATCH mesa] i965: Check result of make_surface() for miptree_create

[Eric Engestrom]

From: Andrea Azzarone 

Since make_surface() can fail we need to check the result before dereferencing 
it.

Bug: https://github.com/mesa3d/mesa/pull/5
Bug: https://bugs.launchpad.net/ubuntu/+source/gnome-shell/+bug/1760415
Reviewed-by: Eric Engestrom 
---
Andrea: We don't use github, I only happened to notice your pull request :)
Next time you want to send us something, send it here :P
---
 src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c 
b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
index 67086ee6c0e8d6b6feb0..43687ea77abfe9989882 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
@@ -718,6 +718,9 @@ miptree_create(struct brw_context *brw,
  ISL_SURF_USAGE_DEPTH_BIT | ISL_SURF_USAGE_TEXTURE_BIT,
  BO_ALLOC_BUSY, 0, NULL);
 
+  if (!mt)
+ return NULL;
+
   if (needs_separate_stencil(brw, mt, format) &&
   !make_separate_stencil_surface(brw, mt)) {
  intel_miptree_release();
-- 
Cheers,
  Eric

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Re: [Mesa-dev] [PATCH] autotools, meson: add tileset.h

[Eric Engestrom]

On Monday, 2018-05-14 11:05:34 -0700, Dylan Baker wrote:
> Quoting Eric Engestrom (2018-05-14 06:09:59)
> > 
> > Dylan, what do you think? Do we want to remove all the unnecessary
> > files() from meson, or keep them to mirror what was needed by autotools?
> > I'd vote 'remove', but the "let's do the same thing everywhere" argument
> > is valid; what do people think?
> > 
> 
> I vote that we be consistent (which unfortunately I have been really bad 
> about).
> Not tracking headers sounds easier, so I have a preference for that.

Started working on it, WIP on my github:
https://github.com/mesa3d/mesa/compare/master...1ace:meson/drop-included-headers
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Re: [Mesa-dev] [PATCH 1/3] mesa/main/shaderapi: Use generate_sha1() unconditionally

[Benedikt Schemmer]

I looked at the appveyor log for that specific build
https://ci.appveyor.com/project/mesa3d/mesa/build/3186

It seems to only complain about
disk_cache.c
src\util\disk_cache.c(28) : fatal error C1083: Cannot open include file: 
'sys/file.h': No such file or directory
scons: *** [build\windows-x86-debug\util\disk_cache.obj] Error 2
scons: building terminated because of errors.


Found this on
https://stackoverflow.com/questions/2537960/windows-sys-file-h-equivalent

For the benefit of posterity,  is the BSD version of low-level file 
I/O routines.
Depending upon your compiler installation and build environment, you'll 
probably want  instead.
Most of the usual I/O routines are in , even setvbuf() which is pretty 
low-level control.
You'll want  or  if you want I/O routines/settings that 
don't normally exist under
Linux (or the other *NICES).

Am 17.05.2018 um 12:28 schrieb Tapani Pälli:
> 
> 
> On 05/17/2018 11:38 AM, Benedikt Schemmer wrote:
>> Thanks for reviewing!
>>
>> Am 17.05.2018 um 08:42 schrieb Tapani Pälli:
>>>
>>>
>>> On 05/10/2018 12:05 PM, Benedikt Schemmer wrote:
 Move shader-cache code from back to front and make generate_sha1() usable
 unconditionally to avoid code duplication in the following patch

 ---
    src/mesa/main/shaderapi.c | 228 
 +++---
    1 file changed, 116 insertions(+), 112 deletions(-)

 diff --git a/src/mesa/main/shaderapi.c b/src/mesa/main/shaderapi.c
 index 44b18af492..e8acca4490 100644
 --- a/src/mesa/main/shaderapi.c
 +++ b/src/mesa/main/shaderapi.c
 @@ -64,6 +64,122 @@
    #include "util/mesa-sha1.h"
    #include "util/crc32.h"

 +
 +/**
 + * Generate a SHA-1 hash value string for given source string.
 + */
 +static void
 +generate_sha1(const char *source, char sha_str[64])
 +{
 +   unsigned char sha[20];
 +   _mesa_sha1_compute(source, strlen(source), sha);
 +   _mesa_sha1_format(sha_str, sha);
 +}
>>>
>>> There is one potential problem here. The 'ENABLE_SHADER_CACHE' guard for 
>>> generate_sha1 and others was placed there because the imported sha1 code 
>>> broke windows build, I'm wondering if this is still
>>> the case? If so, then generate_sha1 should be inside ENABLE_SHADER_CACHE 
>>> guard.
>>>
>>
>> I did a quick
>> gedit $(grep -Rlsi "_mesa_sha1_compute" | grep -E "\.c|\.h")
>>
>> and it seems radv and anv use _mesa_sha1_compute (and _mesa_sha1_format) 
>> without a guard
>> best example from Intel seems to be brw_disk_cache.c which uses it alot 
>> outside of the ENABLE_SHADER_CACHE guard
>>
>> so probably safe?
> 
> AFAIK none of those things are compiled on windows. IIUC windows builds are 
> about Mesa core and gallium side.
> 
 +
 +
 +#ifdef ENABLE_SHADER_CACHE
 +/**
 + * Construct a full path for shader replacement functionality using
 + * following format:
 + *
 + * /_.glsl
 + */
 +static char *
 +construct_name(const gl_shader_stage stage, const char *source,
 +   const char *path)
 +{
 +   char sha[64];
 +   static const char *types[] = {
 +  "VS", "TC", "TE", "GS", "FS", "CS",
 +   };
 +
 +   generate_sha1(source, sha);
 +   return ralloc_asprintf(NULL, "%s/%s_%s.glsl", path, types[stage], sha);
 +}
 +
 +/**
 + * Write given shader source to a file in MESA_SHADER_DUMP_PATH.
 + */
 +static void
 +dump_shader(const gl_shader_stage stage, const char *source)
 +{
 +   static bool path_exists = true;
 +   char *dump_path;
 +   FILE *f;
 +
 +   if (!path_exists)
 +  return;
 +
 +   dump_path = getenv("MESA_SHADER_DUMP_PATH");
 +   if (!dump_path) {
 +  path_exists = false;
 +  return;
 +   }
 +
 +   char *name = construct_name(stage, source, dump_path);
 +
 +   f = fopen(name, "w");
 +   if (f) {
 +  fputs(source, f);
 +  fclose(f);
 +   } else {
 +  GET_CURRENT_CONTEXT(ctx);
 +  _mesa_warning(ctx, "could not open %s for dumping shader (%s)", 
 name,
 +    strerror(errno));
 +   }
 +   ralloc_free(name);
 +}
 +
 +/**
 + * Read shader source code from a file.
 + * Useful for debugging to override an app's shader.
 + */
 +static GLcharARB *
 +read_shader(const gl_shader_stage stage, const char *source)
 +{
 +   char *read_path;
 +   static bool path_exists = true;
 +   int len, shader_size = 0;
 +   GLcharARB *buffer;
 +   FILE *f;
 +
 +   if (!path_exists)
 +  return NULL;
 +
 +   read_path = getenv("MESA_SHADER_READ_PATH");
 +   if (!read_path) {
 +  path_exists = false;
 +  return NULL;
 +   }
 +
 +   char *name = construct_name(stage, source, read_path);
 +   f = fopen(name, "r");
 +   ralloc_free(name);
 +   if 

Re: [Mesa-dev] [PATCH 09/22] intel/compiler: implement 16-bit multiply-add

[Eero Tamminen]

Hi,

On 17.05.2018 11:46, Iago Toral Quiroga wrote:

The PRM for MAD states that F, DF and HF are supported, however, then
it requires that the instruction includes a 2-bit mask specifying
the types of each operand like this:

>

00: 32-bit float
01: 32-bit signed integer
10: 32-bit unsigned integer
11: 64-bit float


Where this was?


In 
https://01.org/sites/default/files/documentation/intel-gfx-bspec-osrc-chv-bsw-vol07-3d-media-gpgpu-engine.pdf


Section "EU Changes by Processor Generation" states:
-
These features or behaviors are added for CHV, BSW, continuing to later 
generations:

...
In the 3-source instruction format, widen the SrcType and DstType fields 
and add an encoding for the HF (Half Float) type.

-

(I.e. it applies to GEN9+ [1] and on GEN8 for BSW/CHV.)


In section "GEN Instruction Format – 3-src" table, both "Dst Type" and 
"Src Type" fields are 3 bits, and there's additional 1 bit "Src1 Type" 
and "Src2 Type" fields to differentiate formats for src1 & src2.



Then, when looking at "Source or Destination Operand Fields 
(Alphabetically by Short Name)" section:

---
DstType:

Encoding for three source instructions:
000b = :f. Single precision Float (32-bit).
001b = :d. Signed Doubleword integer.
010b = :ud. Unsigned Doubleword integer.
011b = :df. Double precision Float (64-bit).
100b = :hf. Half precision Float (16-bit).
101b - 111b. Reserved.

...

SrcType:

Three source instructions use one SrcType field for all source operands, 
with a 3-bit encoding that allows fewer data types:


Encoding for three source instructions:
000b = :f. Single precision Float (32-bit).
001b = :d. Signed Doubleword integer.
010b = :ud. Unsigned Doubleword integer.
011b = :df. Double precision Float (64-bit).
100b = :hf. Half precision Float (16-bit).
101b - 111b. Reserved.

Three source instructions can use operands with mixed-mode precision. 
When SrcType field is set to :f or :hf it defines precision for source 0 
only, and fields Src1Type and Src2Type define precision for other source 
operands:

0b = :f. Single precision Float (32-bit).
1b = :hf. Half precision Float (16-bit).
---


- Eero

[1]: SkyLake & KabyLake PRMs lists same amount of bits, but don't tell 
what they represent (often one needs to look into PRM for the HW where 
these changes were first introduced, which in this case was Braswell / 
Cherryview).




So 16-bit float would not be supported.  The driver also asserts that
the types involved in ALING16 3-src operations are one of these
(MAD is always emitted as an align16 instruction prior to gen10).
---
  src/intel/compiler/brw_fs_nir.cpp | 9 -
  1 file changed, 8 insertions(+), 1 deletion(-)

diff --git a/src/intel/compiler/brw_fs_nir.cpp 
b/src/intel/compiler/brw_fs_nir.cpp
index 91283ab4911..58ddc456bae 100644
--- a/src/intel/compiler/brw_fs_nir.cpp
+++ b/src/intel/compiler/brw_fs_nir.cpp
@@ -1525,7 +1525,14 @@ fs_visitor::nir_emit_alu(const fs_builder , 
nir_alu_instr *instr)
break;
  
 case nir_op_ffma:

-  inst = bld.MAD(result, op[2], op[1], op[0]);
+  /* 3-src MAD doesn't support 16-bit operands */
+  if (nir_dest_bit_size(instr->dest.dest) >= 32) {
+ inst = bld.MAD(result, op[2], op[1], op[0]);
+  } else {
+ fs_reg tmp = bld.vgrf(BRW_REGISTER_TYPE_HF);
+ bld.MUL(tmp, op[1], op[0]);
+ inst = bld.ADD(result, tmp, op[2]);
+  }
inst->saturate = instr->dest.saturate;
break;
  



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Re: [Mesa-dev] [PATCH 1/3] mesa/main/shaderapi: Use generate_sha1() unconditionally

[Benedikt Schemmer]

Ok I found the commit.
But it says: "Until we have a proper fix."
So this would be a good time I guess ;)


---

author  Emil Velikov    2017-01-18 19:40:31 
+
committer   Emil Velikov  2017-01-18 20:09:01 
+
commit  9f8dc3bf03ec825bae7041858dda6ca2e9a34363 (patch)
treeff9672995474d3c31f027fea8356cb5733e45388
parent  d1efa09d342bff3e5def2978a0bef748d74f9c82 (diff)
utils: build sha1/disk cache only with Android/Autoconf
Earlier commit imported a SHA1 implementation and relaxed the SHA1 and
disk cache handling, broking the Windows builds.

Restrict things for now until we get to a proper fix.

Fixes: d1efa09d342 "util: import sha1 implementation from OpenBSD"
Signed-off-by: Emil Velikov 


Am 17.05.2018 um 12:28 schrieb Tapani Pälli:
> 
> 
> On 05/17/2018 11:38 AM, Benedikt Schemmer wrote:
>> Thanks for reviewing!
>>
>> Am 17.05.2018 um 08:42 schrieb Tapani Pälli:
>>>
>>>
>>> On 05/10/2018 12:05 PM, Benedikt Schemmer wrote:
 Move shader-cache code from back to front and make generate_sha1() usable
 unconditionally to avoid code duplication in the following patch

 ---
    src/mesa/main/shaderapi.c | 228 
 +++---
    1 file changed, 116 insertions(+), 112 deletions(-)

 diff --git a/src/mesa/main/shaderapi.c b/src/mesa/main/shaderapi.c
 index 44b18af492..e8acca4490 100644
 --- a/src/mesa/main/shaderapi.c
 +++ b/src/mesa/main/shaderapi.c
 @@ -64,6 +64,122 @@
    #include "util/mesa-sha1.h"
    #include "util/crc32.h"

 +
 +/**
 + * Generate a SHA-1 hash value string for given source string.
 + */
 +static void
 +generate_sha1(const char *source, char sha_str[64])
 +{
 +   unsigned char sha[20];
 +   _mesa_sha1_compute(source, strlen(source), sha);
 +   _mesa_sha1_format(sha_str, sha);
 +}
>>>
>>> There is one potential problem here. The 'ENABLE_SHADER_CACHE' guard for 
>>> generate_sha1 and others was placed there because the imported sha1 code 
>>> broke windows build, I'm wondering if this is still
>>> the case? If so, then generate_sha1 should be inside ENABLE_SHADER_CACHE 
>>> guard.
>>>
>>
>> I did a quick
>> gedit $(grep -Rlsi "_mesa_sha1_compute" | grep -E "\.c|\.h")
>>
>> and it seems radv and anv use _mesa_sha1_compute (and _mesa_sha1_format) 
>> without a guard
>> best example from Intel seems to be brw_disk_cache.c which uses it alot 
>> outside of the ENABLE_SHADER_CACHE guard
>>
>> so probably safe?
> 
> AFAIK none of those things are compiled on windows. IIUC windows builds are 
> about Mesa core and gallium side.
> 
 +
 +
 +#ifdef ENABLE_SHADER_CACHE
 +/**
 + * Construct a full path for shader replacement functionality using
 + * following format:
 + *
 + * /_.glsl
 + */
 +static char *
 +construct_name(const gl_shader_stage stage, const char *source,
 +   const char *path)
 +{
 +   char sha[64];
 +   static const char *types[] = {
 +  "VS", "TC", "TE", "GS", "FS", "CS",
 +   };
 +
 +   generate_sha1(source, sha);
 +   return ralloc_asprintf(NULL, "%s/%s_%s.glsl", path, types[stage], sha);
 +}
 +
 +/**
 + * Write given shader source to a file in MESA_SHADER_DUMP_PATH.
 + */
 +static void
 +dump_shader(const gl_shader_stage stage, const char *source)
 +{
 +   static bool path_exists = true;
 +   char *dump_path;
 +   FILE *f;
 +
 +   if (!path_exists)
 +  return;
 +
 +   dump_path = getenv("MESA_SHADER_DUMP_PATH");
 +   if (!dump_path) {
 +  path_exists = false;
 +  return;
 +   }
 +
 +   char *name = construct_name(stage, source, dump_path);
 +
 +   f = fopen(name, "w");
 +   if (f) {
 +  fputs(source, f);
 +  fclose(f);
 +   } else {
 +  GET_CURRENT_CONTEXT(ctx);
 +  _mesa_warning(ctx, "could not open %s for dumping shader (%s)", 
 name,
 +    strerror(errno));
 +   }
 +   ralloc_free(name);
 +}
 +
 +/**
 + * Read shader source code from a file.
 + * Useful for debugging to override an app's shader.
 + */
 +static GLcharARB *
 +read_shader(const gl_shader_stage stage, const char *source)
 +{
 +   char *read_path;
 +   static bool path_exists = true;
 +   int len, shader_size = 0;
 +   GLcharARB *buffer;
 +   FILE *f;
 +
 +   if (!path_exists)
 +  return NULL;
 +
 +   read_path = getenv("MESA_SHADER_READ_PATH");
 +   if (!read_path) {
 +  path_exists = false;
 +  return NULL;
 +   }
 +
 +   char *name = construct_name(stage, source, read_path);
 +   f = fopen(name, "r");
 +   ralloc_free(name);
 +   if (!f)
 +  return NULL;
 +
 +   /* 

[Mesa-dev] [PATCH 0/2] st/dri format handling cleanups

[Lucas Stach]

Hi all,

those 2 patches clean up and align the format handling in the dri state
tracker to how the intel driver implements some details of the interface.

This is mostly in preparation for etnaviv to support native planar YUV
import without needing any of the R8/RG88 sampler rewrites, as those are
really costly due to some of the Vivante hardware constraints. This isn't
quite ready yet, but I wanted to get those patches out, as those have
some value on their own. Just looking at the diffstat should be motivation
enough to pull them in.

As this has the potential to break the NV12 import for drivers using the
sampler rewrite (though I think I've covered all cases) I would appreciate
some testing from the Freedreno folks, or whoever cares about this.

Regards,
Lucas

Lucas Stach (2):
  st/dri: allow both render and sampler compatible dma-buf formats
  st/dri: replace format conversion functions with single mapping table

 src/gallium/state_trackers/dri/dri2.c   | 493 ++--
 src/gallium/state_trackers/dri/dri_screen.h |   1 +
 2 files changed, 150 insertions(+), 344 deletions(-)

-- 
2.17.0

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[Mesa-dev] [PATCH 2/2] st/dri: replace format conversion functions with single mapping table

[Lucas Stach]

Each time I have to touch the buffer import/export functions in the dri
state tracker I get lost in the maze of functions converting between
DRI_IMAGE_FOURCC, DRI_IMAGE_FORMAT, DRI_IMAGE_COMPONENTS and pipe format.

Rip it out and replace by a single table, which defines the correspondence
between the different representations.

Also this now stores all the known representations in the __DRIimageRec,
to avoid the loss of information we currently have when importing a buffer
with a fourcc, which doesn't have a corresponding dri format.

Signed-off-by: Lucas Stach 
---
 src/gallium/state_trackers/dri/dri2.c   | 476 ++--
 src/gallium/state_trackers/dri/dri_screen.h |   1 +
 2 files changed, 138 insertions(+), 339 deletions(-)

diff --git a/src/gallium/state_trackers/dri/dri2.c 
b/src/gallium/state_trackers/dri/dri2.c
index 859161fb87ac..9c74ca54fc89 100644
--- a/src/gallium/state_trackers/dri/dri2.c
+++ b/src/gallium/state_trackers/dri/dri2.c
@@ -54,295 +54,72 @@
 #define DRM_FORMAT_MOD_INVALID ((1ULL<<56) - 1)
 #endif
 
-static const int fourcc_formats[] = {
-   __DRI_IMAGE_FOURCC_ARGB2101010,
-   __DRI_IMAGE_FOURCC_XRGB2101010,
-   __DRI_IMAGE_FOURCC_ABGR2101010,
-   __DRI_IMAGE_FOURCC_XBGR2101010,
-   __DRI_IMAGE_FOURCC_ARGB,
-   __DRI_IMAGE_FOURCC_ABGR,
-   __DRI_IMAGE_FOURCC_SARGB,
-   __DRI_IMAGE_FOURCC_XRGB,
-   __DRI_IMAGE_FOURCC_XBGR,
-   __DRI_IMAGE_FOURCC_ARGB1555,
-   __DRI_IMAGE_FOURCC_RGB565,
-   __DRI_IMAGE_FOURCC_R8,
-   __DRI_IMAGE_FOURCC_R16,
-   __DRI_IMAGE_FOURCC_GR88,
-   __DRI_IMAGE_FOURCC_GR1616,
-   __DRI_IMAGE_FOURCC_YUV410,
-   __DRI_IMAGE_FOURCC_YUV411,
-   __DRI_IMAGE_FOURCC_YUV420,
-   __DRI_IMAGE_FOURCC_YUV422,
-   __DRI_IMAGE_FOURCC_YUV444,
-   __DRI_IMAGE_FOURCC_YVU410,
-   __DRI_IMAGE_FOURCC_YVU411,
-   __DRI_IMAGE_FOURCC_YVU420,
-   __DRI_IMAGE_FOURCC_YVU422,
-   __DRI_IMAGE_FOURCC_YVU444,
-   __DRI_IMAGE_FOURCC_NV12,
-   __DRI_IMAGE_FOURCC_NV16,
-   __DRI_IMAGE_FOURCC_YUYV
-};
-
-static int convert_fourcc(int format, int *dri_components_p)
-{
+struct dri2_format_mapping {
+   int dri_fourcc;
+   int dri_format;
int dri_components;
-   switch(format) {
-   case __DRI_IMAGE_FOURCC_RGB565:
-  format = __DRI_IMAGE_FORMAT_RGB565;
-  dri_components = __DRI_IMAGE_COMPONENTS_RGB;
-  break;
-   case __DRI_IMAGE_FOURCC_ARGB:
-  format = __DRI_IMAGE_FORMAT_ARGB;
-  dri_components = __DRI_IMAGE_COMPONENTS_RGBA;
-  break;
-   case __DRI_IMAGE_FOURCC_XRGB:
-  format = __DRI_IMAGE_FORMAT_XRGB;
-  dri_components = __DRI_IMAGE_COMPONENTS_RGB;
-  break;
-   case __DRI_IMAGE_FOURCC_ABGR:
-  format = __DRI_IMAGE_FORMAT_ABGR;
-  dri_components = __DRI_IMAGE_COMPONENTS_RGBA;
-  break;
-   case __DRI_IMAGE_FOURCC_XBGR:
-  format = __DRI_IMAGE_FORMAT_XBGR;
-  dri_components = __DRI_IMAGE_COMPONENTS_RGB;
-  break;
-   case __DRI_IMAGE_FOURCC_ARGB2101010:
-  format = __DRI_IMAGE_FORMAT_ARGB2101010;
-  dri_components = __DRI_IMAGE_COMPONENTS_RGBA;
-  break;
-   case __DRI_IMAGE_FOURCC_XRGB2101010:
-  format = __DRI_IMAGE_FORMAT_XRGB2101010;
-  dri_components = __DRI_IMAGE_COMPONENTS_RGB;
-  break;
-   case __DRI_IMAGE_FOURCC_ABGR2101010:
-  format = __DRI_IMAGE_FORMAT_ABGR2101010;
-  dri_components = __DRI_IMAGE_COMPONENTS_RGBA;
-  break;
-   case __DRI_IMAGE_FOURCC_XBGR2101010:
-  format = __DRI_IMAGE_FORMAT_XBGR2101010;
-  dri_components = __DRI_IMAGE_COMPONENTS_RGB;
-  break;
-   case __DRI_IMAGE_FOURCC_R8:
-  format = __DRI_IMAGE_FORMAT_R8;
-  dri_components = __DRI_IMAGE_COMPONENTS_R;
-  break;
-   case __DRI_IMAGE_FOURCC_GR88:
-  format = __DRI_IMAGE_FORMAT_GR88;
-  dri_components = __DRI_IMAGE_COMPONENTS_RG;
-  break;
-   case __DRI_IMAGE_FOURCC_R16:
-  format = __DRI_IMAGE_FORMAT_R16;
-  dri_components = __DRI_IMAGE_COMPONENTS_R;
-  break;
-   case __DRI_IMAGE_FOURCC_GR1616:
-  format = __DRI_IMAGE_FORMAT_GR1616;
-  dri_components = __DRI_IMAGE_COMPONENTS_RG;
-  break;
-   case __DRI_IMAGE_FOURCC_YUYV:
-  format = __DRI_IMAGE_FORMAT_YUYV;
-  dri_components = __DRI_IMAGE_COMPONENTS_Y_XUXV;
-  break;
-   /*
-* For multi-planar YUV formats, we return the format of the first
-* plane only.  Since there is only one caller which supports multi-
-* planar YUV it gets to figure out the remaining planes on it's
-* own.
-*/
-   case __DRI_IMAGE_FOURCC_YUV420:
-   case __DRI_IMAGE_FOURCC_YVU420:
-  format = __DRI_IMAGE_FORMAT_R8;
-  dri_components = __DRI_IMAGE_COMPONENTS_Y_U_V;
-  break;
-   case __DRI_IMAGE_FOURCC_NV12:
-  format = __DRI_IMAGE_FORMAT_R8;
-  dri_components = __DRI_IMAGE_COMPONENTS_Y_UV;
-  break;
-   default:
-  return -1;
-   }
-   *dri_components_p = dri_components;
-   return format;
-}
-
-/* NOTE this probably isn't going to do the right thing for YUV images
- * (but I 

[Mesa-dev] [PATCH 1/2] st/dri: allow both render and sampler compatible dma-buf formats

[Lucas Stach]

Currently all the EGL APIs are missing a way to specify how an imported
dma-buf is intended to be used. Demanding the format to be both usable
for sampling and rendering artificially restricts the list of formats a
driver is able to import.

Looking at how the Intel driver implements those DRI2 image APIs it
doesn't distinguish between render or sampler compatible formats. So
this patch aligns behavior between Intel and Gallium based drivers.

Signed-off-by: Lucas Stach 
---
 src/gallium/state_trackers/dri/dri2.c | 29 +--
 1 file changed, 18 insertions(+), 11 deletions(-)

diff --git a/src/gallium/state_trackers/dri/dri2.c 
b/src/gallium/state_trackers/dri/dri2.c
index 58a6757f037a..859161fb87ac 100644
--- a/src/gallium/state_trackers/dri/dri2.c
+++ b/src/gallium/state_trackers/dri/dri2.c
@@ -991,16 +991,21 @@ dri2_create_image_from_winsys(__DRIscreen *_screen,
struct pipe_screen *pscreen = screen->base.screen;
__DRIimage *img;
struct pipe_resource templ;
-   unsigned tex_usage;
+   unsigned tex_usage = 0;
enum pipe_format pf;
int i;
 
-   tex_usage = PIPE_BIND_RENDER_TARGET | PIPE_BIND_SAMPLER_VIEW;
-
pf = dri2_format_to_pipe_format (format);
if (pf == PIPE_FORMAT_NONE)
   return NULL;
 
+   if (pscreen->is_format_supported(pscreen, pf, screen->target, 0,
+PIPE_BIND_RENDER_TARGET))
+  tex_usage |= PIPE_BIND_RENDER_TARGET;
+   if (pscreen->is_format_supported(pscreen, pf, screen->target, 0,
+PIPE_BIND_SAMPLER_VIEW))
+  tex_usage |= PIPE_BIND_SAMPLER_VIEW;
+
img = CALLOC_STRUCT(__DRIimageRec);
if (!img)
   return NULL;
@@ -1477,16 +1482,16 @@ dri2_query_dma_buf_formats(__DRIscreen *_screen, int 
max, int *formats,
 {
struct dri_screen *screen = dri_screen(_screen);
struct pipe_screen *pscreen = screen->base.screen;
-   const unsigned bind = PIPE_BIND_RENDER_TARGET | PIPE_BIND_SAMPLER_VIEW;
int i, j;
 
for (i = 0, j = 0; (i < ARRAY_SIZE(fourcc_formats)) &&
  (j < max || max == 0); i++) {
-  if (pscreen->is_format_supported(pscreen,
-   fourcc_to_pipe_format(
-  fourcc_formats[i]),
-   screen->target,
-   0, bind)) {
+  enum pipe_format format = fourcc_to_pipe_format(fourcc_formats[i]);
+
+  if (pscreen->is_format_supported(pscreen, format, screen->target, 0,
+   PIPE_BIND_RENDER_TARGET) ||
+  pscreen->is_format_supported(pscreen, format, screen->target, 0,
+   PIPE_BIND_SAMPLER_VIEW)) {
  if (j < max)
 formats[j] = fourcc_formats[i];
  j++;
@@ -1504,10 +1509,12 @@ dri2_query_dma_buf_modifiers(__DRIscreen *_screen, int 
fourcc, int max,
struct dri_screen *screen = dri_screen(_screen);
struct pipe_screen *pscreen = screen->base.screen;
enum pipe_format format = fourcc_to_pipe_format(fourcc);
-   const unsigned usage = PIPE_BIND_RENDER_TARGET | PIPE_BIND_SAMPLER_VIEW;
 
if (pscreen->query_dmabuf_modifiers != NULL &&
-   pscreen->is_format_supported(pscreen, format, screen->target, 0, 
usage)) {
+   (pscreen->is_format_supported(pscreen, format, screen->target, 0,
+ PIPE_BIND_RENDER_TARGET) ||
+pscreen->is_format_supported(pscreen, format, screen->target, 0,
+ PIPE_BIND_SAMPLER_VIEW))) {
   pscreen->query_dmabuf_modifiers(pscreen, format, max, modifiers,
   external_only, count);
   return true;
-- 
2.17.0

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[Mesa-dev] [RFC PATCH] virgl: Always assume that ORIGIN_UPPER_LEFT and PIXEL_CENTER* are supported

[Gert Wollny]

The driver must support at least one of

  PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT
  PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT

and one of

  PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER
  PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER

otherwise glsl_to_tgsi will fire an assert.

ORIGIN_UPPER_LEFT is the default convention, and is supported by
all mesa drivers, hence it seems reasonable to always report the caps
to be enabled.  On gles ORIGIN_LOWER_LEFT is generally not supported,
so we rely on the caps reported by the host that depend on whether we
run on an GL or an EGL host.

For PIXEL_CENTER it is completely host driver dependend on what is
supported, and since we do not report the actual host driver capabilities
it is best to mark both as supported, this is how it works for a GL
host too.

Fixes:
   dEQP-GLES3.functional.shaders.builtin_variable.fragcoord_xyz
   dEQP-GLES3.functional.shaders.metamorphic.bubblesort_flag.variant_1
   dEQP-GLES3.functional.shaders.metamorphic.bubblesort_flag.variant_2

Signed-off-by: Gert Wollny 
---
When I return 1 for  PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT too, the test 
fail on an r600g gle host. Likewise, when I disable one of the two PIXEL_CENTER
caps. 

However, I send this as an RFC, because there are some of the *texture* tests 
that
flip: some start to pass with this patch and some start to fail, in total 16 
test
are fixed with this patch and 15 regress on Intel. I have not yet established 
whether
these tests are actually unsable.

thanks for any comments.
Gert

 src/gallium/drivers/virgl/virgl_screen.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/src/gallium/drivers/virgl/virgl_screen.c 
b/src/gallium/drivers/virgl/virgl_screen.c
index 1ca9e85de7..f4fdc61b14 100644
--- a/src/gallium/drivers/virgl/virgl_screen.c
+++ b/src/gallium/drivers/virgl/virgl_screen.c
@@ -88,9 +88,10 @@ virgl_get_param(struct pipe_screen *screen, enum pipe_cap 
param)
case PIPE_CAP_INDEP_BLEND_FUNC:
   return vscreen->caps.caps.v1.bset.indep_blend_func;
case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
-   case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
+  return 1;
+   case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
   return vscreen->caps.caps.v1.bset.fragment_coord_conventions;
case PIPE_CAP_DEPTH_CLIP_DISABLE:
   return vscreen->caps.caps.v1.bset.depth_clip_disable;
-- 
2.16.1

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Re: [Mesa-dev] [PATCH 1/3] mesa/main/shaderapi: Use generate_sha1() unconditionally

[Tapani Pälli]

On 05/17/2018 11:38 AM, Benedikt Schemmer wrote:

Thanks for reviewing!

Am 17.05.2018 um 08:42 schrieb Tapani Pälli:



On 05/10/2018 12:05 PM, Benedikt Schemmer wrote:

Move shader-cache code from back to front and make generate_sha1() usable
unconditionally to avoid code duplication in the following patch

---
   src/mesa/main/shaderapi.c | 228 
+++---
   1 file changed, 116 insertions(+), 112 deletions(-)

diff --git a/src/mesa/main/shaderapi.c b/src/mesa/main/shaderapi.c
index 44b18af492..e8acca4490 100644
--- a/src/mesa/main/shaderapi.c
+++ b/src/mesa/main/shaderapi.c
@@ -64,6 +64,122 @@
   #include "util/mesa-sha1.h"
   #include "util/crc32.h"

+
+/**
+ * Generate a SHA-1 hash value string for given source string.
+ */
+static void
+generate_sha1(const char *source, char sha_str[64])
+{
+   unsigned char sha[20];
+   _mesa_sha1_compute(source, strlen(source), sha);
+   _mesa_sha1_format(sha_str, sha);
+}


There is one potential problem here. The 'ENABLE_SHADER_CACHE' guard for 
generate_sha1 and others was placed there because the imported sha1 code broke 
windows build, I'm wondering if this is still
the case? If so, then generate_sha1 should be inside ENABLE_SHADER_CACHE guard.



I did a quick
gedit $(grep -Rlsi "_mesa_sha1_compute" | grep -E "\.c|\.h")

and it seems radv and anv use _mesa_sha1_compute (and _mesa_sha1_format) 
without a guard
best example from Intel seems to be brw_disk_cache.c which uses it alot outside 
of the ENABLE_SHADER_CACHE guard

so probably safe?


AFAIK none of those things are compiled on windows. IIUC windows builds 
are about Mesa core and gallium side.



+
+
+#ifdef ENABLE_SHADER_CACHE
+/**
+ * Construct a full path for shader replacement functionality using
+ * following format:
+ *
+ * /_.glsl
+ */
+static char *
+construct_name(const gl_shader_stage stage, const char *source,
+   const char *path)
+{
+   char sha[64];
+   static const char *types[] = {
+  "VS", "TC", "TE", "GS", "FS", "CS",
+   };
+
+   generate_sha1(source, sha);
+   return ralloc_asprintf(NULL, "%s/%s_%s.glsl", path, types[stage], sha);
+}
+
+/**
+ * Write given shader source to a file in MESA_SHADER_DUMP_PATH.
+ */
+static void
+dump_shader(const gl_shader_stage stage, const char *source)
+{
+   static bool path_exists = true;
+   char *dump_path;
+   FILE *f;
+
+   if (!path_exists)
+  return;
+
+   dump_path = getenv("MESA_SHADER_DUMP_PATH");
+   if (!dump_path) {
+  path_exists = false;
+  return;
+   }
+
+   char *name = construct_name(stage, source, dump_path);
+
+   f = fopen(name, "w");
+   if (f) {
+  fputs(source, f);
+  fclose(f);
+   } else {
+  GET_CURRENT_CONTEXT(ctx);
+  _mesa_warning(ctx, "could not open %s for dumping shader (%s)", name,
+    strerror(errno));
+   }
+   ralloc_free(name);
+}
+
+/**
+ * Read shader source code from a file.
+ * Useful for debugging to override an app's shader.
+ */
+static GLcharARB *
+read_shader(const gl_shader_stage stage, const char *source)
+{
+   char *read_path;
+   static bool path_exists = true;
+   int len, shader_size = 0;
+   GLcharARB *buffer;
+   FILE *f;
+
+   if (!path_exists)
+  return NULL;
+
+   read_path = getenv("MESA_SHADER_READ_PATH");
+   if (!read_path) {
+  path_exists = false;
+  return NULL;
+   }
+
+   char *name = construct_name(stage, source, read_path);
+   f = fopen(name, "r");
+   ralloc_free(name);
+   if (!f)
+  return NULL;
+
+   /* allocate enough room for the entire shader */
+   fseek(f, 0, SEEK_END);
+   shader_size = ftell(f);
+   rewind(f);
+   assert(shader_size);
+
+   /* add one for terminating zero */
+   shader_size++;
+
+   buffer = malloc(shader_size);
+   assert(buffer);
+
+   len = fread(buffer, 1, shader_size, f);
+   buffer[len] = 0;
+
+   fclose(f);
+
+   return buffer;
+}
+
+#endif /* ENABLE_SHADER_CACHE */
+
   /**
    * Return mask of GLSL_x flags by examining the MESA_GLSL env var.
    */
@@ -1775,119 +1891,7 @@ _mesa_LinkProgram(GLuint programObj)
  link_program_error(ctx, shProg);
   }

-#ifdef ENABLE_SHADER_CACHE
-/**
- * Generate a SHA-1 hash value string for given source string.
- */
-static void
-generate_sha1(const char *source, char sha_str[64])
-{
-   unsigned char sha[20];
-   _mesa_sha1_compute(source, strlen(source), sha);
-   _mesa_sha1_format(sha_str, sha);
-}
-
-/**
- * Construct a full path for shader replacement functionality using
- * following format:
- *
- * /_.glsl
- */
-static char *
-construct_name(const gl_shader_stage stage, const char *source,
-   const char *path)
-{
-   char sha[64];
-   static const char *types[] = {
-  "VS", "TC", "TE", "GS", "FS", "CS",
-   };
-
-   generate_sha1(source, sha);
-   return ralloc_asprintf(NULL, "%s/%s_%s.glsl", path, types[stage], sha);
-}
-
-/**
- * Write given shader source to a file in MESA_SHADER_DUMP_PATH.
- */
-static void
-dump_shader(const gl_shader_stage stage, const char 

Re: [Mesa-dev] [PATCH 2/2] radv: remove the radv_finishme() when compiling shaders

[Bas Nieuwenhuizen]

Reviewed-by: Bas Nieuwenhuizen 

for both.

On Thu, May 17, 2018 at 9:56 AM, Samuel Pitoiset
 wrote:
> Having an entrypoint different than "main" doesn't mean we
> have multiple shaders per module.
>
> Signed-off-by: Samuel Pitoiset 
> ---
>  src/amd/vulkan/radv_shader.c | 4 
>  1 file changed, 4 deletions(-)
>
> diff --git a/src/amd/vulkan/radv_shader.c b/src/amd/vulkan/radv_shader.c
> index 1968758a39..7589d9c88a 100644
> --- a/src/amd/vulkan/radv_shader.c
> +++ b/src/amd/vulkan/radv_shader.c
> @@ -163,10 +163,6 @@ radv_shader_compile_to_nir(struct radv_device *device,
>const VkSpecializationInfo *spec_info,
>const VkPipelineCreateFlags flags)
>  {
> -   if (strcmp(entrypoint_name, "main") != 0) {
> -   radv_finishme("Multiple shaders per module not really 
> supported");
> -   }
> -
> nir_shader *nir;
> nir_function *entry_point;
> if (module->nir) {
> --
> 2.17.0
>
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Re: [Mesa-dev] [PATCH] radv: only pass the global BO list at submit time if enabled

[Bas Nieuwenhuizen]

Reviewed-by: Bas Nieuwenhuizen 

On Thu, May 17, 2018 at 11:36 AM, Samuel Pitoiset
 wrote:
> That way the winsys might use a faster path when the global
> BO list is NULL.
>
> Signed-off-by: Samuel Pitoiset 
> ---
>  src/amd/vulkan/radv_device.c | 8 ++--
>  1 file changed, 6 insertions(+), 2 deletions(-)
>
> diff --git a/src/amd/vulkan/radv_device.c b/src/amd/vulkan/radv_device.c
> index a7f4a5ab7b..9f87e7ef1e 100644
> --- a/src/amd/vulkan/radv_device.c
> +++ b/src/amd/vulkan/radv_device.c
> @@ -2474,6 +2474,8 @@ VkResult radv_QueueSubmit(
>
> for (uint32_t j = 0; j < pSubmits[i].commandBufferCount; j += 
> advance) {
> struct radeon_winsys_cs *initial_preamble = (do_flush 
> && !j) ? initial_flush_preamble_cs : initial_preamble_cs;
> +   const struct radv_winsys_bo_list *bo_list = NULL;
> +
> advance = MIN2(max_cs_submission,
>pSubmits[i].commandBufferCount - j);
>
> @@ -2483,12 +2485,14 @@ VkResult radv_QueueSubmit(
> sem_info.cs_emit_wait = j == 0;
> sem_info.cs_emit_signal = j + advance == 
> pSubmits[i].commandBufferCount;
>
> -   if (unlikely(queue->device->use_global_bo_list))
> +   if (unlikely(queue->device->use_global_bo_list)) {
> 
> pthread_mutex_lock(>device->bo_list.mutex);
> +   bo_list = >device->bo_list.list;
> +   }
>
> ret = queue->device->ws->cs_submit(ctx, 
> queue->queue_idx, cs_array + j,
> advance, 
> initial_preamble, continue_preamble_cs,
> -   _info, 
> >device->bo_list.list,
> +   _info, bo_list,
> can_patch, 
> base_fence);
>
> if (unlikely(queue->device->use_global_bo_list))
> --
> 2.17.0
>
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[Mesa-dev] [PATCH] radv: only pass the global BO list at submit time if enabled

[Samuel Pitoiset]

That way the winsys might use a faster path when the global
BO list is NULL.

Signed-off-by: Samuel Pitoiset 
---
 src/amd/vulkan/radv_device.c | 8 ++--
 1 file changed, 6 insertions(+), 2 deletions(-)

diff --git a/src/amd/vulkan/radv_device.c b/src/amd/vulkan/radv_device.c
index a7f4a5ab7b..9f87e7ef1e 100644
--- a/src/amd/vulkan/radv_device.c
+++ b/src/amd/vulkan/radv_device.c
@@ -2474,6 +2474,8 @@ VkResult radv_QueueSubmit(
 
for (uint32_t j = 0; j < pSubmits[i].commandBufferCount; j += 
advance) {
struct radeon_winsys_cs *initial_preamble = (do_flush 
&& !j) ? initial_flush_preamble_cs : initial_preamble_cs;
+   const struct radv_winsys_bo_list *bo_list = NULL;
+
advance = MIN2(max_cs_submission,
   pSubmits[i].commandBufferCount - j);
 
@@ -2483,12 +2485,14 @@ VkResult radv_QueueSubmit(
sem_info.cs_emit_wait = j == 0;
sem_info.cs_emit_signal = j + advance == 
pSubmits[i].commandBufferCount;
 
-   if (unlikely(queue->device->use_global_bo_list))
+   if (unlikely(queue->device->use_global_bo_list)) {

pthread_mutex_lock(>device->bo_list.mutex);
+   bo_list = >device->bo_list.list;
+   }
 
ret = queue->device->ws->cs_submit(ctx, 
queue->queue_idx, cs_array + j,
advance, 
initial_preamble, continue_preamble_cs,
-   _info, 
>device->bo_list.list,
+   _info, bo_list,
can_patch, base_fence);
 
if (unlikely(queue->device->use_global_bo_list))
-- 
2.17.0

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[Mesa-dev] [PATCH] i965/disasm: Always print message descriptor and SFID for SEND instructions

[Toni Lönnberg]

Having the disassembly always show the message descriptor and SFID makes it
easier to debug what data is actually fed to the external units. Descriptor
format was changed to unsigned so that immediate values as 'src1' will get
printed out in a readable format.
---
 src/intel/compiler/brw_disasm.c | 10 +-
 src/intel/compiler/brw_eu_emit.c|  2 +-
 src/intel/compiler/brw_fs_generator.cpp |  2 +-
 3 files changed, 7 insertions(+), 7 deletions(-)

diff --git a/src/intel/compiler/brw_disasm.c b/src/intel/compiler/brw_disasm.c
index 5f75c67..d50bbc6 100644
--- a/src/intel/compiler/brw_disasm.c
+++ b/src/intel/compiler/brw_disasm.c
@@ -1591,11 +1591,11 @@ brw_disassemble_inst(FILE *file, const struct 
gen_device_info *devinfo,
if (opcode == BRW_OPCODE_SEND || opcode == BRW_OPCODE_SENDC) {
   enum brw_message_target sfid = brw_inst_sfid(devinfo, inst);
 
-  if (brw_inst_src1_reg_file(devinfo, inst) != BRW_IMMEDIATE_VALUE) {
- /* show the indirect descriptor source */
- pad(file, 48);
- err |= src1(file, devinfo, inst);
-  }
+  pad(file, 48);
+  err |= src1(file, devinfo, inst);
+
+  pad(file, 64);
+  format(file, "0x%"PRIx32, sfid);
 
   newline(file);
   pad(file, 16);
diff --git a/src/intel/compiler/brw_eu_emit.c b/src/intel/compiler/brw_eu_emit.c
index ee5a048..d055fb1 100644
--- a/src/intel/compiler/brw_eu_emit.c
+++ b/src/intel/compiler/brw_eu_emit.c
@@ -378,7 +378,7 @@ brw_set_message_descriptor(struct brw_codegen *p,
 {
const struct gen_device_info *devinfo = p->devinfo;
 
-   brw_set_src1(p, inst, brw_imm_d(0));
+   brw_set_src1(p, inst, brw_imm_ud(0));
 
/* For indirect sends, `inst` will not be the SEND/SENDC instruction
 * itself; instead, it will be a MOV/OR into the address register.
diff --git a/src/intel/compiler/brw_fs_generator.cpp 
b/src/intel/compiler/brw_fs_generator.cpp
index 6d5306a..56246dd 100644
--- a/src/intel/compiler/brw_fs_generator.cpp
+++ b/src/intel/compiler/brw_fs_generator.cpp
@@ -688,7 +688,7 @@ fs_generator::generate_urb_write(fs_inst *inst, struct 
brw_reg payload)
 
brw_set_dest(p, insn, brw_null_reg());
brw_set_src0(p, insn, payload);
-   brw_set_src1(p, insn, brw_imm_d(0));
+   brw_set_src1(p, insn, brw_imm_ud(0));
 
brw_inst_set_sfid(p->devinfo, insn, BRW_SFID_URB);
brw_inst_set_urb_opcode(p->devinfo, insn, GEN8_URB_OPCODE_SIMD8_WRITE);
-- 
2.7.4

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Re: [Mesa-dev] [PATCH 2/3] mesa/main/shaderapi: Use sha as part of captured shaders name

[Tapani Pälli]

On 05/17/2018 11:49 AM, Benedikt Schemmer wrote:



Am 17.05.2018 um 09:11 schrieb Tapani Pälli:

some nitpicking below .. I'll do some testing to see that things work as before 
but overall these changes look good to me. Would be nice to hear comments from 
active shader-db users.

On 05/10/2018 12:05 PM, Benedikt Schemmer wrote:

It is inconvenient to capture shaders by program name alone because this does
not allow to capture shaders that get overwritten by shaders with the same
program name (ie games when you change settings or piglit).

---
   src/mesa/main/shaderapi.c | 47 
---
   1 file changed, 32 insertions(+), 15 deletions(-)

diff --git a/src/mesa/main/shaderapi.c b/src/mesa/main/shaderapi.c
index 1d0ca5374b..65cf0a67a2 100644
--- a/src/mesa/main/shaderapi.c
+++ b/src/mesa/main/shaderapi.c
@@ -1343,29 +1343,46 @@ link_program(struct gl_context *ctx, struct 
gl_shader_program *shProg,
  /* Capture .shader_test files. */
  const char *capture_path = _mesa_get_shader_capture_path();
  if (shProg->Name != 0 && shProg->Name != ~0 && capture_path != NULL) {
+


extra space


     FILE *file;
-  char *filename = ralloc_asprintf(NULL, "%s/%u.shader_test",
-   capture_path, shProg->Name);
+  char *filename = NULL;
+  char *fsource = NULL;
+  char *ftemp = NULL;
+
+  asprintf(, "[require]\nGLSL%s >= %u.%02u\n",
+   shProg->IsES ? " ES" : "",
+   shProg->data->Version / 100, shProg->data->Version % 100);
+
+  if (shProg->SeparateShader) {
+ ftemp = fsource;
+ asprintf(, "%sGL_ARB_separate_shader_objects\nSSO ENABLED\n",
+  ftemp);
+ free(ftemp);
+  }
+
+  for (unsigned i = 0; i < shProg->NumShaders; i++) {
+  ftemp = fsource;
+  asprintf(, "%s\n[%s shader]\n%s\n", ftemp,
+   _mesa_shader_stage_to_string(shProg->Shaders[i]->Stage),
+   shProg->Shaders[i]->Source);
+  free(ftemp);
+  }
+
+  char shabuf[64] = {"mylittlebunny"};


please remove the initialization, it is unnecessary


That was left from before I used generate_sha1 which sometimes failed for some 
reason.
I have one little thing though:
Most of the time this is defined as shabuf[41] (20 bytes sha plus trailing \0 )
In this file it is 64 for some reason.
Should I change that?


Yes please, 41 is enough space there.




+  generate_sha1(fsource, shabuf);
+
+  asprintf(, "%s/%s_%u.shader_test", capture_path,
+   shabuf, shProg->Name);
     file = fopen(filename, "w");
     if (file) {
- fprintf(file, "[require]\nGLSL%s >= %u.%02u\n",
- shProg->IsES ? " ES" : "",
- shProg->data->Version / 100, shProg->data->Version % 100);
- if (shProg->SeparateShader)
-    fprintf(file, "GL_ARB_separate_shader_objects\nSSO ENABLED\n");
- fprintf(file, "\n");
-
- for (unsigned i = 0; i < shProg->NumShaders; i++) {
-    fprintf(file, "[%s shader]\n%s\n",
-    _mesa_shader_stage_to_string(shProg->Shaders[i]->Stage),
-    shProg->Shaders[i]->Source);
- }
+ fprintf(file, "%s", fsource);
    fclose(file);
     } else {
    _mesa_warning(ctx, "Failed to open %s", filename);
     }

-  ralloc_free(filename);
+  free(filename);
+  free(fsource);
  }

  if (shProg->data->LinkStatus == LINKING_FAILURE &&


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Re: [Mesa-dev] [PATCH 2/3] mesa/main/shaderapi: Use sha as part of captured shaders name

[Benedikt Schemmer]

Am 17.05.2018 um 09:11 schrieb Tapani Pälli:
> some nitpicking below .. I'll do some testing to see that things work as 
> before but overall these changes look good to me. Would be nice to hear 
> comments from active shader-db users.
> 
> On 05/10/2018 12:05 PM, Benedikt Schemmer wrote:
>> It is inconvenient to capture shaders by program name alone because this does
>> not allow to capture shaders that get overwritten by shaders with the same
>> program name (ie games when you change settings or piglit).
>>
>> ---
>>   src/mesa/main/shaderapi.c | 47 
>> ---
>>   1 file changed, 32 insertions(+), 15 deletions(-)
>>
>> diff --git a/src/mesa/main/shaderapi.c b/src/mesa/main/shaderapi.c
>> index 1d0ca5374b..65cf0a67a2 100644
>> --- a/src/mesa/main/shaderapi.c
>> +++ b/src/mesa/main/shaderapi.c
>> @@ -1343,29 +1343,46 @@ link_program(struct gl_context *ctx, struct 
>> gl_shader_program *shProg,
>>  /* Capture .shader_test files. */
>>  const char *capture_path = _mesa_get_shader_capture_path();
>>  if (shProg->Name != 0 && shProg->Name != ~0 && capture_path != NULL) {
>> +
> 
> extra space
> 
>>     FILE *file;
>> -  char *filename = ralloc_asprintf(NULL, "%s/%u.shader_test",
>> -   capture_path, shProg->Name);
>> +  char *filename = NULL;
>> +  char *fsource = NULL;
>> +  char *ftemp = NULL;
>> +
>> +  asprintf(, "[require]\nGLSL%s >= %u.%02u\n",
>> +   shProg->IsES ? " ES" : "",
>> +   shProg->data->Version / 100, shProg->data->Version % 100);
>> +
>> +  if (shProg->SeparateShader) {
>> + ftemp = fsource;
>> + asprintf(, "%sGL_ARB_separate_shader_objects\nSSO 
>> ENABLED\n",
>> +  ftemp);
>> + free(ftemp);
>> +  }
>> +
>> +  for (unsigned i = 0; i < shProg->NumShaders; i++) {
>> +  ftemp = fsource;
>> +  asprintf(, "%s\n[%s shader]\n%s\n", ftemp,
>> +   _mesa_shader_stage_to_string(shProg->Shaders[i]->Stage),
>> +   shProg->Shaders[i]->Source);
>> +  free(ftemp);
>> +  }
>> +
>> +  char shabuf[64] = {"mylittlebunny"};
> 
> please remove the initialization, it is unnecessary

That was left from before I used generate_sha1 which sometimes failed for some 
reason.
I have one little thing though:
Most of the time this is defined as shabuf[41] (20 bytes sha plus trailing \0 )
In this file it is 64 for some reason.
Should I change that?

> 
>> +  generate_sha1(fsource, shabuf);
>> +
>> +  asprintf(, "%s/%s_%u.shader_test", capture_path,
>> +   shabuf, shProg->Name);
>>     file = fopen(filename, "w");
>>     if (file) {
>> - fprintf(file, "[require]\nGLSL%s >= %u.%02u\n",
>> - shProg->IsES ? " ES" : "",
>> - shProg->data->Version / 100, shProg->data->Version % 100);
>> - if (shProg->SeparateShader)
>> -    fprintf(file, "GL_ARB_separate_shader_objects\nSSO ENABLED\n");
>> - fprintf(file, "\n");
>> -
>> - for (unsigned i = 0; i < shProg->NumShaders; i++) {
>> -    fprintf(file, "[%s shader]\n%s\n",
>> -    _mesa_shader_stage_to_string(shProg->Shaders[i]->Stage),
>> -    shProg->Shaders[i]->Source);
>> - }
>> + fprintf(file, "%s", fsource);
>>    fclose(file);
>>     } else {
>>    _mesa_warning(ctx, "Failed to open %s", filename);
>>     }
>>
>> -  ralloc_free(filename);
>> +  free(filename);
>> +  free(fsource);
>>  }
>>
>>  if (shProg->data->LinkStatus == LINKING_FAILURE &&
>>
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[Mesa-dev] [PATCH 19/22] intel/compiler: lower 16-bit fmod

[Iago Toral Quiroga]

---
 src/intel/compiler/brw_compiler.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/src/intel/compiler/brw_compiler.c 
b/src/intel/compiler/brw_compiler.c
index 6480dbefbf6..36a870ece0d 100644
--- a/src/intel/compiler/brw_compiler.c
+++ b/src/intel/compiler/brw_compiler.c
@@ -33,6 +33,7 @@
.lower_sub = true, \
.lower_fdiv = true,\
.lower_scmp = true,\
+   .lower_fmod16 = true,  \
.lower_fmod32 = true,  \
.lower_fmod64 = false, \
.lower_bitfield_extract = true,\
-- 
2.14.1

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[Mesa-dev] [PATCH 21/22] intel/compiler: lower 16-bit flrp

[Iago Toral Quiroga]

---
 src/intel/compiler/brw_compiler.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/src/intel/compiler/brw_compiler.c 
b/src/intel/compiler/brw_compiler.c
index 36a870ece0d..250e4695ded 100644
--- a/src/intel/compiler/brw_compiler.c
+++ b/src/intel/compiler/brw_compiler.c
@@ -33,6 +33,7 @@
.lower_sub = true, \
.lower_fdiv = true,\
.lower_scmp = true,\
+   .lower_flrp16 = true,  \
.lower_fmod16 = true,  \
.lower_fmod32 = true,  \
.lower_fmod64 = false, \
-- 
2.14.1

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[Mesa-dev] [PATCH 20/22] compiler/nir: add lowering for 16-bit flrp

[Iago Toral Quiroga]

---
 src/compiler/nir/nir.h| 1 +
 src/compiler/nir/nir_opt_algebraic.py | 1 +
 2 files changed, 2 insertions(+)

diff --git a/src/compiler/nir/nir.h b/src/compiler/nir/nir.h
index 59c84bde268..7e4c78cc1b7 100644
--- a/src/compiler/nir/nir.h
+++ b/src/compiler/nir/nir.h
@@ -1871,6 +1871,7 @@ typedef struct nir_shader_compiler_options {
bool lower_fdiv;
bool lower_ffma;
bool fuse_ffma;
+   bool lower_flrp16;
bool lower_flrp32;
/** Lowers flrp when it does not support doubles */
bool lower_flrp64;
diff --git a/src/compiler/nir/nir_opt_algebraic.py 
b/src/compiler/nir/nir_opt_algebraic.py
index 1033a42a06c..75e71efcc6b 100644
--- a/src/compiler/nir/nir_opt_algebraic.py
+++ b/src/compiler/nir/nir_opt_algebraic.py
@@ -113,6 +113,7 @@ optimizations = [
(('~flrp', 0.0, a, b), ('fmul', a, b)),
(('~flrp', a, b, ('b2f', c)), ('bcsel', c, b, a), 'options->lower_flrp32'),
(('~flrp', a, 0.0, c), ('fadd', ('fmul', ('fneg', a), c), a)),
+   (('flrp@16', a, b, c), ('fadd', ('fmul', c, ('fsub', b, a)), a), 
'options->lower_flrp16'),
(('flrp@32', a, b, c), ('fadd', ('fmul', c, ('fsub', b, a)), a), 
'options->lower_flrp32'),
(('flrp@64', a, b, c), ('fadd', ('fmul', c, ('fsub', b, a)), a), 
'options->lower_flrp64'),
(('ffract', a), ('fsub', a, ('ffloor', a)), 'options->lower_ffract'),
-- 
2.14.1

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[Mesa-dev] [PATCH 22/22] intel/compiler: Extended Math is limited to SIMD8 on half-float

[Iago Toral Quiroga]

From the Skylake PRM, Extended Math Function:

  "The execution size must be no more than 8 when half-floats
   are used in source or destination operand."

Earlier generations do not support Extended Math with half-float.
---
 src/intel/compiler/brw_fs.cpp | 30 +++---
 1 file changed, 23 insertions(+), 7 deletions(-)

diff --git a/src/intel/compiler/brw_fs.cpp b/src/intel/compiler/brw_fs.cpp
index b21996c1682..dcba4ee8068 100644
--- a/src/intel/compiler/brw_fs.cpp
+++ b/src/intel/compiler/brw_fs.cpp
@@ -5199,18 +5199,34 @@ get_lowered_simd_width(const struct gen_device_info 
*devinfo,
case SHADER_OPCODE_EXP2:
case SHADER_OPCODE_LOG2:
case SHADER_OPCODE_SIN:
-   case SHADER_OPCODE_COS:
+   case SHADER_OPCODE_COS: {
   /* Unary extended math instructions are limited to SIMD8 on Gen4 and
* Gen6.
*/
-  return (devinfo->gen >= 7 ? MIN2(16, inst->exec_size) :
-  devinfo->gen == 5 || devinfo->is_g4x ? MIN2(16, inst->exec_size) 
:
-  MIN2(8, inst->exec_size));
+  unsigned max_width =
+ (devinfo->gen >= 7 ? MIN2(16, inst->exec_size) :
+  devinfo->gen == 5 || devinfo->is_g4x ? MIN2(16, inst->exec_size) :
+  MIN2(8, inst->exec_size));
 
-   case SHADER_OPCODE_POW:
+  /* Extended Math Function is limited to SIMD8 with half-float */
+  if (inst->dst.type == BRW_REGISTER_TYPE_HF)
+ max_width = MIN2(max_width, 8);
+
+  return max_width;
+   }
+
+   case SHADER_OPCODE_POW: {
   /* SIMD16 is only allowed on Gen7+. */
-  return (devinfo->gen >= 7 ? MIN2(16, inst->exec_size) :
-  MIN2(8, inst->exec_size));
+  unsigned max_width =
+  (devinfo->gen >= 7 ? MIN2(16, inst->exec_size) :
+   MIN2(8, inst->exec_size));
+
+  /* Extended Math Function is limited to SIMD8 with half-float */
+  if (inst->dst.type == BRW_REGISTER_TYPE_HF)
+ max_width = MIN2(max_width, 8);
+
+  return max_width;
+   }
 
case SHADER_OPCODE_INT_QUOTIENT:
case SHADER_OPCODE_INT_REMAINDER:
-- 
2.14.1

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[Mesa-dev] [PATCH 17/22] compiler/spirv: implement 16-bit frexp

[Iago Toral Quiroga]

---
 src/compiler/spirv/vtn_glsl450.c | 48 ++--
 1 file changed, 46 insertions(+), 2 deletions(-)

diff --git a/src/compiler/spirv/vtn_glsl450.c b/src/compiler/spirv/vtn_glsl450.c
index 738f1ea93f1..88d2dcfb0fd 100644
--- a/src/compiler/spirv/vtn_glsl450.c
+++ b/src/compiler/spirv/vtn_glsl450.c
@@ -408,6 +408,45 @@ build_atan2(nir_builder *b, nir_ssa_def *y, nir_ssa_def *x)
 nir_fneg(b, arc), arc);
 }
 
+static nir_ssa_def *
+build_frexp16(nir_builder *b, nir_ssa_def *x, nir_ssa_def **exponent)
+{
+   assert(x->bit_size == 16);
+
+   nir_ssa_def *abs_x = nir_fabs(b, x);
+   nir_ssa_def *zero = nir_imm_floatN_t(b, 0, 16);
+
+   /* Half-precision floating-point values are stored as
+*   1 sign bit;
+*   5 exponent bits;
+*   10 mantissa bits.
+*
+* An exponent shift of 10 will shift the mantissa out, leaving only the
+* exponent and sign bit (which itself may be zero, if the absolute value
+* was taken before the bitcast and shift.
+*/
+   nir_ssa_def *exponent_shift = nir_imm_int(b, 10);
+   nir_ssa_def *exponent_bias = nir_imm_intN_t(b, -14, 16);
+
+   nir_ssa_def *sign_mantissa_mask = nir_imm_intN_t(b, 0x83ffu, 16);
+
+   /* Exponent of floating-point values in the range [0.5, 1.0). */
+   nir_ssa_def *exponent_value = nir_imm_intN_t(b, 0x3c00u, 16);
+
+   nir_ssa_def *is_not_zero = nir_fne(b, abs_x, zero);
+
+   /* Significand return must be of the same type as the input, but the
+* exponent must be a 32-bit integer.
+*/
+   *exponent =
+  nir_i2i32(b,
+nir_iadd(b, nir_ushr(b, abs_x, exponent_shift),
+nir_bcsel(b, is_not_zero, exponent_bias, zero)));
+
+   return nir_ior(b, nir_iand(b, x, sign_mantissa_mask),
+ nir_bcsel(b, is_not_zero, exponent_value, zero));
+}
+
 static nir_ssa_def *
 build_frexp32(nir_builder *b, nir_ssa_def *x, nir_ssa_def **exponent)
 {
@@ -791,8 +830,10 @@ handle_glsl450_alu(struct vtn_builder *b, enum GLSLstd450 
entrypoint,
   nir_ssa_def *exponent;
   if (src[0]->bit_size == 64)
  val->ssa->def = build_frexp64(nb, src[0], );
-  else
+  else if (src[0]->bit_size == 32)
  val->ssa->def = build_frexp32(nb, src[0], );
+  else
+ val->ssa->def = build_frexp16(nb, src[0], );
   nir_store_deref_var(nb, vtn_nir_deref(b, w[6]), exponent, 0xf);
   return;
}
@@ -802,9 +843,12 @@ handle_glsl450_alu(struct vtn_builder *b, enum GLSLstd450 
entrypoint,
   if (src[0]->bit_size == 64)
  val->ssa->elems[0]->def = build_frexp64(nb, src[0],
  >ssa->elems[1]->def);
-  else
+  else if (src[0]->bit_size == 32)
  val->ssa->elems[0]->def = build_frexp32(nb, src[0],
  >ssa->elems[1]->def);
+  else
+ val->ssa->elems[0]->def = build_frexp16(nb, src[0],
+ >ssa->elems[1]->def);
   return;
}
 
-- 
2.14.1

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[Mesa-dev] [PATCH 18/22] compiler/nir: add lowering option for 16-bit fmod

[Iago Toral Quiroga]

---
 src/compiler/nir/nir.h| 1 +
 src/compiler/nir/nir_opt_algebraic.py | 1 +
 2 files changed, 2 insertions(+)

diff --git a/src/compiler/nir/nir.h b/src/compiler/nir/nir.h
index a379928cdcd..59c84bde268 100644
--- a/src/compiler/nir/nir.h
+++ b/src/compiler/nir/nir.h
@@ -1877,6 +1877,7 @@ typedef struct nir_shader_compiler_options {
bool lower_fpow;
bool lower_fsat;
bool lower_fsqrt;
+   bool lower_fmod16;
bool lower_fmod32;
bool lower_fmod64;
bool lower_bitfield_extract;
diff --git a/src/compiler/nir/nir_opt_algebraic.py 
b/src/compiler/nir/nir_opt_algebraic.py
index 96232f0e549..1033a42a06c 100644
--- a/src/compiler/nir/nir_opt_algebraic.py
+++ b/src/compiler/nir/nir_opt_algebraic.py
@@ -481,6 +481,7 @@ optimizations = [
(('bcsel', ('ine', a, -1), ('ifind_msb', a), -1), ('ifind_msb', a)),
 
# Misc. lowering
+   (('fmod@16', a, b), ('fsub', a, ('fmul', b, ('ffloor', ('fdiv', a, b, 
'options->lower_fmod16'),
(('fmod@32', a, b), ('fsub', a, ('fmul', b, ('ffloor', ('fdiv', a, b, 
'options->lower_fmod32'),
(('fmod@64', a, b), ('fsub', a, ('fmul', b, ('ffloor', ('fdiv', a, b, 
'options->lower_fmod64'),
(('frem', a, b), ('fsub', a, ('fmul', b, ('ftrunc', ('fdiv', a, b, 
'options->lower_fmod32'),
-- 
2.14.1

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[Mesa-dev] [PATCH 16/22] compiler/spirv: implement 16-bit hyperbolic trigonometric functions

[Iago Toral Quiroga]

---
 src/compiler/spirv/vtn_glsl450.c | 29 +++--
 1 file changed, 19 insertions(+), 10 deletions(-)

diff --git a/src/compiler/spirv/vtn_glsl450.c b/src/compiler/spirv/vtn_glsl450.c
index 324e8b5874a..738f1ea93f1 100644
--- a/src/compiler/spirv/vtn_glsl450.c
+++ b/src/compiler/spirv/vtn_glsl450.c
@@ -712,7 +712,7 @@ handle_glsl450_alu(struct vtn_builder *b, enum GLSLstd450 
entrypoint,
case GLSLstd450Sinh:
   /* 0.5 * (e^x - e^(-x)) */
   val->ssa->def =
- nir_fmul(nb, nir_imm_float(nb, 0.5f),
+ nir_fmul(nb, nir_imm_floatN_t(nb, 0.5f, src[0]->bit_size),
   nir_fsub(nb, build_exp(nb, src[0]),
build_exp(nb, nir_fneg(nb, src[0];
   return;
@@ -720,7 +720,7 @@ handle_glsl450_alu(struct vtn_builder *b, enum GLSLstd450 
entrypoint,
case GLSLstd450Cosh:
   /* 0.5 * (e^x + e^(-x)) */
   val->ssa->def =
- nir_fmul(nb, nir_imm_float(nb, 0.5f),
+ nir_fmul(nb, nir_imm_floatN_t(nb, 0.5f, src[0]->bit_size),
   nir_fadd(nb, build_exp(nb, src[0]),
build_exp(nb, nir_fneg(nb, src[0];
   return;
@@ -733,11 +733,20 @@ handle_glsl450_alu(struct vtn_builder *b, enum GLSLstd450 
entrypoint,
* We clamp x to (-inf, +10] to avoid precision problems.  When x > 10,
* e^2x is so much larger than 1.0 that 1.0 gets flushed to zero in the
* computation e^2x +/- 1 so it can be ignored.
+   *
+   * For 16-bit precision we clamp x to (-inf, +4.2] since the maximum
+   * representable number is only 65,504 and e^(2*6) exceeds that. Also,
+   * if x > 4.2, tanh(x) will return 1.0 in fp16.
*/
-  nir_ssa_def *x = nir_fmin(nb, src[0], nir_imm_float(nb, 10));
-  nir_ssa_def *exp2x = build_exp(nb, nir_fmul(nb, x, nir_imm_float(nb, 
2)));
-  val->ssa->def = nir_fdiv(nb, nir_fsub(nb, exp2x, nir_imm_float(nb, 1)),
-   nir_fadd(nb, exp2x, nir_imm_float(nb, 1)));
+  const uint32_t bit_size = src[0]->bit_size;
+  const double clamped_x = bit_size > 16 ? 10.0 : 4.2;
+  nir_ssa_def *x = nir_fmin(nb, src[0],
+nir_imm_floatN_t(nb, clamped_x, bit_size));
+  nir_ssa_def *one = nir_imm_floatN_t(nb, 1.0, bit_size);
+  nir_ssa_def *two = nir_imm_floatN_t(nb, 2.0, bit_size);
+  nir_ssa_def *exp2x = build_exp(nb, nir_fmul(nb, x, two));
+  val->ssa->def = nir_fdiv(nb, nir_fsub(nb, exp2x, one),
+   nir_fadd(nb, exp2x, one));
   return;
}
 
@@ -745,16 +754,16 @@ handle_glsl450_alu(struct vtn_builder *b, enum GLSLstd450 
entrypoint,
   val->ssa->def = nir_fmul(nb, nir_fsign(nb, src[0]),
  build_log(nb, nir_fadd(nb, nir_fabs(nb, src[0]),
nir_fsqrt(nb, nir_fadd(nb, nir_fmul(nb, src[0], src[0]),
-  nir_imm_float(nb, 1.0f));
+  nir_imm_floatN_t(nb, 1.0f, 
src[0]->bit_size));
   return;
case GLSLstd450Acosh:
   val->ssa->def = build_log(nb, nir_fadd(nb, src[0],
  nir_fsqrt(nb, nir_fsub(nb, nir_fmul(nb, src[0], src[0]),
-nir_imm_float(nb, 1.0f);
+nir_imm_floatN_t(nb, 1.0f, 
src[0]->bit_size);
   return;
case GLSLstd450Atanh: {
-  nir_ssa_def *one = nir_imm_float(nb, 1.0);
-  val->ssa->def = nir_fmul(nb, nir_imm_float(nb, 0.5f),
+  nir_ssa_def *one = nir_imm_floatN_t(nb, 1.0, src[0]->bit_size);
+  val->ssa->def = nir_fmul(nb, nir_imm_floatN_t(nb, 0.5f, 
src[0]->bit_size),
  build_log(nb, nir_fdiv(nb, nir_fadd(nb, one, src[0]),
 nir_fsub(nb, one, src[0];
   return;
-- 
2.14.1

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[Mesa-dev] [PATCH 14/22] compiler/spirv: implement 16-bit atan2

[Iago Toral Quiroga]

---
 src/compiler/spirv/vtn_glsl450.c | 22 +++---
 1 file changed, 15 insertions(+), 7 deletions(-)

diff --git a/src/compiler/spirv/vtn_glsl450.c b/src/compiler/spirv/vtn_glsl450.c
index 9e565ef9e5a..70e3eb80c4c 100644
--- a/src/compiler/spirv/vtn_glsl450.c
+++ b/src/compiler/spirv/vtn_glsl450.c
@@ -322,8 +322,11 @@ build_atan(nir_builder *b, nir_ssa_def *y_over_x)
 static nir_ssa_def *
 build_atan2(nir_builder *b, nir_ssa_def *y, nir_ssa_def *x)
 {
-   nir_ssa_def *zero = nir_imm_float(b, 0);
-   nir_ssa_def *one = nir_imm_float(b, 1);
+   assert(y->bit_size == x->bit_size);
+   const uint32_t bit_size = x->bit_size;
+
+   nir_ssa_def *zero = nir_imm_floatN_t(b, 0, bit_size);
+   nir_ssa_def *one = nir_imm_floatN_t(b, 1, bit_size);
 
/* If we're on the left half-plane rotate the coordinates π/2 clock-wise
 * for the y=0 discontinuity to end up aligned with the vertical
@@ -353,9 +356,10 @@ build_atan2(nir_builder *b, nir_ssa_def *y, nir_ssa_def *x)
 * floating point representations with at least the dynamic range of ATI's
 * 24-bit representation.
 */
-   nir_ssa_def *huge = nir_imm_float(b, 1e18f);
+   const double huge_val = bit_size >= 32 ? 1e18 : 1e14;
+   nir_ssa_def *huge = nir_imm_floatN_t(b,  huge_val, bit_size);
nir_ssa_def *scale = nir_bcsel(b, nir_fge(b, nir_fabs(b, t), huge),
-  nir_imm_float(b, 0.25), one);
+  nir_imm_floatN_t(b, 0.25, bit_size), one);
nir_ssa_def *rcp_scaled_t = nir_frcp(b, nir_fmul(b, t, scale));
nir_ssa_def *s_over_t = nir_fmul(b, nir_fmul(b, s, scale), rcp_scaled_t);
 
@@ -382,9 +386,13 @@ build_atan2(nir_builder *b, nir_ssa_def *y, nir_ssa_def *x)
/* Calculate the arctangent and fix up the result if we had flipped the
 * coordinate system.
 */
-   nir_ssa_def *arc = nir_fadd(b, nir_fmul(b, nir_b2f(b, flip),
-   nir_imm_float(b, M_PI_2f)),
-   build_atan(b, tan));
+   nir_ssa_def *b2f_flip = nir_b2f(b, flip);
+   if (bit_size == 16)
+  b2f_flip = nir_f2f16_undef(b, b2f_flip);
+   nir_ssa_def *arc =
+  nir_fadd(b, nir_fmul(b, b2f_flip,
+  nir_imm_floatN_t(b, M_PI_2f, bit_size)),
+  build_atan(b, tan));
 
/* Rather convoluted calculation of the sign of the result.  When x < 0 we
 * cannot use fsign because we need to be able to distinguish between
-- 
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[Mesa-dev] [PATCH 13/22] compiler/spirv: implement 16-bit atan

[Iago Toral Quiroga]

---
 src/compiler/spirv/vtn_glsl450.c | 37 +
 1 file changed, 25 insertions(+), 12 deletions(-)

diff --git a/src/compiler/spirv/vtn_glsl450.c b/src/compiler/spirv/vtn_glsl450.c
index 8cbdaad3998..9e565ef9e5a 100644
--- a/src/compiler/spirv/vtn_glsl450.c
+++ b/src/compiler/spirv/vtn_glsl450.c
@@ -255,8 +255,10 @@ build_fsum(nir_builder *b, nir_ssa_def **xs, int terms)
 static nir_ssa_def *
 build_atan(nir_builder *b, nir_ssa_def *y_over_x)
 {
+   const uint32_t bit_size = y_over_x->bit_size;
+
nir_ssa_def *abs_y_over_x = nir_fabs(b, y_over_x);
-   nir_ssa_def *one = nir_imm_float(b, 1.0f);
+   nir_ssa_def *one = nir_imm_floatN_t(b, 1.0f, bit_size);
 
/*
 * range-reduction, first step:
@@ -282,25 +284,36 @@ build_atan(nir_builder *b, nir_ssa_def *y_over_x)
nir_ssa_def *x_9  = nir_fmul(b, x_7, x_2);
nir_ssa_def *x_11 = nir_fmul(b, x_9, x_2);
 
+   const float coef[] = {
+   0.793128310355f,
+  -0.3326756418091246f,
+   0.1938924977115610f,
+  -0.1173503194786851f,
+   0.0536813784310406f,
+  -0.0121323213173444f,
+   };
+
nir_ssa_def *polynomial_terms[] = {
-  nir_fmul(b, x,nir_imm_float(b,  0.793128310355f)),
-  nir_fmul(b, x_3,  nir_imm_float(b, -0.3326756418091246f)),
-  nir_fmul(b, x_5,  nir_imm_float(b,  0.1938924977115610f)),
-  nir_fmul(b, x_7,  nir_imm_float(b, -0.1173503194786851f)),
-  nir_fmul(b, x_9,  nir_imm_float(b,  0.0536813784310406f)),
-  nir_fmul(b, x_11, nir_imm_float(b, -0.0121323213173444f)),
+  nir_fmul(b, x,nir_imm_floatN_t(b, coef[0], bit_size)),
+  nir_fmul(b, x_3,  nir_imm_floatN_t(b, coef[1], bit_size)),
+  nir_fmul(b, x_5,  nir_imm_floatN_t(b, coef[2], bit_size)),
+  nir_fmul(b, x_7,  nir_imm_floatN_t(b, coef[3], bit_size)),
+  nir_fmul(b, x_9,  nir_imm_floatN_t(b, coef[4], bit_size)),
+  nir_fmul(b, x_11, nir_imm_floatN_t(b, coef[5], bit_size)),
};
 
nir_ssa_def *tmp =
   build_fsum(b, polynomial_terms, ARRAY_SIZE(polynomial_terms));
 
/* range-reduction fixup */
+   nir_ssa_def *minus_2 = nir_imm_floatN_t(b, -2.0f, bit_size);
+   nir_ssa_def *m_pi_2 = nir_imm_floatN_t(b, M_PI_2f, bit_size);
+   nir_ssa_def *b2f = nir_b2f(b, nir_flt(b, one, abs_y_over_x));
+   if (bit_size == 16)
+  b2f = nir_f2f16_undef(b, b2f);
tmp = nir_fadd(b, tmp,
-  nir_fmul(b,
-   nir_b2f(b, nir_flt(b, one, abs_y_over_x)),
-   nir_fadd(b, nir_fmul(b, tmp,
-nir_imm_float(b, -2.0f)),
-   nir_imm_float(b, M_PI_2f;
+  nir_fmul(b, b2f,
+  nir_fadd(b, nir_fmul(b, tmp, minus_2), m_pi_2)));
 
/* sign fixup */
return nir_fmul(b, tmp, nir_fsign(b, y_over_x));
-- 
2.14.1

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[Mesa-dev] [PATCH 15/22] compiler/spirv: implement 16-bit exp and log

[Iago Toral Quiroga]

---
 src/compiler/spirv/vtn_glsl450.c | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/src/compiler/spirv/vtn_glsl450.c b/src/compiler/spirv/vtn_glsl450.c
index 70e3eb80c4c..324e8b5874a 100644
--- a/src/compiler/spirv/vtn_glsl450.c
+++ b/src/compiler/spirv/vtn_glsl450.c
@@ -194,7 +194,7 @@ build_fclamp(nir_builder *b,
 static nir_ssa_def *
 build_exp(nir_builder *b, nir_ssa_def *x)
 {
-   return nir_fexp2(b, nir_fmul(b, x, nir_imm_float(b, M_LOG2E)));
+   return nir_fexp2(b, nir_fmul(b, x, nir_imm_floatN_t(b, M_LOG2E, 
x->bit_size)));
 }
 
 /**
@@ -203,7 +203,8 @@ build_exp(nir_builder *b, nir_ssa_def *x)
 static nir_ssa_def *
 build_log(nir_builder *b, nir_ssa_def *x)
 {
-   return nir_fmul(b, nir_flog2(b, x), nir_imm_float(b, 1.0 / M_LOG2E));
+   return nir_fmul(b, nir_flog2(b, x),
+  nir_imm_floatN_t(b, 1.0 / M_LOG2E, x->bit_size));
 }
 
 /**
-- 
2.14.1

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[Mesa-dev] [PATCH 12/22] compiler/spirv: implement 16-bit acos

[Iago Toral Quiroga]

---
 src/compiler/spirv/vtn_glsl450.c | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/src/compiler/spirv/vtn_glsl450.c b/src/compiler/spirv/vtn_glsl450.c
index 845e5a9e517..8cbdaad3998 100644
--- a/src/compiler/spirv/vtn_glsl450.c
+++ b/src/compiler/spirv/vtn_glsl450.c
@@ -743,8 +743,9 @@ handle_glsl450_alu(struct vtn_builder *b, enum GLSLstd450 
entrypoint,
   return;
 
case GLSLstd450Acos:
-  val->ssa->def = nir_fsub(nb, nir_imm_float(nb, M_PI_2f),
-   build_asin(nb, src[0], 0.08132463, 
-0.02363318));
+  val->ssa->def =
+ nir_fsub(nb, nir_imm_floatN_t(nb, M_PI_2f, src[0]->bit_size),
+  build_asin(nb, src[0], 0.08132463, -0.02363318));
   return;
 
case GLSLstd450Atan:
-- 
2.14.1

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[Mesa-dev] [PATCH 10/22] intel/compiler: allow extended math functions with HF operands

[Iago Toral Quiroga]

The PRM states that half-float operands are supported since gen9.
---
 src/intel/compiler/brw_eu_emit.c | 6 --
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/src/intel/compiler/brw_eu_emit.c b/src/intel/compiler/brw_eu_emit.c
index ee5a048bcaa..20c3f9fa933 100644
--- a/src/intel/compiler/brw_eu_emit.c
+++ b/src/intel/compiler/brw_eu_emit.c
@@ -1933,8 +1933,10 @@ void gen6_math(struct brw_codegen *p,
   assert(src1.file == BRW_GENERAL_REGISTER_FILE ||
  (devinfo->gen >= 8 && src1.file == BRW_IMMEDIATE_VALUE));
} else {
-  assert(src0.type == BRW_REGISTER_TYPE_F);
-  assert(src1.type == BRW_REGISTER_TYPE_F);
+  assert(src0.type == BRW_REGISTER_TYPE_F ||
+ (src0.type == BRW_REGISTER_TYPE_HF && devinfo->gen >= 9));
+  assert(src1.type == BRW_REGISTER_TYPE_F ||
+ (src1.type == BRW_REGISTER_TYPE_HF && devinfo->gen >= 9));
}
 
/* Source modifiers are ignored for extended math instructions on Gen6. */
-- 
2.14.1

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[Mesa-dev] [PATCH 11/22] compiler/spirv: implement 16-bit asin

[Iago Toral Quiroga]

---
 src/compiler/spirv/vtn_glsl450.c | 20 +---
 1 file changed, 13 insertions(+), 7 deletions(-)

diff --git a/src/compiler/spirv/vtn_glsl450.c b/src/compiler/spirv/vtn_glsl450.c
index ffe12a71818..845e5a9e517 100644
--- a/src/compiler/spirv/vtn_glsl450.c
+++ b/src/compiler/spirv/vtn_glsl450.c
@@ -217,19 +217,25 @@ build_log(nir_builder *b, nir_ssa_def *x)
  * in each case.
  */
 static nir_ssa_def *
-build_asin(nir_builder *b, nir_ssa_def *x, float p0, float p1)
+build_asin(nir_builder *b, nir_ssa_def *x, float _p0, float _p1)
 {
+   nir_ssa_def *p0 = nir_imm_floatN_t(b, _p0, x->bit_size);
+   nir_ssa_def *p1 = nir_imm_floatN_t(b, _p1, x->bit_size);
+   nir_ssa_def *one = nir_imm_floatN_t(b, 1.0f, x->bit_size);
+   nir_ssa_def *m_pi_2 = nir_imm_floatN_t(b, M_PI_2f, x->bit_size);
+   nir_ssa_def *m_pi_4_minus_one =
+  nir_imm_floatN_t(b, M_PI_4f - 1.0f, x->bit_size);
nir_ssa_def *abs_x = nir_fabs(b, x);
return nir_fmul(b, nir_fsign(b, x),
-   nir_fsub(b, nir_imm_float(b, M_PI_2f),
-nir_fmul(b, nir_fsqrt(b, nir_fsub(b, 
nir_imm_float(b, 1.0f), abs_x)),
- nir_fadd(b, nir_imm_float(b, M_PI_2f),
+   nir_fsub(b, m_pi_2,
+nir_fmul(b, nir_fsqrt(b, nir_fsub(b, one, abs_x)),
+ nir_fadd(b, m_pi_2,
   nir_fmul(b, abs_x,
-   nir_fadd(b, 
nir_imm_float(b, M_PI_4f - 1.0f),
+   nir_fadd(b, 
m_pi_4_minus_one,
 nir_fmul(b, 
abs_x,
- 
nir_fadd(b, nir_imm_float(b, p0),
+ 
nir_fadd(b, p0,

   nir_fmul(b, abs_x,
-   
nir_imm_float(b, p1));
+   
p1);
 }
 
 /**
-- 
2.14.1

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[Mesa-dev] [PATCH 09/22] intel/compiler: implement 16-bit multiply-add

[Iago Toral Quiroga]

The PRM for MAD states that F, DF and HF are supported, however, then
it requires that the instruction includes a 2-bit mask specifying
the types of each operand like this:

00: 32-bit float
01: 32-bit signed integer
10: 32-bit unsigned integer
11: 64-bit float

So 16-bit float would not be supported. The driver also asserts that
the types involved in ALING16 3-src operations are one of these
(MAD is always emitted as an align16 instruction prior to gen10).
---
 src/intel/compiler/brw_fs_nir.cpp | 9 -
 1 file changed, 8 insertions(+), 1 deletion(-)

diff --git a/src/intel/compiler/brw_fs_nir.cpp 
b/src/intel/compiler/brw_fs_nir.cpp
index 91283ab4911..58ddc456bae 100644
--- a/src/intel/compiler/brw_fs_nir.cpp
+++ b/src/intel/compiler/brw_fs_nir.cpp
@@ -1525,7 +1525,14 @@ fs_visitor::nir_emit_alu(const fs_builder , 
nir_alu_instr *instr)
   break;
 
case nir_op_ffma:
-  inst = bld.MAD(result, op[2], op[1], op[0]);
+  /* 3-src MAD doesn't support 16-bit operands */
+  if (nir_dest_bit_size(instr->dest.dest) >= 32) {
+ inst = bld.MAD(result, op[2], op[1], op[0]);
+  } else {
+ fs_reg tmp = bld.vgrf(BRW_REGISTER_TYPE_HF);
+ bld.MUL(tmp, op[1], op[0]);
+ inst = bld.ADD(result, tmp, op[2]);
+  }
   inst->saturate = instr->dest.saturate;
   break;
 
-- 
2.14.1

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[Mesa-dev] [PATCH 08/22] intel/compiler: implement 16-bit fsign

[Iago Toral Quiroga]

---
 src/intel/compiler/brw_fs_nir.cpp | 27 +--
 1 file changed, 21 insertions(+), 6 deletions(-)

diff --git a/src/intel/compiler/brw_fs_nir.cpp 
b/src/intel/compiler/brw_fs_nir.cpp
index fb5ad7a614a..91283ab4911 100644
--- a/src/intel/compiler/brw_fs_nir.cpp
+++ b/src/intel/compiler/brw_fs_nir.cpp
@@ -868,14 +868,29 @@ fs_visitor::nir_emit_alu(const fs_builder , 
nir_alu_instr *instr)
   * Predicated OR ORs 1.0 (0x3f80) with the sign bit if val is not
   * zero.
   */
- bld.CMP(bld.null_reg_f(), op[0], brw_imm_f(0.0f), BRW_CONDITIONAL_NZ);
+ fs_reg zero, one_mask, sign_mask;
+ brw_reg_type reg_type;
+ if (type_sz(op[0].type) == 4) {
+zero = brw_imm_f(0.0f);
+one_mask = brw_imm_ud(0x3f80);
+sign_mask = brw_imm_ud(0x8000);
+reg_type = BRW_REGISTER_TYPE_UD;
+ } else {
+assert(type_sz(op[0].type) == 2);
+zero = retype(brw_imm_uw(0), BRW_REGISTER_TYPE_HF);
+one_mask = brw_imm_uw(0x3c00);
+sign_mask = brw_imm_uw(0x8000);
+reg_type = BRW_REGISTER_TYPE_UW;
+ }
+
+ bld.CMP(bld.null_reg_f(), op[0], zero, BRW_CONDITIONAL_NZ);
 
- fs_reg result_int = retype(result, BRW_REGISTER_TYPE_UD);
- op[0].type = BRW_REGISTER_TYPE_UD;
- result.type = BRW_REGISTER_TYPE_UD;
- bld.AND(result_int, op[0], brw_imm_ud(0x8000u));
+ fs_reg result_int = retype(result, reg_type);
+ op[0].type = reg_type;
+ result.type = reg_type;
+ bld.AND(result_int, op[0], sign_mask);
 
- inst = bld.OR(result_int, result_int, brw_imm_ud(0x3f80u));
+ inst = bld.OR(result_int, result_int, one_mask);
  inst->predicate = BRW_PREDICATE_NORMAL;
  if (instr->dest.saturate) {
 inst = bld.MOV(result, result);
-- 
2.14.1

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[Mesa-dev] [PATCH 06/22] compiler/nir: support 16-bit float in nir_imm_floatN_t

[Iago Toral Quiroga]

---
 src/compiler/nir/nir_builder.h | 29 -
 1 file changed, 16 insertions(+), 13 deletions(-)

diff --git a/src/compiler/nir/nir_builder.h b/src/compiler/nir/nir_builder.h
index 02a9dbfb040..198c42dd823 100644
--- a/src/compiler/nir/nir_builder.h
+++ b/src/compiler/nir/nir_builder.h
@@ -25,6 +25,7 @@
 #define NIR_BUILDER_H
 
 #include "nir_control_flow.h"
+#include "util/half_float.h"
 
 struct exec_list;
 
@@ -227,19 +228,6 @@ nir_imm_double(nir_builder *build, double x)
return nir_build_imm(build, 1, 64, v);
 }
 
-static inline nir_ssa_def *
-nir_imm_floatN_t(nir_builder *build, double x, unsigned bit_size)
-{
-   switch (bit_size) {
-   case 32:
-  return nir_imm_float(build, x);
-   case 64:
-  return nir_imm_double(build, x);
-   }
-
-   unreachable("unknown float immediate bit size");
-}
-
 static inline nir_ssa_def *
 nir_imm_vec4(nir_builder *build, float x, float y, float z, float w)
 {
@@ -288,6 +276,21 @@ nir_imm_intN_t(nir_builder *build, uint64_t x, unsigned 
bit_size)
return nir_build_imm(build, 1, bit_size, v);
 }
 
+static inline nir_ssa_def *
+nir_imm_floatN_t(nir_builder *build, double x, unsigned bit_size)
+{
+   switch (bit_size) {
+   case 16:
+  return nir_imm_intN_t(build, _mesa_float_to_half((float)x), 16);
+   case 32:
+  return nir_imm_float(build, x);
+   case 64:
+  return nir_imm_double(build, x);
+   }
+
+   unreachable("unknown float immediate bit size");
+}
+
 static inline nir_ssa_def *
 nir_imm_ivec4(nir_builder *build, int x, int y, int z, int w)
 {
-- 
2.14.1

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[Mesa-dev] [PATCH 07/22] compiler/spirv: handle 16-bit float in radians() and degrees()

[Iago Toral Quiroga]

---
 src/compiler/spirv/vtn_glsl450.c | 10 --
 1 file changed, 8 insertions(+), 2 deletions(-)

diff --git a/src/compiler/spirv/vtn_glsl450.c b/src/compiler/spirv/vtn_glsl450.c
index 6fa759b1bba..ffe12a71818 100644
--- a/src/compiler/spirv/vtn_glsl450.c
+++ b/src/compiler/spirv/vtn_glsl450.c
@@ -540,11 +540,17 @@ handle_glsl450_alu(struct vtn_builder *b, enum GLSLstd450 
entrypoint,
 
switch (entrypoint) {
case GLSLstd450Radians:
-  val->ssa->def = nir_fmul(nb, src[0], nir_imm_float(nb, 0.01745329251));
+  val->ssa->def = nir_fmul(nb, src[0],
+   nir_imm_floatN_t(nb, 0.01745329251,
+src[0]->bit_size));
   return;
+
case GLSLstd450Degrees:
-  val->ssa->def = nir_fmul(nb, src[0], nir_imm_float(nb, 57.2957795131));
+  val->ssa->def = nir_fmul(nb, src[0],
+   nir_imm_floatN_t(nb, 57.2957795131,
+src[0]->bit_size));
   return;
+
case GLSLstd450Tan:
   val->ssa->def = nir_fdiv(nb, nir_fsin(nb, src[0]),
nir_fcos(nb, src[0]));
-- 
2.14.1

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[Mesa-dev] [PATCH 04/22] intel/compiler: lower some 16-bit float operations to 32-bit

[Iago Toral Quiroga]

The hardware doesn't support half-float for these.
---
 src/intel/compiler/brw_nir.c | 5 +
 1 file changed, 5 insertions(+)

diff --git a/src/intel/compiler/brw_nir.c b/src/intel/compiler/brw_nir.c
index dfeea73b06a..ff245b59b81 100644
--- a/src/intel/compiler/brw_nir.c
+++ b/src/intel/compiler/brw_nir.c
@@ -605,6 +605,11 @@ lower_bit_size_callback(const nir_alu_instr *alu, void 
*data)
case nir_op_irem:
case nir_op_udiv:
case nir_op_umod:
+   case nir_op_fceil:
+   case nir_op_ffloor:
+   case nir_op_ffract:
+   case nir_op_fround_even:
+   case nir_op_ftrunc:
   return 32;
default:
   return 0;
-- 
2.14.1

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[Mesa-dev] [PATCH 03/22] compiler/spirv: fix SpvOpIsInf for 16-bit float

[Iago Toral Quiroga]

---
 src/compiler/spirv/vtn_alu.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/src/compiler/spirv/vtn_alu.c b/src/compiler/spirv/vtn_alu.c
index 5f9cc97fdfb..62a5149797a 100644
--- a/src/compiler/spirv/vtn_alu.c
+++ b/src/compiler/spirv/vtn_alu.c
@@ -578,7 +578,9 @@ vtn_handle_alu(struct vtn_builder *b, SpvOp opcode,
   break;
 
case SpvOpIsInf: {
-  nir_ssa_def *inf = nir_imm_floatN_t(>nb, INFINITY, src[0]->bit_size);
+  nir_ssa_def *inf = src[0]->bit_size > 16 ?
+ nir_imm_floatN_t(>nb, INFINITY, src[0]->bit_size) :
+ nir_imm_intN_t(>nb, 0x7c00, 16);
   val->ssa->def = nir_ieq(>nb, nir_fabs(>nb, src[0]), inf);
   break;
}
-- 
2.14.1

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[Mesa-dev] [PATCH 05/22] intel/compiler: lower 16-bit extended math to 32-bit prior to gen9

[Iago Toral Quiroga]

Extended math desn't support half-float on these generations.
---
 src/intel/compiler/brw_nir.c | 13 -
 1 file changed, 12 insertions(+), 1 deletion(-)

diff --git a/src/intel/compiler/brw_nir.c b/src/intel/compiler/brw_nir.c
index ff245b59b81..8337da57585 100644
--- a/src/intel/compiler/brw_nir.c
+++ b/src/intel/compiler/brw_nir.c
@@ -599,6 +599,8 @@ lower_bit_size_callback(const nir_alu_instr *alu, void 
*data)
if (alu->dest.dest.ssa.bit_size != 16)
   return 0;
 
+   const struct brw_compiler *compiler = (const struct brw_compiler *) data;
+
switch (alu->op) {
case nir_op_idiv:
case nir_op_imod:
@@ -611,6 +613,15 @@ lower_bit_size_callback(const nir_alu_instr *alu, void 
*data)
case nir_op_fround_even:
case nir_op_ftrunc:
   return 32;
+   case nir_op_frcp:
+   case nir_op_frsq:
+   case nir_op_fsqrt:
+   case nir_op_fpow:
+   case nir_op_fexp2:
+   case nir_op_flog2:
+   case nir_op_fsin:
+   case nir_op_fcos:
+  return compiler->devinfo->gen < 9 ? 32 : 0;
default:
   return 0;
}
@@ -669,7 +680,7 @@ brw_preprocess_nir(const struct brw_compiler *compiler, 
nir_shader *nir)
 
nir = brw_nir_optimize(nir, compiler, is_scalar);
 
-   nir_lower_bit_size(nir, lower_bit_size_callback, NULL);
+   nir_lower_bit_size(nir, lower_bit_size_callback, (void *)compiler);
 
if (is_scalar) {
   OPT(nir_lower_load_const_to_scalar);
-- 
2.14.1

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[Mesa-dev] [PATCH 02/22] i965/fs: Implement float64 to float16 conversion

[Iago Toral Quiroga]

From: Samuel Iglesias Gonsálvez 

It is not supported directly in the HW, we need to convert to float32
first as intermediate step.

Signed-off-by: Samuel Iglesias Gonsálvez 
---
 src/intel/compiler/brw_fs_nir.cpp | 17 +
 1 file changed, 17 insertions(+)

diff --git a/src/intel/compiler/brw_fs_nir.cpp 
b/src/intel/compiler/brw_fs_nir.cpp
index dd8e5191f4e..fb5ad7a614a 100644
--- a/src/intel/compiler/brw_fs_nir.cpp
+++ b/src/intel/compiler/brw_fs_nir.cpp
@@ -755,6 +755,23 @@ fs_visitor::nir_emit_alu(const fs_builder , 
nir_alu_instr *instr)
*/
 
case nir_op_f2f16_undef:
+  /* BDW PRM, vol02, Command Reference Instructions, mov - MOVE:
+   *
+   *   "There is no direct conversion from HF to DF or DF to HF.
+   *Use two instructions and F (Float) as an intermediate type.
+   *
+   *There is no direct conversion from HF to Q/UQ or Q/UQ to HF.
+   *Use two instructions and F (Float) or a word integer type
+   *or a DWord integer type as an intermediate type."
+   */
+  if (nir_src_bit_size(instr->src[0].src) == 64) {
+ fs_reg tmp = bld.vgrf(BRW_REGISTER_TYPE_F, 1);
+ inst = bld.MOV(tmp, op[0]);
+ inst->saturate = instr->dest.saturate;
+ inst = bld.MOV(result, tmp);
+ inst->saturate = instr->dest.saturate;
+ break;
+  }
   inst = bld.MOV(result, op[0]);
   inst->saturate = instr->dest.saturate;
   break;
-- 
2.14.1

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[Mesa-dev] [PATCH 01/22] i965/fs: implement conversions from float16 to 64 bits data types

[Iago Toral Quiroga]

From: Samuel Iglesias Gonsálvez 

Signed-off-by: Samuel Iglesias Gonsálvez 
---
 src/intel/compiler/brw_fs_nir.cpp | 32 
 1 file changed, 32 insertions(+)

diff --git a/src/intel/compiler/brw_fs_nir.cpp 
b/src/intel/compiler/brw_fs_nir.cpp
index 1ce89520bf1..dd8e5191f4e 100644
--- a/src/intel/compiler/brw_fs_nir.cpp
+++ b/src/intel/compiler/brw_fs_nir.cpp
@@ -762,6 +762,38 @@ fs_visitor::nir_emit_alu(const fs_builder , 
nir_alu_instr *instr)
case nir_op_f2f64:
case nir_op_f2i64:
case nir_op_f2u64:
+  /* BDW PRM, vol02, Command Reference Instructions, mov - MOVE:
+   *
+   *   "There is no direct conversion from HF to DF or DF to HF.
+   *Use two instructions and F (Float) as an intermediate type.
+   *
+   *There is no direct conversion from HF to Q/UQ or Q/UQ to HF.
+   *Use two instructions and F (Float) or a word integer type
+   *or a DWord integer type as an intermediate type."
+   */
+  if (nir_src_bit_size(instr->src[0].src) == 16) {
+ brw_reg_type type;
+ switch (instr->op) {
+ case nir_op_f2f64:
+type = BRW_REGISTER_TYPE_F;
+break;
+ case nir_op_f2i64:
+type = BRW_REGISTER_TYPE_D;
+break;
+ case nir_op_f2u64:
+type = BRW_REGISTER_TYPE_UD;
+break;
+ default:
+unreachable("Not supported");
+ }
+ fs_reg tmp = bld.vgrf(type, 1);
+ inst = bld.MOV(tmp, op[0]);
+ inst->saturate = instr->dest.saturate;
+ inst = bld.MOV(result, tmp);
+ inst->saturate = instr->dest.saturate;
+ break;
+  }
+  /* fallthrough */
case nir_op_i2f64:
case nir_op_i2i64:
case nir_op_u2f64:
-- 
2.14.1

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Re: [Mesa-dev] [PATCH 6/9] intel/blorp: Make blorp_ccs_ambiguate just an internal helper

[Iago Toral]

On Wed, 2018-05-16 at 08:44 -0700, Jason Ekstrand wrote:
> On Wed, May 16, 2018 at 4:00 AM, Iago Toral 
> wrote:
> > On Tue, 2018-05-15 at 15:28 -0700, Jason Ekstrand wrote:
> > 
> > > Now that anv uses blorp_ccs_op for everything, we no longer need
> > to
> > 
> > > expose the ccs_ambiguate function directly.  It's much better
> > tucked
> > 
> > > away as an implementation detail.
> > 
> > > ---
> > 
> > >  src/intel/blorp/blorp.h   |  5 -
> > 
> > >  src/intel/blorp/blorp_clear.c | 21 ++---
> > 
> > >  2 files changed, 10 insertions(+), 16 deletions(-)
> > 
> > > 
> > 
> > > diff --git a/src/intel/blorp/blorp.h b/src/intel/blorp/blorp.h
> > 
> > > index 8c775bf..e27ea7e 100644
> > 
> > > --- a/src/intel/blorp/blorp.h
> > 
> > > +++ b/src/intel/blorp/blorp.h
> > 
> > > @@ -208,11 +208,6 @@ blorp_ccs_op(struct blorp_batch *batch,
> > 
> > >   enum isl_aux_op ccs_op);
> > 
> > >  
> > 
> > >  void
> > 
> > > -blorp_ccs_ambiguate(struct blorp_batch *batch,
> > 
> > > -struct blorp_surf *surf,
> > 
> > > -uint32_t level, uint32_t layer);
> > 
> > > -
> > 
> > > -void
> > 
> > >  blorp_mcs_partial_resolve(struct blorp_batch *batch,
> > 
> > >struct blorp_surf *surf,
> > 
> > >enum isl_format format,
> > 
> > > diff --git a/src/intel/blorp/blorp_clear.c
> > 
> > > b/src/intel/blorp/blorp_clear.c
> > 
> > > index 6f5549f..39bc0c6 100644
> > 
> > > --- a/src/intel/blorp/blorp_clear.c
> > 
> > > +++ b/src/intel/blorp/blorp_clear.c
> > 
> > > @@ -814,6 +814,11 @@ blorp_clear_attachments(struct blorp_batch
> > 
> > > *batch,
> > 
> > > batch->blorp->exec(batch, );
> > 
> > >  }
> > 
> > >  
> > 
> > > +static void
> > 
> > > +blorp_legacy_ccs_ambiguate(struct blorp_batch *batch,
> > 
> > > +   struct blorp_surf *surf,
> > 
> > > +   uint32_t level, uint32_t layer);
> > 
> > > +
> > 
> > >  void
> > 
> > >  blorp_ccs_op(struct blorp_batch *batch,
> > 
> > >   struct blorp_surf *surf, uint32_t level,
> > 
> > > @@ -835,7 +840,7 @@ blorp_ccs_op(struct blorp_batch *batch,
> > 
> > > * mess to another function.
> > 
> > > */
> > 
> > >for (uint32_t a = 0; a < num_layers; a++)
> > 
> > > - blorp_ccs_ambiguate(batch, surf, level, start_layer +
> > a);
> > 
> > > + blorp_legacy_ccs_ambiguate(batch, surf, level,
> > start_layer
> > 
> > > + a);
> > 
> > >return;
> > 
> > > }
> > 
> > >  
> > 
> > > @@ -1022,17 +1027,11 @@ blorp_mcs_partial_resolve(struct
> > blorp_batch
> > 
> > > *batch,
> > 
> > >   * for a given layer/level of a surface to 0x0 which is the
> > 
> > > "uncompressed"
> > 
> > >   * state which tells the sampler to go look at the main surface.
> > 
> > >   */
> > 
> > > -void
> > 
> > > -blorp_ccs_ambiguate(struct blorp_batch *batch,
> > 
> > > -struct blorp_surf *surf,
> > 
> > > -uint32_t level, uint32_t layer)
> > 
> > > +static void
> > 
> > > +blorp_legacy_ccs_ambiguate(struct blorp_batch *batch,
> > 
> > > +   struct blorp_surf *surf,
> > 
> > > +   uint32_t level, uint32_t layer)
> > 
> > >  {
> > 
> > > -   if (ISL_DEV_GEN(batch->blorp->isl_dev) >= 10) {
> > 
> > > -  /* On gen10 and above, we have a hardware resolve op for
> > this
> > 
> > > */
> > 
> > > -  return blorp_ccs_op(batch, surf, level, layer, 1,
> > 
> > > -  surf->surf->format,
> > ISL_AUX_OP_AMBIGUATE);
> > 
> > > -   }
> > 
> > > -
> > 
> > 
> > 
> > Since we don't want to call this in gen10+, would it make sense to
> > an
> > 
> > assert for gen < 10?
> 
> It does work on gen10 and 11 (and we used it on gen 10 for a while). 
> I'll make it gen < 12.
> 

My point was that even if it works, we don't want this to be called for
these generations... maybe an assert would be too much for this?

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[Mesa-dev] [PATCH 00/22] spirv/intel: half-float compiler enablement

[Iago Toral Quiroga]

Most of our compiler was already 16-bit aware thanks to previous work on
VK_KHR_16bit_storage and shaderInt16, but specifically for 16-bit floating
point, we were missing a few things such as some lowerings that depend on the
specific bit representation of the float or some hardware restrictions which
we address here.

The series contains two patches from Samuel that handle float64/16 conversions,
which had been posted in the mailing list some time ago and that are also
relevant to this.

Iago Toral Quiroga (20):
  compiler/spirv: fix SpvOpIsInf for 16-bit float
  intel/compiler: lower some 16-bit float operations to 32-bit
  intel/compiler: lower 16-bit extended math to 32-bit prior to gen9
  compiler/nir: support 16-bit float in nir_imm_floatN_t
  compiler/spirv: handle 16-bit float in radians() and degrees()
  intel/compiler: implement 16-bit fsign
  intel/compiler: implement 16-bit multiply-add
  intel/compiler: allow extended math functions with HF operands
  compiler/spirv: implement 16-bit asin
  compiler/spirv: implement 16-bit acos
  compiler/spirv: implement 16-bit atan
  compiler/spirv: implement 16-bit atan2
  compiler/spirv: implement 16-bit exp and log
  compiler/spirv: implement 16-bit hyperbolic trigonometric functions
  compiler/spirv: implement 16-bit frexp
  compiler/nir: add lowering option for 16-bit fmod
  intel/compiler: lower 16-bit fmod
  compiler/nir: add lowering for 16-bit flrp
  intel/compiler: lower 16-bit flrp
  intel/compiler: Extended Math is limited to SIMD8 on half-float

Samuel Iglesias Gonsálvez (2):
  i965/fs: implement conversions from float16 to 64 bits data types
  i965/fs: Implement float64 to float16 conversion

 src/compiler/nir/nir.h|   2 +
 src/compiler/nir/nir_builder.h|  29 +++---
 src/compiler/nir/nir_opt_algebraic.py |   2 +
 src/compiler/spirv/vtn_alu.c  |   4 +-
 src/compiler/spirv/vtn_glsl450.c  | 176 +-
 src/intel/compiler/brw_compiler.c |   2 +
 src/intel/compiler/brw_eu_emit.c  |   6 +-
 src/intel/compiler/brw_fs.cpp |  30 --
 src/intel/compiler/brw_fs_nir.cpp |  85 ++--
 src/intel/compiler/brw_nir.c  |  18 +++-
 10 files changed, 279 insertions(+), 75 deletions(-)

-- 
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Re: [Mesa-dev] [PATCH 3/3] mesa/main/shaderapi: purely non-functional cleanups, like whitespace errors and cleanups

[Benedikt Schemmer]

Am 17.05.2018 um 08:59 schrieb Tapani Pälli:
> 
> 
> On 05/10/2018 12:05 PM, Benedikt Schemmer wrote:
>> remove a memset too and yes, this is all functionally identical
>>
>> ---
>>   src/mesa/main/shaderapi.c | 40 
>>   1 file changed, 20 insertions(+), 20 deletions(-)
>>
>> diff --git a/src/mesa/main/shaderapi.c b/src/mesa/main/shaderapi.c
>> index e8acca4490..1d0ca5374b 100644
>> --- a/src/mesa/main/shaderapi.c
>> +++ b/src/mesa/main/shaderapi.c
>> @@ -241,11 +241,10 @@ _mesa_init_shader_state(struct gl_context *ctx)
>>  /* Device drivers may override these to control what kind of 
>> instructions
>>   * are generated by the GLSL compiler.
>>   */
>> -   struct gl_shader_compiler_options options;
>> +   struct gl_shader_compiler_options options = {};
>>  gl_shader_stage sh;
>>  int i;
>>
>> -   memset(, 0, sizeof(options));
>>  options.MaxUnrollIterations = 32;
>>  options.MaxIfDepth = UINT_MAX;
>>
>> @@ -254,7 +253,7 @@ _mesa_init_shader_state(struct gl_context *ctx)
>>
>>  ctx->Shader.Flags = _mesa_get_shader_flags();
>>
>> -   if (ctx->Shader.Flags != 0)
>> +   if (ctx->Shader.Flags)
>>     ctx->Const.GenerateTemporaryNames = true;
>>
>>  /* Extended for ARB_separate_shader_objects */
>> @@ -771,7 +770,8 @@ get_programiv(struct gl_context *ctx, GLuint program, 
>> GLenum pname,
>>     GLint *params)
>>   {
>>  struct gl_shader_program *shProg
>> -  = _mesa_lookup_shader_program_err(ctx, program, 
>> "glGetProgramiv(program)");
>> +  = _mesa_lookup_shader_program_err(ctx, program,
>> +    "glGetProgramiv(program)");
>>
>>  /* Is transform feedback available in this context?
>>   */
>> @@ -953,7 +953,7 @@ get_programiv(struct gl_context *ctx, GLuint program, 
>> GLenum pname,
>>     *params = shProg->BinaryRetreivableHint;
>>     return;
>>  case GL_PROGRAM_BINARY_LENGTH:
>> -  if (ctx->Const.NumProgramBinaryFormats == 0) {
>> +  if (!ctx->Const.NumProgramBinaryFormats) {
> 
> Maybe it's just me having some OCD but with these 'Num' constants I find it 
> much easier to read '== 0' than '!' (also below with NumProgramBinaryFormats 
> and NumSubroutineUniformRemapTable).
> 
> I don't feel strong about this though so no need to change this.

I dont have strong feelings about this either, I use a script to replace these 
things.
In my opinion it just helps to see whether these comparisons have meaning. >=1 
or ==0 don't really.
If they do I just use a define to make it clear. Otherwise I find the ! easier 
to read and understand.

> 
>>    *params = 0;
>>     } else {
>>    _mesa_get_program_binary_length(ctx, shProg, params);
>> @@ -974,7 +974,7 @@ get_programiv(struct gl_context *ctx, GLuint program, 
>> GLenum pname,
>>    "linked)");
>>    return;
>>     }
>> -  if (shProg->_LinkedShaders[MESA_SHADER_COMPUTE] == NULL) {
>> +  if (!shProg->_LinkedShaders[MESA_SHADER_COMPUTE]) {
>>    _mesa_error(ctx, GL_INVALID_OPERATION, "glGetProgramiv(no compute 
>> "
>>    "shaders)");
>>    return;
>> @@ -1234,7 +1234,7 @@ _mesa_compile_shader(struct gl_context *ctx, struct 
>> gl_shader *sh)
>>  } else {
>>     if (ctx->_Shader->Flags & GLSL_DUMP) {
>>    _mesa_log("GLSL source for %s shader %d:\n",
>> - _mesa_shader_stage_to_string(sh->Stage), sh->Name);
>> +   _mesa_shader_stage_to_string(sh->Stage), sh->Name);
>>    _mesa_log("%s\n", sh->Source);
>>     }
>>
>> @@ -1381,13 +1381,13 @@ link_program(struct gl_context *ctx, struct 
>> gl_shader_program *shProg,
>>     GLuint i;
>>
>>     printf("Link %u shaders in program %u: %s\n",
>> -   shProg->NumShaders, shProg->Name,
>> -   shProg->data->LinkStatus ? "Success" : "Failed");
>> + shProg->NumShaders, shProg->Name,
>> + shProg->data->LinkStatus ? "Success" : "Failed");
>>
>>     for (i = 0; i < shProg->NumShaders; i++) {
>>    printf(" shader %u, stage %u\n",
>> -  shProg->Shaders[i]->Name,
>> -  shProg->Shaders[i]->Stage);
>> +    shProg->Shaders[i]->Name,
>> +    shProg->Shaders[i]->Stage);
>>     }
>>  }
>>   }
>> @@ -1460,7 +1460,7 @@ void
>>   _mesa_active_program(struct gl_context *ctx, struct gl_shader_program 
>> *shProg,
>>    const char *caller)
>>   {
>> -   if ((shProg != NULL) && !shProg->data->LinkStatus) {
>> +   if ((shProg) && !shProg->data->LinkStatus) {
> 
> remove extra parenthesis
> 
>>     _mesa_error(ctx, GL_INVALID_OPERATION,
>>     "%s(program %u not linked)", caller, shProg->Name);
>>     return;
>> @@ -1794,7 +1794,7 @@ void GLAPIENTRY
>>   _mesa_GetObjectParameterfvARB(GLhandleARB object, GLenum pname,
>>     

Re: [Mesa-dev] [PATCH 1/3] mesa/main/shaderapi: Use generate_sha1() unconditionally

[Benedikt Schemmer]

Thanks for reviewing!

Am 17.05.2018 um 08:42 schrieb Tapani Pälli:
> 
> 
> On 05/10/2018 12:05 PM, Benedikt Schemmer wrote:
>> Move shader-cache code from back to front and make generate_sha1() usable
>> unconditionally to avoid code duplication in the following patch
>>
>> ---
>>   src/mesa/main/shaderapi.c | 228 
>> +++---
>>   1 file changed, 116 insertions(+), 112 deletions(-)
>>
>> diff --git a/src/mesa/main/shaderapi.c b/src/mesa/main/shaderapi.c
>> index 44b18af492..e8acca4490 100644
>> --- a/src/mesa/main/shaderapi.c
>> +++ b/src/mesa/main/shaderapi.c
>> @@ -64,6 +64,122 @@
>>   #include "util/mesa-sha1.h"
>>   #include "util/crc32.h"
>>
>> +
>> +/**
>> + * Generate a SHA-1 hash value string for given source string.
>> + */
>> +static void
>> +generate_sha1(const char *source, char sha_str[64])
>> +{
>> +   unsigned char sha[20];
>> +   _mesa_sha1_compute(source, strlen(source), sha);
>> +   _mesa_sha1_format(sha_str, sha);
>> +}
> 
> There is one potential problem here. The 'ENABLE_SHADER_CACHE' guard for 
> generate_sha1 and others was placed there because the imported sha1 code 
> broke windows build, I'm wondering if this is still
> the case? If so, then generate_sha1 should be inside ENABLE_SHADER_CACHE 
> guard.
> 

I did a quick
gedit $(grep -Rlsi "_mesa_sha1_compute" | grep -E "\.c|\.h")

and it seems radv and anv use _mesa_sha1_compute (and _mesa_sha1_format) 
without a guard
best example from Intel seems to be brw_disk_cache.c which uses it alot outside 
of the ENABLE_SHADER_CACHE guard

so probably safe?

>> +
>> +
>> +#ifdef ENABLE_SHADER_CACHE
>> +/**
>> + * Construct a full path for shader replacement functionality using
>> + * following format:
>> + *
>> + * /_.glsl
>> + */
>> +static char *
>> +construct_name(const gl_shader_stage stage, const char *source,
>> +   const char *path)
>> +{
>> +   char sha[64];
>> +   static const char *types[] = {
>> +  "VS", "TC", "TE", "GS", "FS", "CS",
>> +   };
>> +
>> +   generate_sha1(source, sha);
>> +   return ralloc_asprintf(NULL, "%s/%s_%s.glsl", path, types[stage], sha);
>> +}
>> +
>> +/**
>> + * Write given shader source to a file in MESA_SHADER_DUMP_PATH.
>> + */
>> +static void
>> +dump_shader(const gl_shader_stage stage, const char *source)
>> +{
>> +   static bool path_exists = true;
>> +   char *dump_path;
>> +   FILE *f;
>> +
>> +   if (!path_exists)
>> +  return;
>> +
>> +   dump_path = getenv("MESA_SHADER_DUMP_PATH");
>> +   if (!dump_path) {
>> +  path_exists = false;
>> +  return;
>> +   }
>> +
>> +   char *name = construct_name(stage, source, dump_path);
>> +
>> +   f = fopen(name, "w");
>> +   if (f) {
>> +  fputs(source, f);
>> +  fclose(f);
>> +   } else {
>> +  GET_CURRENT_CONTEXT(ctx);
>> +  _mesa_warning(ctx, "could not open %s for dumping shader (%s)", name,
>> +    strerror(errno));
>> +   }
>> +   ralloc_free(name);
>> +}
>> +
>> +/**
>> + * Read shader source code from a file.
>> + * Useful for debugging to override an app's shader.
>> + */
>> +static GLcharARB *
>> +read_shader(const gl_shader_stage stage, const char *source)
>> +{
>> +   char *read_path;
>> +   static bool path_exists = true;
>> +   int len, shader_size = 0;
>> +   GLcharARB *buffer;
>> +   FILE *f;
>> +
>> +   if (!path_exists)
>> +  return NULL;
>> +
>> +   read_path = getenv("MESA_SHADER_READ_PATH");
>> +   if (!read_path) {
>> +  path_exists = false;
>> +  return NULL;
>> +   }
>> +
>> +   char *name = construct_name(stage, source, read_path);
>> +   f = fopen(name, "r");
>> +   ralloc_free(name);
>> +   if (!f)
>> +  return NULL;
>> +
>> +   /* allocate enough room for the entire shader */
>> +   fseek(f, 0, SEEK_END);
>> +   shader_size = ftell(f);
>> +   rewind(f);
>> +   assert(shader_size);
>> +
>> +   /* add one for terminating zero */
>> +   shader_size++;
>> +
>> +   buffer = malloc(shader_size);
>> +   assert(buffer);
>> +
>> +   len = fread(buffer, 1, shader_size, f);
>> +   buffer[len] = 0;
>> +
>> +   fclose(f);
>> +
>> +   return buffer;
>> +}
>> +
>> +#endif /* ENABLE_SHADER_CACHE */
>> +
>>   /**
>>    * Return mask of GLSL_x flags by examining the MESA_GLSL env var.
>>    */
>> @@ -1775,119 +1891,7 @@ _mesa_LinkProgram(GLuint programObj)
>>  link_program_error(ctx, shProg);
>>   }
>>
>> -#ifdef ENABLE_SHADER_CACHE
>> -/**
>> - * Generate a SHA-1 hash value string for given source string.
>> - */
>> -static void
>> -generate_sha1(const char *source, char sha_str[64])
>> -{
>> -   unsigned char sha[20];
>> -   _mesa_sha1_compute(source, strlen(source), sha);
>> -   _mesa_sha1_format(sha_str, sha);
>> -}
>> -
>> -/**
>> - * Construct a full path for shader replacement functionality using
>> - * following format:
>> - *
>> - * /_.glsl
>> - */
>> -static char *
>> -construct_name(const gl_shader_stage stage, const char *source,
>> -   const char *path)
>> -{
>> -   char sha[64];
>> -   static const char