If we can choose an standardized design methodology, I think we can
exchange our codes. My VHDL coding-style is technology-independent, which
means that one can use it for implementing in Xilinx FPGAs, in Altera
FPGAs, and also for ASIC fabrication. AFAIK, as I saw in Kunihiko's VDP
code, I
Well, I think it is a matter of negotiation between the VHDL-coders.
Personally, I didn't like the agreement proposed by Tsujikawa.
And there is another problem: my design methodology is based in chip
replacement, and Tsujikawa's methodology consists in creating new
boards. This method is
I have the same problem with my Sanyo MSX2+ 70FD. The problem lays in the
plastic flatcable connection from the keyboard to the mainboard. In my case,
it's that bad that even after I put it right again (with much much effort
'cause however I put it it never seems to work), when I close the case
On Mon, 26 Aug 2002, Laurens Holst wrote:
Yet, these efforts aren't joined, which I think *really* is a shame. If all
these people would join their efforts, I honestly believe a one-chip MSX for
example could be made right now, or at least in the not-so-distant future,
say, within the year!
On Tue, 27 Aug 2002, Snout wrote:
But the efforts of changing to a standardized methodology could lead to
rapid
realisation of a one-chip MSX. At least, that's the way I see it.
Yes, I agree, and as a hardware developer, I am here open for
discussions. So, what about the japanese hardware
On Tue, 27 Aug 2002, Laurens Holst wrote:
If we can choose an standardized design methodology, I think we can
exchange our codes. My VHDL coding-style is technology-independent, which
means that one can use it for implementing in Xilinx FPGAs, in Altera
FPGAs, and also for ASIC
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SCC/SCC+ are already implemented in FPGA by Ademir Carchano.
Does anyone know his working e-mail? His page is down...
Dark Soul
e-mail: [EMAIL PROTECTED]
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Get your free mail box @ http://www.mail.md
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Please cut this HTML crap. I can't read through it. Not all people
enjoy great products from multibillion corporation in richmond.
DIV/DIVFrom: Daniel Caetano [EMAIL PROTECTED]
DIV/DIVReply-To: [EMAIL PROTECTED]
DIV/DIVTo: [EMAIL PROTECTED] [EMAIL PROTECTED]
DIV/DIVSubject: [MSX]
And also, if the ESE FPGA project belongs to the MSX Association or
not. Personally, I think that if the MSX Association wants to make money
with the hardware developed by Tsujikawa, then I also want. For me it's
not clear what is the goal of ESE.
ESE FPGA project is NOT part of MSX
On Tue, 27 Aug 2002, Dark Soul wrote:
SCC/SCC+ are already implemented in FPGA by Ademir Carchano.
Does anyone know his working e-mail? His page is down...
Actually his e-mail is also down.
What do you wanna know about Ademir projects? Maybe I can talk to him.
[]'s
Ah. Heh, it's great to actually have direct communication with one of
the
VHDL coders out there, since contact with all others has to go through
other
people :). I just re-read the MSX print, and the part about the
cooperation
I agree, and it seems that this is one of the barriers of the
On Tue, 27 Aug 2002, Patriek Lesparre wrote:
And also, if the ESE FPGA project belongs to the MSX Association or
not. Personally, I think that if the MSX Association wants to make money
with the hardware developed by Tsujikawa, then I also want. For me it's
not clear what is the goal of ESE.
SCC/SCC+ are already implemented in FPGA by Ademir Carchano.
Does anyone know his working e-mail? His page is down...
Actually his e-mail is also down.
What do you wanna know about Ademir projects? Maybe I can talk to him.
I want to buy his MegaIDE cartridge. It's a very awesome piece
On Wed, 28 Aug 2002, Dark Soul wrote:
SCC/SCC+ are already implemented in FPGA by Ademir Carchano.
Does anyone know his working e-mail? His page is down...
Actually his e-mail is also down.
What do you wanna know about Ademir projects? Maybe I can talk to him.
I want to buy his
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