Dennis
The reason you want to use update afterwards is because you want to update
relative to the latest netlist.
Mike
- Original Message -
From: Dennis Saputelli [EMAIL PROTECTED]
To: Protel EDA Forum [EMAIL PROTECTED]
Sent: Sunday, August 25, 2002 11:52 AM
Subject: Re: [PEDA]
Thanks Guys,
I see all of your points, I agree with you that
once you understand how it works
you can use it safely. (it can be a time issue if
you get out of wack)
I was trying to point out that if you are not
careful and like you said understand what
it will do it can take a bit of time to get
All,
For those that might be trying the multichannel feature of DXP: I just
learned the hard way (hours of fiddling) about a few confusing things with
the method. The little bit of documentation in the manual, Introducing
Protel DXP, creates a couple of misunderstandings that I could only
Hello all,
I have a client that is looking for a Protel 99SE license. Does anyone have
one for sale. Please email me off-line at [EMAIL PROTECTED]
Thanks,
Lloyd Good
Circuit Creations
92 Holly Street NW
Calgary AB Canada
T2K 2C8
ph: (403)282-6445
cell:(403)710-5077
Hi all,
I am currently designing a printed circuit board in which the main part is a XILINX
FPGA.
What I want to know is: (please read on)
Upon completion of the schematics of the board design
do PCB designers do anything to verify the correctness of the board
schematics like
Yes, you trust the schematic and its netlist. If it is wrong, then the
person that did the schematic screwed up. Now of course you can tell
them you spotted something, like a power pin that was floating because
they were using hidden pins and forgot to connect the right name, but
don't fix it for
LLoyd,
I tried posting direct to you at your [EMAIL PROTECTED] , twice,
and it bombed both tomes with the following fatal error message:
The original message was received at Mon, 26 Aug 2002 16:18:03 -0400
from xxx.xxx.xxx.xxx pacbell.net [xxx.xxx.xxx.xxx]
- The following addresses had
Anand,
you are asking questions to which the answers shall be as varied as
the number of respondents. The answers will of course be based upon the
environments where the designers work. Some designers are actually EEs and
they do all the design including PCBs, some are EEs but only do the
Anand asked:
I am currently designing a printed circuit board in which the main part is a
XILINX FPGA.
What I want to know is: (please read on)
Upon completion of the schematics of the board design
do PCB designers do anything to verify the correctness of the board
schematics like
Hi Tim,
The drawing routines for this were overlooked in the first release but will
be updated to correctly draw the overlapping style in SP1. My apologies
for the confusion.
Best Regards,
Nick Martin
Joint CEO, Altium
- Original Message -
From: Tim Hutcheson [EMAIL PROTECTED]
To:
Anand Kulkarni wrote:
Hi all,
I am currently designing a printed circuit board in which the main part is a XILINX
FPGA.
What I want to know is: (please read on)
Upon completion of the schematics of the board design
do PCB designers do anything to verify the correctness of the board
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