Re: [PEDA] six or eight-layer (or more?) stackups

The text book standard that is 1signal 2gnd 3signal 4gnd 5pwr 6signal 7pwr 8signal I thought that the following stackup was prefered because then every signal is one layer from a ground plane. 1signal 2gnd 3signal 4pwr 5pwr

Re: [PEDA] metric footprint

John, Assume that you don't have any info from the mfg other than the package dimensions. How do you then come up with a footprint? Specifically, I find that the dimensions requested by Protel are typically not the dimensions provided by the mfg datasheet, so it can get confusing to figure

Re: [PEDA] eight-layer stackup

Just one note on split planes. High speed signals crossing splits in either power or ground (they're the same for AC), there will be a reflection due to the sharp impedance change. Of course the effect will vary depending on trace length and split length and locations of nearby bypass caps. In

Re: [PEDA] six or eight-layer (or more?) stackups

I thought that the following stackup was prefered because then every signal is one layer from a ground plane. 1signal 2gnd 3signal 4pwr 5pwr 6signal 7gnd 8signal But then you don't have as good decoupling between your pwr and gnd planes, since

Re: [PEDA] six or eight-layer (or more?) stackups - Capacitance

At 03:44 PM 6/3/2003 -0400, you wrote: I thought that the following stackup was prefered because then every signal is one layer from a ground plane. 1signal 2gnd 3signal 4pwr 5pwr 6signal 7gnd 8signal But then you don't have as good decoupling

[PEDA] Orcad Layout 9.2 vs. Protel

Recently we were asked to violate our normal practices and use Orcad Layout (Version 9.2) to do a customer's job, instead of Protel. Can anyone point to a more or less objective written comparison between the capabilities of these rival packages? Or provide such a comparison based on personal

Re: [PEDA] metric footprint

Bryn, The IPC has a calculator at http://landpatterns.ipc.org/default.asp that can assist with the land pattern design. But be warned: there's a fundamental flaw with IPC-SM-782 calculation method that adds all tolerances together (thus assuming that every parameter will be at worst-case

Re: [PEDA] six or eight-layer (or more?) stackups - Capacitance

First, my experience regarding layout is minimal at best since I seem to exhaust all the wrong ways first. I once took a class in multilayer layout and was told that the capacitance between the power/ground planes themselves was sufficient for decoupling high frequencies and that adding

Re: [PEDA] six or eight-layer (or more?) stackups - Capacitance

Ray, It is indeed possible to design a board where no external caps are required BUT there are major caveats! An interplane capacitor is indeed the best cap you'll ever get on a board however the total capacitance available is limited. This means that your design must be capable of working with

Re: [PEDA] six or eight-layer (or more?) stackups

Bagotronix Tech Support wrote: I thought that the following stackup was prefered because then every signal is one layer from a ground plane. 1signal 2gnd 3signal 4pwr 5pwr 6signal 7gnd 8signal But then you don't have as good decoupling between your pwr and

[PEDA] Re[2]: six or eight-layer (or more?) stackups - Capacitance

JH 2/ Use a spread of capacitor values so that you swap one or two deep JH resonant nulls for a swag of shallower ones spread across the spectrum. I found this to be interesting. I've just about finished reading Digital Design for Interference Specifications David l. Terrell, R.Kenneth Keenan,

Re: [PEDA] metric footprint

I'm not familiar with any current work reflecting this. (Doesn't mean that I'm up to the minute with my reading though...) IPC-SM-782a suggests (section 3.3.3.1) fillets in the range of: Toe: 0.4mm - 0.6mm Heel: 0.0mm - 0.2mm Side: -0.02mm - 0.02mm I've always been wary of excess heel fillet

Re: [PEDA] Re[2]: six or eight-layer (or more?) stackups - Capacitance

- Original Message - From: Phillip Stevens [EMAIL PROTECTED] To: Protel EDA Forum [EMAIL PROTECTED] Sent: Wednesday, June 04, 2003 7:22 AM Subject: [PEDA] Re[2]: six or eight-layer (or more?) stackups - Capacitance JH 2/ Use a spread of capacitor values so that you swap one or two

Re: [PEDA] metric footprint

John Haddy wrote: I'm not familiar with any current work reflecting this. (Doesn't mean that I'm up to the minute with my reading though...) IPC-SM-782a suggests (section 3.3.3.1) fillets in the range of: Toe: 0.4mm - 0.6mm Heel: 0.0mm - 0.2mm Side: -0.02mm - 0.02mm I've always been wary of

Re: [PEDA] eight-layer stackup

Jami, you missed a few important points. Generating a netlist and loading it into your PCB is not hard to do. It is a few more mouse clicks (maybe 20 seconds more work) than just hitting update. Your time is surely not that valuable, is it?? like I said: generate a netlist - it gives you the