On Thu, 23 Aug 2001 11:14:19 +0200, Florian Finsterbusch wrote:
i have just seen your new layer-stackup for your 8-layer PCB.
But i'm wondering about the numbers of prepregs.
I think when you put 4 cores with copper on both sides together, you need
only 3 prepregs.
Not so simple.
I believe
Got it. Thanks. Does anybody have any ideas about how much the dielectric
constant generally changes as a result of the pressing process and by how
much a 5-mil trace shrinks on average? If I had a general idea about this I
could make a better estimate of the target configuration needed for
Thanks Florian. I visited Polar's site and notice that
CITS25 Impedance calculator, now replaced by Si6000 controlled impedance
design software.
So I am having a look at Si6000 right now. I have implemented much of
several good books on my TI-92 calc though and continue to refine that as I
23, 2001 8:18 AM
To: Protel EDA Forum
Subject: Re: [PEDA] Warping on small odd layer boards.
Got it. Thanks. Does anybody have any ideas about how much
the dielectric
constant generally changes as a result of the pressing
process and by how
much a 5-mil trace shrinks on average
Dr.,
Burnaby, B.C., V5C 6G9.
Tel. (604) 292-9089 direct
Fax (604) 292-9010
website www.norsat.com
-Original Message-
From: Tim Hutcheson [mailto:[EMAIL PROTECTED]]
Sent: Thursday, August 23, 2001 8:28 AM
To: Protel EDA Forum
Subject: Re: [PEDA] Warping on small odd layer boards
functions like printing.
(You can use a screen dump utilty instead :-)
Florian
-Urspr ngliche Nachricht-
Von: Tim Hutcheson [mailto:[EMAIL PROTECTED]]
Gesendet: Donnerstag, 23. August 2001 17:28
An: Protel EDA Forum
Betreff: Re: [PEDA] Warping on small odd layer boards.
Thanks
Terry Harris wrote:
On Wed, 22 Aug 2001 16:24:37 -0500, Tim Hutcheson wrote:
Since my source resistance is 53 ohms, I have less than 2% mismatch.
Just to inject a little reality here. Board houses can not control layer
thickness to anything like 2%. The can mic up the cores and maybe get
Has anyone any experience building small (4x7 inch) 7-layer .063 boards? I
would like to have a certain stack up impedance that is best met with
4,9,9,9,9,4 for the 5-mil trace widths I am using but I know from what I
have read that warping can be a problem. On the other hand, a conventional
: Tim Hutcheson [mailto:[EMAIL PROTECTED]]
Sent: Wednesday, August 22, 2001 10:53 AM
To: Protel EDA Forum
Subject: [PEDA] Warping on small odd layer boards.
Has anyone any experience building small (4x7 inch) 7-layer
.063 boards? I
would like to have a certain stack up impedance
August 22, 2001 10:53 AM
>> To: Protel EDA Forum
>> Subject: [PEDA] Warping on small odd layer boards.
>>
>>
>>
>> Has anyone any experience building small (4x7 inch) 7-layer
>> .063" boards? I would like to have a certain stack up impedance
www.norsat.com
-Original Message-
From: Tim Hutcheson [mailto:[EMAIL PROTECTED]]
Sent: Wednesday, August 22, 2001 12:56 PM
To: Protel EDA Forum
Subject: Re: [PEDA] Warping on small odd layer boards.
Brad, thanks. Now I know how to count them. :o) And yes
the thinner layer
Tim Hutcheson wrote:
Has anyone any experience building small (4x7 inch) 7-layer .063 boards? I
would like to have a certain stack up impedance that is best met with
4,9,9,9,9,4 for the 5-mil trace widths I am using but I know from what I
have read that warping can be a problem.
I
I'm learning, thanks. I have only just gotten to the point of trying to
understand how the layers are put together. And it is real easy to miss the
practical details.
Tim Hutcheson
Institute for Human and Machine Cognition
40 S. Alcaniz St.
Pensacola, FL. 32503
* * * * * * * * * * * * * * *
Tim Hutcheson wrote:
I'm learning, thanks. I have only just gotten to the point of trying to
understand how the layers are put together. And it is real easy to miss the
practical details.
This is somewhat of a problem. Unless you read the trade journals
of the PCB industry, or have done
Yes, I understand that problem. As I get closer being certain of the design
issues and the design itself, I will start working with a board vendor
closely to be sure I am specifying something they can build at a reasonable
cost. I am trying to stay in the mainstream of the high end PCB
On Wed, 22 Aug 2001 16:24:37 -0500, Tim Hutcheson wrote:
Since my source resistance is 53 ohms, I have less than 2% mismatch.
Just to inject a little reality here. Board houses can not control layer
thickness to anything like 2%. The can mic up the cores and maybe get close
to what you want
Indeed. But we can only do the calculations for what we have control of, so
that we are in the center of the remaining variance window that we don't
have any/much control of unless we go to expensive processes. Just getting
in the center has been enough challenge for me. :o)
regards,
Tim
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