[PEDA] Vias do not tent when expected
Hi. I just discovered something strange: I like my vias tented so I keep the tenting checkbox in the default via settings dialog checked. While interactively routing a PCB I noticed that the automatically placed vias did not get tented (and the forementioned checkbox is still checked) I do not want to end up with a board that has some vias tented and some not, and the global edit on the complete board afterwards is too easiliy forgotten. I'm sure I'm missing something obvious, but haven't a clue Please help me out, guys.. Leo Potjewijd hardware designer Integrated Engineering B.V. [EMAIL PROTECTED] +31 20 4620700 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
[PEDA] Pads and single pin connectors.
Hey guys, I've got a problem I can't figure out. We do a lot of interconnect with wires soldered into a single pad. We generally designate them as E?. I cannot figure out how to relate the pad to the schematic. I've tried using the one pin CON1 out of the library. I've tried naming a port symbol. Neither seem to work with the Update schematic option. Any ideas on what I'm doing wrong? Michael Badillo * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Pads and single pin connectors.
maybe the pad of the E is not the same number as the pin of your one pin Dennis Saputelli [EMAIL PROTECTED] wrote: Hey guys, I've got a problem I can't figure out. We do a lot of interconnect with wires soldered into a single pad. We generally designate them as E?. I cannot figure out how to relate the pad to the schematic. I've tried using the one pin CON1 out of the library. I've tried naming a port symbol. Neither seem to work with the Update schematic option. Any ideas on what I'm doing wrong? Michael Badillo * * * * * * * * * * * * * * * * * * * * -- ___ Integrated Controls, Inc. Tel: 415-647-0480 EXT 107 2851 21st StreetFax: 415-647-3003 San Francisco, CA 94110 www.integratedcontrolsinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Pads and single pin connectors.
I'm guessing your PCB object is a free pad??? I'm also guessing you don't have a PCB footprint defined in your 'CON1' sch part?? An object on the schematic needs to match an object on the PCB. If you use the CON1 sch part, you need to assign a footprint to it. I have a footprint called PAD100 that I use for the same thing (a wire soldered onto the board) These two objects are treated like any other part on the SCH/PCB pair of documents. -Original Message- From: [EMAIL PROTECTED] [mailto:[EMAIL PROTECTED] Sent: Wednesday, March 03, 2004 8:34 AM To: [EMAIL PROTECTED] Subject: [PEDA] Pads and single pin connectors. Hey guys, I've got a problem I can't figure out. We do a lot of interconnect with wires soldered into a single pad. We generally designate them as E?. I cannot figure out how to relate the pad to the schematic. I've tried using the one pin CON1 out of the library. I've tried naming a port symbol. Neither seem to work with the Update schematic option. Any ideas on what I'm doing wrong? Michael Badillo * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Pads and single pin connectors.
At 03-03-2004 17:34, [EMAIL PROTECTED] wrote: Hey guys, I've got a problem I can't figure out. We do a lot of interconnect with wires soldered into a single pad. We generally designate them as E?. I cannot figure out how to relate the pad to the schematic. I've tried using the one pin CON1 out of the library. I've tried naming a port symbol. Neither seem to work with the Update schematic option. Any ideas on what I'm doing wrong? As long as the wire ends are not on the schematic as components the synchroniser doesn't know what to do. I will assume that you are talking about wires with no fixed relation between start- and enpoint, otherwise you could use a (modified) axial resistor... I use a special (single pin) component for this purpose, its' standard footprint is just a pad with a circle around it on the top overlay. Without that circle it is very hard to grab the thing as component when the designator gets hidden or erased although a fill on a soldermask (or a mechanical layer) will do the trick too. For wires that connect points on the same PCB/schematic you need to visualise that wire in the schematic using two single-pin connectors and a line from the drawing tools. Do not use a wire, otherwise you will be stuck with an 'unrouted net' error later on... Unfortunately there is no way that I know of to mark these two single-pin connectors as a pair in order to make the DRC recognise the 'external' wire correctly. What one would really need in this case is the PCB equivalent of a multi-part schematic component (and a DRC setting to flag unplaced parts). Hope this helps * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Pads and single pin connectors.
Yes, I have. I've even gone so far as to cut the designator out of the net list and paste it into the designator field of the pad. Still didn't help. Any other ideas? Michael From: Dennis Saputelli [EMAIL PROTECTED] Date: 2004/03/03 Wed PM 12:40:23 EST To: Protel EDA Forum [EMAIL PROTECTED] Subject: Re: [PEDA] Pads and single pin connectors. maybe the pad of the E is not the same number as the pin of your one pin Dennis Saputelli [EMAIL PROTECTED] wrote: Hey guys, I've got a problem I can't figure out. We do a lot of interconnect with wires soldered into a single pad. We generally designate them as E?. I cannot figure out how to relate the pad to the schematic. I've tried using the one pin CON1 out of the library. I've tried naming a port symbol. Neither seem to work with the Update schematic option. Any ideas on what I'm doing wrong? Michael Badillo * * * * * * * * * * * * * * * * * * * * -- ___ Integrated Controls, Inc. Tel: 415-647-0480 EXT 107 2851 21st StreetFax: 415-647-3003 San Francisco, CA 94110 www.integratedcontrolsinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Pads and single pin connectors.
Aha! Thanx, Michael From: Tony Karavidas [EMAIL PROTECTED] Date: 2004/03/03 Wed PM 12:44:44 EST To: 'Protel EDA Forum' [EMAIL PROTECTED] Subject: Re: [PEDA] Pads and single pin connectors. I'm guessing your PCB object is a free pad??? I'm also guessing you don't have a PCB footprint defined in your 'CON1' sch part?? An object on the schematic needs to match an object on the PCB. If you use the CON1 sch part, you need to assign a footprint to it. I have a footprint called PAD100 that I use for the same thing (a wire soldered onto the board) These two objects are treated like any other part on the SCH/PCB pair of documents. -Original Message- From: [EMAIL PROTECTED] [mailto:[EMAIL PROTECTED] Sent: Wednesday, March 03, 2004 8:34 AM To: [EMAIL PROTECTED] Subject: [PEDA] Pads and single pin connectors. Hey guys, I've got a problem I can't figure out. We do a lot of interconnect with wires soldered into a single pad. We generally designate them as E?. I cannot figure out how to relate the pad to the schematic. I've tried using the one pin CON1 out of the library. I've tried naming a port symbol. Neither seem to work with the Update schematic option. Any ideas on what I'm doing wrong? Michael Badillo * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Pads and single pin connectors.
Okay, that seems to be part of the problem, but it raises another question. Does the single pad in question have to be on the master schematic? I can get the pads on the master to work, but the sub-drawings are still being difficult. Thanx, Michael Badillo * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Vias do not tent when expected
At 03-03-04 22:24, BROCK RUSSELL wrote: Probably the current default for vias is not set for tenting. Check in Tools/Preferences/Defaults for the via property settings. Brock Russell Sorry Brock, just checked and is _is_ set for tenting Manually' placed vias tent, but auto-placed vias don't. Happens on two different systems (same ddb though). Leo * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Pads and single pin connectors.
No they don't have to be, but I put them there. The single pad part is just like any other part. If you can have a resistor on a schematic 2 levels deep, then a single pad part can be there too. I put ALL connectors at the top level because this graphically indicates what leaves the board. I don't like wading through multipage schematics looking for connectors. I want to know in one image what is coming onto the board and what is leaving. So my schematics always look like a top level full of connectors and blocks; the blocks contain all of the 'circuitry' of the design. Tony -Original Message- From: [EMAIL PROTECTED] [mailto:[EMAIL PROTECTED] Sent: Wednesday, March 03, 2004 1:02 PM To: Protel EDA Forum Subject: Re: [PEDA] Pads and single pin connectors. Okay, that seems to be part of the problem, but it raises another question. Does the single pad in question have to be on the master schematic? I can get the pads on the master to work, but the sub-drawings are still being difficult. Thanx, Michael Badillo * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Vias do not tent when expected
On 12:28 AM 4/03/2004, Leo Potjewijd said: Hi. I just discovered something strange: I like my vias tented so I keep the tenting checkbox in the default via settings dialog checked. While interactively routing a PCB I noticed that the automatically placed vias did not get tented (and the forementioned checkbox is still checked) I do not want to end up with a board that has some vias tented and some not, and the global edit on the complete board afterwards is too easiliy forgotten. I'm sure I'm missing something obvious, but haven't a clue Please help me out, guys.. There are two ways to force tenting on vias - or at least there are two places to control the solder mask expansion. The via has a tenting attribute and there is a design rule that controls solder mask expansion. I have no idea which has precedence, I would hope the tenting attribute of the via. However you may want to check, and play with, the Manufacturing-Solder Mask expansion rule. If you make the rule expansion ridiculously big do the auto-placed vias follow the silly expansion? Before we had the tenting attribute you had to apply a large enough negative expansion to force tenting. The checkbox being tented but the actual via being untented does sound very odd - unless there is a conflict between the rules and the tent attribute. Are the auto-placed vias the same dimensions as the manual placed vias? Are they both vias? The manual ones aren't free pads are they? (Just asking some possibly silly questions.) What happens if you save as ASCII and then re-load? What does the ASCII file show for a tented and untented via? The ASCII records are not hard to read. Not sure I have too many other ideas. Bye for now, Ian * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
[PEDA] Protel Designer needed
I happen to know of a 4 month or longer assignment that requires a Protel Designer with Protel 99SE SP6 experience. If you know of someone in the San Diego area that could do this job please send me a resume so I can forward it to the interested party. Bill Brooks PCB Design Engineer , C.I.D., C.I.I. Tel: (760)597-1500 Ext 3772 Fax: (760)597-1510 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Vias do not tent when expected
in 99SE the via tenting attribute (and/or the override) will take precendence over a design rule expansion amount as it should IMO i have never seen one be untented mysteriously, but maybe i never noticed it Dennis Saputelli Ian Wilson wrote: On 12:28 AM 4/03/2004, Leo Potjewijd said: Hi. I just discovered something strange: I like my vias tented so I keep the tenting checkbox in the default via settings dialog checked. While interactively routing a PCB I noticed that the automatically placed vias did not get tented (and the forementioned checkbox is still checked) I do not want to end up with a board that has some vias tented and some not, and the global edit on the complete board afterwards is too easiliy forgotten. I'm sure I'm missing something obvious, but haven't a clue Please help me out, guys.. There are two ways to force tenting on vias - or at least there are two places to control the solder mask expansion. The via has a tenting attribute and there is a design rule that controls solder mask expansion. I have no idea which has precedence, I would hope the tenting attribute of the via. However you may want to check, and play with, the Manufacturing-Solder Mask expansion rule. If you make the rule expansion ridiculously big do the auto-placed vias follow the silly expansion? Before we had the tenting attribute you had to apply a large enough negative expansion to force tenting. The checkbox being tented but the actual via being untented does sound very odd - unless there is a conflict between the rules and the tent attribute. Are the auto-placed vias the same dimensions as the manual placed vias? Are they both vias? The manual ones aren't free pads are they? (Just asking some possibly silly questions.) What happens if you save as ASCII and then re-load? What does the ASCII file show for a tented and untented via? The ASCII records are not hard to read. Not sure I have too many other ideas. Bye for now, Ian -- ___ Integrated Controls, Inc. Tel: 415-647-0480 EXT 107 2851 21st StreetFax: 415-647-3003 San Francisco, CA 94110 www.integratedcontrolsinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
[PEDA] German messages
Does anyone know what this message is about? I keep getting them when I post to this list. I replied in English (since I really don't speak German) and got the same reply. So I replied in Japanese--I figure if we are not going to communicate, it might as well involve two mutually unintelligible languages. Still no answer. Michael Badillo The text in question: Dies ist eine automatisch erstellte Benachrichtigung +APw-ber den Zustellstatus. +ANw-bermittlung an folgende Empf+AOQ-nger fehlgeschlagen. * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
