[PEDA] Internal plane problems

2002-12-10 Thread Afshin Salehi
Sirs,
I have noticed a problem when I route a multilayer board with an internal
power plane split up into different sections in 99SE.  When I setup an
internal plane then add split planes to it the auto router doesn't seem to
check if the via it placed into the board is actually going into the plane.
It seems like if the via is in the pcb the router considers its job done and
I have to find out when I run the DRC that it didn't connect to the plane it
was supposed to.  It feels like one of those problems where I am missing
something simple.  What would that simple thing be?  :)

Afshin Salehi
DPS Telecom

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Re: [PEDA] Mislabeled Nets

2002-06-22 Thread Afshin Salehi

Bernhard,
My problem arose on a smaller board, but my concern was on a bigger board.
What happens when I have a 15 page schematic, and a 10 x 10 inch board?  I
was trying to figure some automated method that could be used.  I read about
some DC simulation analysis in the Protel book, I was wondering if something
like that would be worth trying.

Afshin

p.s.  Thanks for all the responses to my question

-Original Message-
From: Bernhard Koss [mailto:[EMAIL PROTECTED]]
Sent: Thursday, June 20, 2002 5:49 PM
To: Protel EDA Forum
Subject: Re: [PEDA] Mislabeled Nets


I see an easier solution for your problem

In the PCB just use select connected copper and click on one ground-wire -
then u'll see if all gnd-nets are connected!

Bernhard


- Original Message -
From: Afshin Salehi [EMAIL PROTECTED]
To: Protel Forum [EMAIL PROTECTED]
Sent: Wednesday, June 19, 2002 3:14 PM
Subject: [PEDA] Mislabeled Nets


 Hello all,
 I have a problem that has plagued me for quite some time.  A lot of
 schematics I make will be for small test boards to verify a technology of
 some sort.  I copy and paste pieces of the schematic from other schematics
 that were created in the past.  When this is done sometimes the power nets
 are labeled like AGND and DGND and this is not seen, just the ground
symbol.
 An ERC check didn't reveal this since I had 2 of each type.  How can I
 reliably verify a schematic has the connectivity I think it does when I
view
 it, is there any kinds of simulation I can run?  How does anyone else
 overcome this problem?  I know that verifying a schematic with a
highlighter
 can't be the way this is done.  :)


 Afshin Salehi
 DPS Telecom


 
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[PEDA] Ground plane floods on top and bottom of PCB

2002-04-24 Thread Afshin Salehi

Hello all,
Currently on PCB's I flood the top and bottom layers with a ground plane
after routing.  I have it remove the dead copper then I manually place via's
where there was no flood to connect those area's to ground.  I then repour
the planes and continue this process until I am satisfied with the coverage.
This can't be the most efficient way.  Is anyone else doing something like
this that has a better way or a trick I am unaware of?  I look forward to
reading your replies.

Afshin Salehi
DPS Telecom


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[PEDA] Solder mask keepout

2002-02-14 Thread Afshin Salehi

Hello all,
I am having a problem trying to keep solder mask off of a polygon plane.  I
have a Ground plane that I would like to have no solder mask on in specific
area's.  I placed a keepout fill on those area's and the keepout is on the
Top solder mask layer.  I also have one in the same location on the bottom
solder mask layer.  When I view the gerbers in Camtastic the keepouts did
not do their job.  What am I missing?

Afshin Salehi
DPS Telecom

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[PEDA] Document Options

2002-02-04 Thread Afshin Salehi

Hi all,
Is it possible to change the Title, No. and Revision on a global basis
rather than sheet by sheet?  I have never seen a global setting for this but
I know that entering that data 20 times for a 20 sheet schematic can't be
what protel intended  :)

Afshin Salehi
DPS Telecom

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[PEDA] Via's to close to pads.

2002-01-31 Thread Afshin Salehi

Hey all,
I was looking over a board route of mine and noticed that there are a lot
of via's that are very close to pads which could bridge during soldering.
Is there any rule specifically to control via to pad distance.  I know the
clearance rule will move them away but it also makes the traces need a lot
more room as well which is not a possibility.

Afshin Salehi
DPS Telecom

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Re: [PEDA] Via's to close to pads.

2002-01-31 Thread Afshin Salehi

JaMi,
Yes, I have.  Thats how I take care of the problem currently.  It just
seems to me like there ought to be some way of controlling how close it
places the via's to pads.  Some SMT IC's have via's VERY close between two
pads, that just scares me.  :)

Afshin

-Original Message-
From: JaMi Smith [mailto:[EMAIL PROTECTED]]
Sent: Thursday, January 31, 2002 12:28 PM
To: Protel EDA Forum
Subject: Re: [PEDA] Via's to close to pads.


Afshin,

Have you considered tenting your vias (covering them with solder
mask), which should eliminate the problem and bring it back into the
range of a standard clearance problem?

JaMi Smith
Optical Crossing

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[PEDA] SMT pad and routing

2002-01-25 Thread Afshin Salehi

Wow, you guys are goodWho needs protel tech support anyways   ;)

I have a question that has had me thinking every so often.  When the
autorouter connects traces to small smt pads of IC's it never goes straight
into the pad.  Instead it will go along the side of the pad and then turn
left or right and into the pad.  This looks like a potential problem to me,
and on top of that it just looks cheesy!  :)  I am not sure what the most
efficient method would be to solve this problem (hint, hint).  I look
forward to hearing your suggestions.

Afshin Salehi
DPS Telecom

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[PEDA] Solder mask over via's

2002-01-24 Thread Afshin Salehi

Hello all,
I was wondering how I could have solder mask placed over all the via's on
my PCB.  Is there a design rule for the via's that allow you to select
solder mask options?  I saw a design rule for via size but not solder mask.
All of my via's should be a different size than any pads so if it were
necessary I am sure I could select them all and do a global change if that
is the only way possible.  Some of my via's are placed so close to pads
after a route that I am afraid of bridging occurring when the PCB is
soldered.

Thanks to everyone for your continued help.

Afshin Salehi
DPS Telecom

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[PEDA] Autoplacer

2002-01-22 Thread Afshin Salehi

Hey everyone,
I was wondering if anyone has had any luck with the autoplace function?  I
have played with it myself but I have never had a lot of time to devote to
it.  Does it work? Does anyone use this?  If so for what type of placing is
it a good tool to use?

Thankyou for your help

Afshin Salehi
DPS Telecom

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[PEDA] On the SCH but not on the PCB

2002-01-17 Thread Afshin Salehi

Hello all,
I was wondering how I would go about placing a part on the schematic but
not have it appear on the PCB.  For example, I would have 3 resistors in
parallel labeled 100, 200, 300 and I would only want one of those three to
appear on the PCB when I updated it. Is there a way to set if a part is to
appear on the PCB or is that not possible?

Afshin Salehi
DPS Telecom

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[PEDA] Printing multiple pages

2001-11-30 Thread Afshin Salehi

Hello all,
I have a quick question.  Has anyone written a Client Basic program to
print multiple schematic sheets?  I have not seen a feature in Protel for
printing multiple files unless I overlooked it.

Thanks for the help
Afshin

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Re: [PEDA] Printing multiple pages

2001-11-30 Thread Afshin Salehi

WOW, guess I just had to ask the question to receive the answer.  I opened
up the print setup menu for the heck of it and saw a Batch Type drop down
menu.  I selected All Documents and guess what it printed...  :)  Its
amazing how some answers will come so quickly at times and take forever at
other times.

Afshin

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[PEDA] Split Internal Plane

2001-10-29 Thread Afshin Salehi
 


[PEDA] Pad with multiple holes surrounding it.

2001-09-18 Thread Afshin Salehi
 


[PEDA] Client Basic help

2001-07-18 Thread Afshin Salehi
 


[PEDA] Overlapping Pads

2001-05-07 Thread Afshin Salehi