Re: [PEDA] virtual shorts, the saga goes on
i should have said
1 mil or greater INTEGER grid instead of
'1 mil or greater grid'
Dennis Saputelli
Dennis Saputelli wrote:
>
> earlier i had reported the following
> (the saga continues):
>
> history
> i used virtual shorts without problems for > 1 year
> hundreds and hundreds of bds (turns out i was lucky)
>
> one day a bd shop calls and offers to increase some tiny gaps ("no,
> thanks!")
>
> later another shop 'fixes' them without calling, causing opens
> no big deal, a short run, blob a little solder
>
> i investigate and conclude that using gerber 2.3 i too *could*
> see a 1 mil gap that they were seeing, but not always (i.e. not in every
> VS instance)
>
> i conclude that the problem was that i had shifted the origin from pin 1
> to centroid in my VS part
> did some gerber viewing and shipped another one to yet another shop
> (it turns out this was almost the right conclusion)
>
> a quick glance at the bds and they look fine
> testing begins and then power which was running is lost to one section
> the gap blew out, it was only maybe 800mA going thru a pretty beefy VS
> pad part
>
> looking at the bd you could see what did not look like a gap but did
> look like a slight visual line in the solder plated pad
>
> looking at the gerbers there was in 2 of 6 VS cases a 1 mil gap
> (don't know how i missed that, i thought it was nailed)
> i guess those guys can etch pretty good (i think i will start doing 1/1
> bds!)
>
> new conclusion, this fix works i am pretty sure
> my original part had 60x75mil thruhole pads spaced at 75.005 mils apart
> (depending on the positioning the gerber rounding can be benign or not,
> this is why it always worked sometimes and sometimes worked other times)
>
> my new part has 60x74.995 mil pads spaced at 75 mils apart
> maybe this is what Lomax recomended from the outset and i just caused
> myself some grief, i don't know
>
> as long as the new part is placed on a 1 mil or greater grid i think the
> pads will always bleed together now
>
> i did a test at gerber 2.5 and camtastic still reports 0 gap between
> objects using their inspection query tool
> (which is as it should be since 2.5 is .01 mil resolution)
>
> another problem solved i hope!
> i am pursuing this because it is a very useful technique for certain
> situations
>
> you can steer the currents and control trace widths on an otherwise
> common 'net'
>
> i have made the schematic so that is not too messy by using a symbol
> that appears to be a wire but has pins at the opposite ends so the
> schematic reflects the intent
> it is not hard to read or as confusing as it would be if they appeared
> as 'jumpers'
>
> i have not tried the other technique he has described of using a
> mechanical layer to create the shorts since making this VS work seems
> more integral to me
>
> there is of course the option of drawing a trace at the end of the
> process and putting a wire in the schematic and sometimes this is the
> best choice for certain situations
>
> Dennis Saputelli
>
> --
> ___
> www.integratedcontrolsinc.comIntegrated Controls, Inc.
>tel: 415-647-04802851 21st Street
> fax: 415-647-3003San Francisco, CA 94110
--
___
www.integratedcontrolsinc.comIntegrated Controls, Inc.
tel: 415-647-04802851 21st Street
fax: 415-647-3003San Francisco, CA 94110
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Re: [PEDA] virtual shorts, the saga goes on
earlier i had reported the following
(the saga continues):
history
i used virtual shorts without problems for > 1 year
hundreds and hundreds of bds (turns out i was lucky)
one day a bd shop calls and offers to increase some tiny gaps ("no,
thanks!")
later another shop 'fixes' them without calling, causing opens
no big deal, a short run, blob a little solder
i investigate and conclude that using gerber 2.3 i too *could*
see a 1 mil gap that they were seeing, but not always (i.e. not in every
VS instance)
i conclude that the problem was that i had shifted the origin from pin 1
to centroid in my VS part
did some gerber viewing and shipped another one to yet another shop
(it turns out this was almost the right conclusion)
a quick glance at the bds and they look fine
testing begins and then power which was running is lost to one section
the gap blew out, it was only maybe 800mA going thru a pretty beefy VS
pad part
looking at the bd you could see what did not look like a gap but did
look like a slight visual line in the solder plated pad
looking at the gerbers there was in 2 of 6 VS cases a 1 mil gap
(don't know how i missed that, i thought it was nailed)
i guess those guys can etch pretty good (i think i will start doing 1/1
bds!)
new conclusion, this fix works i am pretty sure
my original part had 60x75mil thruhole pads spaced at 75.005 mils apart
(depending on the positioning the gerber rounding can be benign or not,
this is why it always worked sometimes and sometimes worked other times)
my new part has 60x74.995 mil pads spaced at 75 mils apart
maybe this is what Lomax recomended from the outset and i just caused
myself some grief, i don't know
as long as the new part is placed on a 1 mil or greater grid i think the
pads will always bleed together now
i did a test at gerber 2.5 and camtastic still reports 0 gap between
objects using their inspection query tool
(which is as it should be since 2.5 is .01 mil resolution)
another problem solved i hope!
i am pursuing this because it is a very useful technique for certain
situations
you can steer the currents and control trace widths on an otherwise
common 'net'
i have made the schematic so that is not too messy by using a symbol
that appears to be a wire but has pins at the opposite ends so the
schematic reflects the intent
it is not hard to read or as confusing as it would be if they appeared
as 'jumpers'
i have not tried the other technique he has described of using a
mechanical layer to create the shorts since making this VS work seems
more integral to me
there is of course the option of drawing a trace at the end of the
process and putting a wire in the schematic and sometimes this is the
best choice for certain situations
Dennis Saputelli
--
___
www.integratedcontrolsinc.comIntegrated Controls, Inc.
tel: 415-647-04802851 21st Street
fax: 415-647-3003San Francisco, CA 94110
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Re: [PEDA] Virtual Shorts
At 11:27 AM 9/25/01 -0400, you wrote: >Hey, Abdul, your message had the full text of the original thread in it. I >thought you were the one who advocated not doing that! ;-) Certainly I have. Do as I say, not as I do :-) Seriously, I did not quote the "full text," the boilerplate at the end was cut. I normally leave enough of the original post for my response to have some context; if the original post is short, as it was in this case, I may leave all of it. In this case I probably left a little too much, looking back, especially with the levels of nesting. Sometimes I might simply overlook the quoted text if I inserted text and the quotation was off-screen as a result of my editing process. I try to be careful not to do that Abd ul-Rahman Lomax LOMAX DESIGN ASSOCIATES PCB design, consulting, and training Protel EDA license resales Easthampton, Massachusetts, USA (413) 282-0013, efax (419) 730-4777 [EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Virtual Shorts
Edi I've used land patterns that look like two semi circles separated by 7-8 mils for test and debug shunts. These 2 pad footprints needed to be this far apart so that it was easy to remove the bridge when required. They are a little hard to manage because they are made of 2 pads 40mil round, 2 arcs 8mil wide 25mil radius, and 2 tracks 14mil wide forming the flat sides of the semicircles. These primitives need to be cut then pasted to get nets assigned to them because the net list only includes the pads. I have not tried process soldering but it should be possible. If I were trying to connect them in IR reflow I would make an oversize paste mask openning, then the surface tension of the semi circles should force it to bridge. I am always working with contract assembly houses and processes vary. Good luck Dave E -Original Message- From: Edi Im Hof [mailto:[EMAIL PROTECTED]] Sent: Tuesday, September 25, 2001 1:24 AM To: Protel EDA Forum Subject: Re: [PEDA] Virtual Shorts At 11:47 24.09.01 -0700, you wrote: >At 08:21 AM 9/24/01 -0500, Mark E Witherite wrote: >> The issue with the virtual short is that it must be cut to test >> the two nets. Has somebody tried to make the virtual short not virtual but real? I mean, put it on the _solder_ side with a small gap (4..8mil) and let is solder together on the solder wave. Or put it on the top side and expose both pads and the gap on the top paste mask layer and solder it on the reflow process. Does one of this works reliable? This would allow to test the bare board and connect them with no additional costs. Edi * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Virtual Shorts
> I tried "virtual" shorts once but they were too drafty ; ) In the 80's I used to work in the service dept. of a traffic equipment maker. We had to repair new equipment that had plenty of "real" shorts caused by faulty etching of PCBs (electrical test? - we didn't need no stinkin' electrical test). Sometimes the copper short was so small you could not see it. So we would charge up a big capacitor with < 5V and use the stored energy to evaporate the copper short. This technique was referred to as "blow out your shorts". 8^) Yes, it did work (most of the time). As long as we didn't reverse bias the chips... Best regards, Ivan Baggett Bagotronix Inc. website: www.bagotronix.com - Original Message - From: "Greg Olson" <[EMAIL PROTECTED]> To: "Protel EDA Forum" <[EMAIL PROTECTED]> Sent: Tuesday, September 25, 2001 11:31 AM Subject: Re: [PEDA] Virtual Shorts > I tried "virtual" shorts once but they were too drafty ; ) > > (sorry, I couldn't resist!) > > - Original Message - > From: "Abd ul-Rahman Lomax" <[EMAIL PROTECTED]> > To: "Protel EDA Forum" <[EMAIL PROTECTED]> > Sent: Tuesday, September 25, 2001 1:19 PM > Subject: Re: [PEDA] Virtual Shorts > > > > At 08:23 AM 9/25/01 +0200, Edi Im Hof wrote: > > >At 11:47 24.09.01 -0700, you wrote: > > >>At 08:21 AM 9/24/01 -0500, Mark E Witherite wrote: > > >>> The issue with the virtual short is that it must be cut to > test > > >>> the two nets. > > > > > >Has somebody tried to make the virtual short not virtual but real? > * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Virtual Shorts
> Otherwise a zero-ohm resistor is very cheap, requires no special process or > attention, and has other advantages with regard to potential modifications > of the short character to add resistance or inductance. We use zero-ohm resistors for jumpers too. It eliminates second guessing by all parties involved (engineering, fab house, boards stuffers, etc.). Copper is free if you already paid for it, but grief costs... Hey, Abdul, your message had the full text of the original thread in it. I thought you were the one who advocated not doing that! ;-) Best regards, Ivan Baggett Bagotronix Inc. website: www.bagotronix.com - Original Message - From: "Abd ul-Rahman Lomax" <[EMAIL PROTECTED]> To: "Protel EDA Forum" <[EMAIL PROTECTED]> Sent: Tuesday, September 25, 2001 2:19 PM Subject: Re: [PEDA] Virtual Shorts * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Virtual Shorts
I tried "virtual" shorts once but they were too drafty ; ) (sorry, I couldn't resist!) - Original Message - From: "Abd ul-Rahman Lomax" <[EMAIL PROTECTED]> To: "Protel EDA Forum" <[EMAIL PROTECTED]> Sent: Tuesday, September 25, 2001 1:19 PM Subject: Re: [PEDA] Virtual Shorts > At 08:23 AM 9/25/01 +0200, Edi Im Hof wrote: > >At 11:47 24.09.01 -0700, you wrote: > >>At 08:21 AM 9/24/01 -0500, Mark E Witherite wrote: > >>> The issue with the virtual short is that it must be cut to test > >>> the two nets. > > > >Has somebody tried to make the virtual short not virtual but real? * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Virtual Shorts
At 08:23 AM 9/25/01 +0200, Edi Im Hof wrote: >At 11:47 24.09.01 -0700, you wrote: >>At 08:21 AM 9/24/01 -0500, Mark E Witherite wrote: >>> The issue with the virtual short is that it must be cut to test >>> the two nets. > >Has somebody tried to make the virtual short not virtual but real? >I mean, put it on the _solder_ side with a small gap (4..8mil) and let is >solder together on the solder wave. Or put it on the top side and expose >both pads and the gap on the top paste mask layer and solder it on the >reflow process. > >Does one of this works reliable? > >This would allow to test the bare board and connect them with no >additional costs. Well, the original virtual short depended on (1) the gap being much smaller than the film resolution, (2) being much smaller than what can be fabricated. If a gap makes it through the first two obstacles, it is because, somehow, incorrect apertures were used (and Protel behavior in aperture matching is not thoroughly tested to my knowledge, or, at least, how it behaves is not documented for us as far as I know). The most likely cause of incorrect aperture usage would be a fabricator who notices the two flashes adjacent to each other and who assumes that a gap was intended; thus he or she modifies the film to make it a larger gap. However, if a relatively large gap were used in the first place, it would need to be a gap that can reliably be fabricated; exactly how large would depend on process, but 4 mils might still be too small, or the fabricator might need to adjust the process, adding cost. 7 mils or more should not add cost. A 5 mil gap with no mask between may well short in the wave; in reflow I don't know; I would not trust it to short. Why should it? Someone with more recent practical experience may provide better information. If a board was for high production and was very cost-sensitive, or space was *very* tight such that even a very small resistor would be a problem, it might be worthwhile to work out the process parameters and follow what Mr. Im Hof suggested. Wave solder direction might be critical, for example. Otherwise a zero-ohm resistor is very cheap, requires no special process or attention, and has other advantages with regard to potential modifications of the short character to add resistance or inductance. [EMAIL PROTECTED] Abdulrahman Lomax Easthampton, Massachusetts USA * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Virtual Shorts
At 11:47 24.09.01 -0700, you wrote: >At 08:21 AM 9/24/01 -0500, Mark E Witherite wrote: >> The issue with the virtual short is that it must be cut to test >> the two nets. Has somebody tried to make the virtual short not virtual but real? I mean, put it on the _solder_ side with a small gap (4..8mil) and let is solder together on the solder wave. Or put it on the top side and expose both pads and the gap on the top paste mask layer and solder it on the reflow process. Does one of this works reliable? This would allow to test the bare board and connect them with no additional costs. Edi * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Virtual Shorts
At 08:21 AM 9/24/01 -0500, Mark E Witherite wrote: > The issue with the virtual short is that it must be cut to test > the two nets. Right. And if you know you are going to cut it, and especially if you are going to cut it before assembly, it is desireable to fabricate it "cut," i.e., open, i.e., it is a simple jumper or zero-ohm resistor instead of a virtual short. For those who might be popping into this discussion late, a "virtual short" is a footprint which is made such that Protel sees it as two or more separate and non-connected pads, does not generate a DRC error, and yet it fabricates as a short. There are several methods for doing this, they have been detailed elsewhere. On the schematic, a jumper is placed between the nets to be shorted. So, from a schematic point of view, there is no difference between a virtual short and a jumper. A virtual short may easily be made in such a way as to be easily severable, should this be necessary. So the decision as to whether or not to use a virtual short or a jumper/zero-ohm resistor depends on what one wants for the as-fabricated default. It is *not* recommended to generate a single ground net for otherwise-isolated single-point grounds. The reason for this is as Mr. Witherite explained: there will be no easy way to discover additional connecting points, nor is there any control over where the connection is made, which can also be crucial. DRC won't care. Using a component to accomplish the connection forces a single-point connection and makes it simple to control the location of that connection. An additional advantage is that one may sever the connection in trouble-shooting the board; in development, one can also test the effect of putting resistance or inductance into the connection; if the footprint has been properly chosen, one can change the nature of the connection from a direct short to a resistor or an inductor without requiring any revision to the artwork. [EMAIL PROTECTED] Abdulrahman Lomax Easthampton, Massachusetts USA * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Virtual Shorts
Re: [PEDA] Virtual Shorts
I was wondering, Mark, was the issue that you wanted to test the nets before assembly? Or was it just in case of problems after assembly? For the second case, you might use a virtual short on the top or bottom layers, which could be cut if need be. -Original Message- From: Mark E Witherite [mailto:[EMAIL PROTECTED]] Sent: Friday, September 21, 2001 2:35 PM Hi I was going to let the group how I made out with the virtual short I was planing on using on my internal planes. After a short discussion We decided not to do it. Our main concern was there was no way to test the PCB to be sure that the nets were tied at one and only one place. We when with the zero ohm resistor. Cheers Mark * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Virtual Shorts
At 04:34 PM 9/21/01 -0500, Mark E Witherite wrote: >I was going to let the group how I made out with the virtual short I was >planing on using on my internal planes. After a short discussion We >decided not to do it. Our main concern was there was no way to test the >PCB to be sure that the nets were tied at one and only one place. We when >with the zero ohm resistor. Right, or any kind of jumper. A zero-ohm resistor is very cheap and can be machine assembled. The virtual short is, schematically, the same thing, but is to be used where one wants the short to be implemented without further assembly. No question, it presents a testing problem, for a short somewhere else may cause very subtle problems, the proverbial system failure when the police outside use their radar gun, the once in 4 trillion operations glitch, etc. But there are ways to test such a thing, it is just, I think, not practical, much easier to guarantee a single point of connection by forcing it in assembly not in board fab. [EMAIL PROTECTED] Abdulrahman Lomax Easthampton, Massachusetts USA * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Virtual Shorts
Re: [PEDA] Virtual Shorts
At 05:40 PM 9/3/01 +1000, Don Ingram wrote: >Just got PCB Fab Magazine & noticed that they are running 10 micron wide >traces. > >Better make the virtual shorts way less than the customary 1mil The "customary" gap for virtual shorts based on unfabricatable gaps is on the order of 4 micro-inches, which is already 250 times smaller than 1 mil. There are numerous barriers in the way of the appearance of an actual gap; the greatest hazard is that the fabricator sees the microgap and enlarges it, thinking that it was intended to be larger. For this reason using a mech layer overlay to implement the short may be superior. However, I think, with proper photoplot settings the gap should not make it into the gerbers, so fabrication accuracy would be irrelevant. [EMAIL PROTECTED] Abdulrahman Lomax Easthampton, Massachusetts USA * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] Virtual Shorts
I'm *wearing* my virtual shorts right now good thing this is radio and not television -chris -Original Message- From: Don Ingram [mailto:[EMAIL PROTECTED]] Sent: Monday, September 03, 2001 3:41 AM To: Protel EDA Forum Subject: [PEDA] Virtual Shorts Just got PCB Fab Magazine & noticed that they are running 10 micron wide traces. Better make the virtual shorts way less than the customary 1mil heh heh heh Cheers Don Ingram [EMAIL PROTECTED] Ph +61 7 4954 6074UTC+10hrs Fx +61 7 4954 6222 - Original Message - From: Abd ul-Rahman Lomax <[EMAIL PROTECTED]> To: Protel EDA Forum <[EMAIL PROTECTED]> Sent: Saturday, September 01, 2001 7:09 AM Subject: Re: [PEDA] Isolated "Island" on PCB > At 06:16 PM 8/30/01 -0500, Nicholas Cobb wrote: > > I am making a board that has internal power and ground planes and > > I would > >like to make an island that is isolated from all layers on my board. I have > >made a split plane of both the power and ground to have the isolated +5, and > >isolated gnd. I just don't know how to keep the gnd and +5 plane from > >invading. I have outlined my "island" with traces on the keepout layer. > > The keepout layer has no effect on negative layers! > > The most reliable way to accomplish what is desired is to ensure that the > isolated net has a *different* net name. This, of course, would normally be > done on the schematic. If you don't want nets connected, don't give them > the same name! > > If we want a single-point ground, there are a number of ways to accomplish > this. > > 1. If the nets are *not* distinctly named and you want to leave it that way > (not recommended), place primitives (such as lines) on the negative layer > to create isolating anti-copper. Leave a gap in the isolating outline. This > will *not* be DRC'd. > > 2. Use an ordinary jumper placed on the schematic; it has one net on one > side and the other net or nets on the other side(s). The jumper is shorted > in production. This method has an advantage that one can tinker with the > isolation, placing, for example, a resistor or an inductor between the > areas. We can place track to short the jumper on production boards, if that > is what we want. But this will produce a DRC error because of the short. I > dislike this, because it encourages me to disregard a DRC error, a bad > habit to develop. > > 3. Use a Virtual Short, which is a footprint used for the jumper which > appears to be isolated to DRC but is actually shorted in production, either > because the gap between the two sides is *very* small (like 2 microinches) > and thus disappears in real-world production, or the sides are shorted *in > the footprint* using a non-copper mech layer assigned for this purpose. > That layer is plotted with the jumper on all relevant layers (this is set > up in the CAM Manager, where we can have different CAM setups for different > layers). The first kind of Virtual Short is described in the user FAQ in > the filespace for [EMAIL PROTECTED] > > I've assumed that Mr. Cobb does not want "an island isolated from all > layers." Rather he wants this island to have its own unique net, or he > wants to isolate sections of +5 and gnd. If he truly wants isolation from > all layers, he can place primitives on all negative layers (such as lines > or fills) to blow out the section. > > [EMAIL PROTECTED] > Abdulrahman Lomax > P.O. Box 690 > El Verano, CA 95433 > * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/proteledaforum@techservinc.com * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
