AAGHH!!!
All of a sudden, I've discovered that if I select a single component and
then either Cut or Copy it, and then paste it (or paste an array of them),
Protel (99SE sp6) locks up completely and the status bar just says
'processing pasted primitives'.
This is not repeatable on
In addition - Upon further investigation, it appears that it only happens on
certain library components. I tried it on a testpoint of ours - crash. I
then tried it on a resistor (also from our own library) - it works... *sob*
;)
-Original Message-
From: Terry Creer
Sent: Thursday, 28
Is it only one particular part or does it happen if you select any type of
component?
What about a part from a different library?
-Original Message-
From: Terry Creer [mailto:[EMAIL PROTECTED]]
Sent: Thursday, 28 November 2002 12:35
To: Protel EDA Forum (E-mail)
Subject: [PEDA]
i doubt it is W2K
i have seen it on a few occasions
it went away somehow
are you pasting into the same document as cutting/copying?
when i cut/copy from one doc into another i have learned not to close
the first one until later, after the paste
i think they improved this somewhere along the way
Have you tried repairing the database that contains the library?
Server menu (arrow left of File)/Design Utilities/Repair
-Original Message-
From: Terry Creer [mailto:[EMAIL PROTECTED]]
Sent: Thursday, 28 November 2002 12:40
To: 'Protel EDA Forum'
Subject: Re: [PEDA] Simple (?)
Terry,
you might have some hidden objects in your components. That would explain why Protel
takes time to process it. Or your component may be corrupted in some other way. Try to
select all the visible objects in the component and then copy-paste to a new
component. Then check if it still does
Another data point:
When I just create a netlist, there are duplicate nets with the same name
formed - the solution here is obviously to generate only one net with that
name, and append the new nodes to the existing net. Is there an easy way of
doing this, since I'll have to do it numerous times
At 12:36 PM 28/11/02 +1000, you wrote:
Hi all:
I usually use a hierarchical structure for my schematic documents, with a
main document with all the connectors on it, then below that a block
diagram, and then the actual circuitry on one or more levels below that.
I'm currently doing a
Forgive me if you already know this:
If any buss connects to a port make sure the busses have net labels.
For example an 8 way buss with lines D0 to D7 connected to a port needs a
net label [D0..D7] without the quotes placed on it for connectivity also
the port must have the same name (that is
Do you have Descend into sheet parts ticked when running the synchroniser?
-Original Message-
From: [EMAIL PROTECTED] [mailto:[EMAIL PROTECTED]]
Sent: Thursday, 28 November 2002 14:21
To: Protel EDA Forum
Subject: Re: [PEDA] Connectivity Nightmares
At 12:36 PM 28/11/02
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