Forum
Subject: Re: [PEDA] Schematic hetero capabilities?
Hello all,
Wednesday, October 24, 2001 12:58 PM Douglas McDonald wrote:
> I've seen a mechanism for achieving this recently on another tool. You can
> add run-time attributes to each gate such as "GROUP=FPGA1" and then duri
Hello all,
Wednesday, October 24, 2001 12:58 PM Douglas McDonald wrote:
> I've seen a mechanism for achieving this recently on another tool. You can
> add run-time attributes to each gate such as "GROUP=FPGA1" and then during
> annotation only parts with compatible attributes can/will be put to
D]>
>Reply-To: "Protel EDA Forum" <[EMAIL PROTECTED]>
>To: "Protel EDA Forum" <[EMAIL PROTECTED]>
>Subject: Re: [PEDA] Schematic hetero capabilities?
>Date: Tue, 23 Oct 2001 23:02:28 +0200
>
>At 13:42 23.10.01 -0700, you wrote:
>>The problem
ation pass (of all '?' designators)will not
swap them around. Back annotation from a re-annotated board will not cause
any problems.
regards,
Phil.
-Original Message-
From: Cliff Ober [mailto:[EMAIL PROTECTED]]
Sent: Wednesday, 24 October 2001 4:12 AM
To: Protel EDA Forum
Subje
>
>-Original Message-
>From: Peter Bennett [mailto:[EMAIL PROTECTED]]
>Sent: Tuesday, October 23, 2001 1:18 PM
>To: Protel EDA Forum
>Subject: Re: [PEDA] Schematic hetero capabilities?
>
>
>Cliff Ober wrote:
> >
> > I'm working with some l
Systems, Inc.
-Original Message-
From: Peter Bennett [mailto:[EMAIL PROTECTED]]
Sent: Tuesday, October 23, 2001 1:18 PM
To: Protel EDA Forum
Subject: Re: [PEDA] Schematic hetero capabilities?
Cliff Ober wrote:
>
> I'm working with some large devices (>500 pins), and I&#
Cliff Ober wrote:
>
> I'm working with some large devices (>500 pins), and I'm interested in
> representing the schematic symbols as hetero type devices (split
> representations of the parts into logical blocks). Is there any efficient
> way to do this in '99SE? I don't seem to find any referenc
I'm working with some large devices (>500 pins), and I'm interested in
representing the schematic symbols as hetero type devices (split
representations of the parts into logical blocks). Is there any efficient
way to do this in '99SE? I don't seem to find any references to this in the
help or use
