Re: [PEDA] P99SE drc
Graham Brown wrote: Hi all, merry Christmas, I have a board with an internal plane split between +5v and +30v. I inadvertently placed a via, belonging to the 30v net, right on the separating line, thereby bridging the two power nets. P99SE/SP6 did not find this during drc. Is this a limitation of Protel or of my menu-digging skills? It appears to be a bug. I've just been lucky and not had a board go out for fab with one of these, yet. If the via is totally in the wrong split plane region, it will usually cause a reliable DRC error. Sometimes, I think, it will still cause an error, depending on the exact placement of the via. Note that many board manufacturers add additional "blowout" around the plane regions and non-connecting through holes toimprove their yield. This is more likely to cause thin areas in planes to become isolated, or cause a single split plane to end up as two regions. But, in any case, Protel is not aware of that modification, and can't predict the results when the fabricator does that expansion. It is a pretty good idea to import the Gerbers and view them one at a time (you can gang import them and then use shift-S to see the layers individually). If you scan along the split plane boundaries, any thermal connection will be pretty obvious. Any via (or pad) that doesn't connect to either plane should have a blowout pad that just makes the gap between the plane regions bigger at that spot, so those shouldn't be a problem even if right on the boundary. But, you say your problem was a via. That normally would not have a thermal connection, just a hole drilled into the plane. If you make the border line of the planes larger than the hole diameter, then you should not get a short between planes. (You'd get a no-connect for a via centered in the gap between planes. That would at least be easier to fix.) But, this is also not easy to spot in the Gerbers, as the direct plane connects do not show at all in single layer view. I suppose you could select the power layer as the current layer, and enable only the power layer and the multilayer, display vias only, and check the borders manually. But, I think making the split plane boundary track width wider than any reasonable through hole is the best policy, and how I always do things. If both boundary tracks are .020" wide, and you don't overlap them much, you should be pretty safe. Jon * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] P99SE drc
IMO, this is a BUG in 99SE. This has happened to me before, and fortunately, I noticed it before having the boards made. No, DRC will NOT find it. I ended up not using split planes, and added another plane instead. BTW, the 99SE autorouter will automatically make the same mistake, that is, placing a via in the wrong net area or bridging a split. And the DRC will NOT find that either. Workaround: if manual routing, check it yourself. If autorouting, do not use split planes. Best regards, Ivan Baggett Bagotronix Inc. website: www.bagotronix.com - Original Message - From: "Graham Brown" <[EMAIL PROTECTED]> To: <[EMAIL PROTECTED]> Sent: Tuesday, December 23, 2003 8:04 PM Subject: [PEDA] P99SE drc > Hi all, merry Christmas, > > I have a board with an internal plane split between +5v and +30v. I > inadvertently placed a via, belonging to the 30v net, right on the > separating line, thereby bridging the two power nets. P99SE/SP6 did not > find this during drc. Is this a limitation of Protel or of my > menu-digging skills? > > Graham Brown > > > * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] P99SE drc
To show you, go to this directory http://www.encoreelectronics.com/99SE/ and download the zip file. It is a compressed DDB file. When you open the DDB in 99SE, go find pad 13. (They are all free pads and vias) You'll see how it draws the plane connection relief. You can play around with the thickness of the split lines and if they are thin enough but slightly larger than the drill hole size, it will look like it's shorting both nets on the split plane. It's not. What really happens with it is that it connects to neither! Look at the gerber files to see what I mean. I made the split thicker to make it obvious that it can't connect to either side of the split. If you go view the gerber read back board, you'll see. This is not caught by 99SE DRC. It's burned me in the past and I knew to look for things on top of the split line. In DXP, this is now caught as a warning about things touching the plane splitting primitives, BUT it also indicates (IMHO incorrectly) that the nets are broken when I believe only 1 of them is broken. This is the DRC report from DXP: WARNING: Via(s)/Pad(s) touching plane splitting primitives on following planes: Pad Free-13(1688mil,1830mil) MultiLayer: Power Plane Via (1680mil,1600mil) Component Side to Solder Side: Power Plane Via (1760mil,1760mil) Component Side to Solder Side: Power Plane Processing Rule : Hole Size Constraint (Min=1mil) (Max=100mil) (All) Rule Violations :0 Processing Rule : Width Constraint (Min=10mil) (Max=10mil) (Preferred=10mil) (All) Rule Violations :0 Processing Rule : Clearance Constraint (Gap=10mil) (All),(All) Rule Violations :0 Processing Rule : Broken-Net Constraint ( (All) ) Violation Net Net2 Warning - Pad/Via touching plane splitting primitives Violation Net +30V Warning - Pad/Via touching plane splitting primitives Violation Net +5V is broken into 2 sub-nets. Routed To 0.00% Subnet : Subnet : Rule Violations :3 I believe the VIA "+30V" is not an error because it is connected to the net using a component side trace. I also believe the VIA "Net2" is not an error because it is connected to the net using a component and solder side traces and is not affect by the plane splitting primitives because it has nothing to do with the plane splitting primitives and when it's plated it will be normal. > -Original Message- > From: Tony Karavidas [mailto:[EMAIL PROTECTED] > Sent: Tuesday, December 23, 2003 6:28 PM > To: 'Protel EDA Forum' > Subject: Re: [PEDA] P99SE drc > > Are you positive it shorted them or did it not connect to > either one? The planes are negative, so if you see a full > circle for that via on the plane, it isn't connected to anything. > > There is a similar bug related to the split plane and a node > that lands in the split will not be reported as a disconnect > from the net. This will get you because that node is just > floating when it should be tied to one side of the split plane. > > Tony > > > -Original Message- > > From: Graham Brown [mailto:[EMAIL PROTECTED] > > Sent: Tuesday, December 23, 2003 5:05 PM > > To: [EMAIL PROTECTED] > > Subject: [PEDA] P99SE drc > > > > Hi all, merry Christmas, > > > > I have a board with an internal plane split between +5v and > > +30v. I inadvertently placed a via, belonging to the 30v > > net, right on the separating line, thereby bridging the two power > > nets. P99SE/SP6 did not find this during drc. Is this a > limitation of > > Protel or of my menu-digging skills? > > > > Graham Brown > > > > > > > > > > > > * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] P99SE drc
Are you positive it shorted them or did it not connect to either one? The planes are negative, so if you see a full circle for that via on the plane, it isn't connected to anything. There is a similar bug related to the split plane and a node that lands in the split will not be reported as a disconnect from the net. This will get you because that node is just floating when it should be tied to one side of the split plane. Tony > -Original Message- > From: Graham Brown [mailto:[EMAIL PROTECTED] > Sent: Tuesday, December 23, 2003 5:05 PM > To: [EMAIL PROTECTED] > Subject: [PEDA] P99SE drc > > Hi all, merry Christmas, > > I have a board with an internal plane split between +5v and > +30v. I inadvertently placed a via, belonging to the 30v > net, right on the separating line, thereby bridging the two > power nets. P99SE/SP6 did not find this during drc. Is this a > limitation of Protel or of my menu-digging skills? > > Graham Brown > > > > * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Re: [PEDA] P99SE drc
Graham, I don't exactly know the answer to your question, but I never use split plains. Instead I use polygons for plains which are "positive" instead of "negative". I never really understood the purpose of the plain function which I find much more difficult to interpert. If I had dropped a via between two polygon boundaries, I definitely would have generated a DRC error just based on a simple clearance rule. Dave At 05:04 PM 12/23/2003 -0800, Graham Brown wrote: Hi all, merry Christmas, I have a board with an internal plane split between +5v and +30v. I inadvertently placed a via, belonging to the 30v net, right on the separating line, thereby bridging the two power nets. P99SE/SP6 did not find this during drc. Is this a limitation of Protel or of my menu-digging skills? Graham Brown +-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-+ | David PalomboTelephone: (818) 597-8915 x101 | Aveox Inc. Fax:(818) 597-0617 | 31324 Via Colinas, #104 e-mail: [EMAIL PROTECTED] | Westlake Village, Ca 91362 http://www.aveox.com +-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-+ * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * To post a message: mailto:[EMAIL PROTECTED] * * To leave this list visit: * http://www.techservinc.com/protelusers/leave.html * * Contact the list manager: * mailto:[EMAIL PROTECTED] * * Forum Guidelines Rules: * http://www.techservinc.com/protelusers/forumrules.html * * Browse or Search previous postings: * http://www.mail-archive.com/[EMAIL PROTECTED] * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
