To show you, go to this directory http://www.encoreelectronics.com/99SE/ and
download the zip file. It is a compressed DDB file. When you open the DDB in
99SE, go find pad 13. (They are all free pads and vias) You'll see how it
draws the plane connection relief.

You can play around with the thickness of the split lines and if they are
thin enough but slightly larger than the drill hole size, it will look like
it's shorting both nets on the split plane. It's not. What really happens
with it is that it connects to neither! Look at the gerber files to see what
I mean. I made the split thicker to make it obvious that it can't connect to
either side of the split. If you go view the gerber read back board, you'll
see.

This is not caught by 99SE DRC. It's burned me in the past and I knew to
look for things on top of the split line.

In DXP, this is now caught as a warning about things touching the plane
splitting primitives, BUT it also indicates (IMHO incorrectly) that the nets
are broken when I believe only 1 of them is broken.

This is the DRC report from DXP:


WARNING: Via(s)/Pad(s) touching plane splitting primitives on following
planes:
       Pad Free-13(1688mil,1830mil)  MultiLayer:
              Power Plane

       Via (1680mil,1600mil) Component Side to Solder Side:
              Power Plane

       Via (1760mil,1760mil) Component Side to Solder Side:
              Power Plane

Processing Rule : Hole Size Constraint (Min=1mil) (Max=100mil) (All)
Rule Violations :0

Processing Rule : Width Constraint (Min=10mil) (Max=10mil) (Preferred=10mil)
(All)
Rule Violations :0

Processing Rule : Clearance Constraint (Gap=10mil) (All),(All)
Rule Violations :0

Processing Rule : Broken-Net Constraint ( (All) )
   Violation         Net Net2
     Warning - Pad/Via touching plane splitting primitives
   Violation         Net +30V
     Warning - Pad/Via touching plane splitting primitives
   Violation         Net +5V   is broken into 2 sub-nets. Routed To 0.00%
     Subnet :
     Subnet :
Rule Violations :3



I believe the VIA "+30V" is not an error because it is connected to the net
using a component side trace.
I also believe the VIA "Net2" is not an error because it is connected to the
net using a component and solder side traces and is not affect by the plane
splitting primitives because it has nothing to do with the plane splitting
primitives and when it's plated it will be normal.









> -----Original Message-----
> From: Tony Karavidas [mailto:[EMAIL PROTECTED] 
> Sent: Tuesday, December 23, 2003 6:28 PM
> To: 'Protel EDA Forum'
> Subject: Re: [PEDA] P99SE drc
> 
> Are you positive it shorted them or did it not connect to 
> either one? The planes are negative, so if you see a full 
> circle for that via on the plane, it isn't connected to anything.
> 
> There is a similar bug related to the split plane and a node 
> that lands in the split will not be reported as a disconnect 
> from the net. This will get you because that node is just 
> floating when it should be tied to one side of the split plane. 
> 
> Tony
> 
> > -----Original Message-----
> > From: Graham Brown [mailto:[EMAIL PROTECTED]
> > Sent: Tuesday, December 23, 2003 5:05 PM
> > To: [EMAIL PROTECTED]
> > Subject: [PEDA] P99SE drc
> > 
> > Hi all, merry Christmas,
> > 
> > I have a board with an internal plane split between +5v and
> > +30v.  I inadvertently placed a via, belonging to the 30v
> > net, right on the separating line, thereby bridging the two power 
> > nets. P99SE/SP6 did not find this during drc. Is this a 
> limitation of 
> > Protel or of my menu-digging skills?
> > 
> > Graham Brown
> > 
> > 
> > 
> > 
> 
> 
> 
> 



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