Hello,
I need to decode SPI from a .sr file on command line.
I use this command line:
sigrok-cli -i test.sr -P spi:wordsize=8:cs=2:clk=0:mosi=1:miso=3 -A
spi=miso-transfer,mosi-transfer
and I get an output like this (I left only the first bytes of the
transactions that are normally 279 bytes lon
Hi
I have the same problem, i be able to use kings la5016 witch ubuntu but
witch windows 10
i get this message
sr: [01:53.204000] kingst-la2016: Manufacture date: 2022-12.
sr: [01:53.207000] kingst-la2016: EEPROM magic bytes 0c f3 00 00 0c f3 10
ef.
sr: [01:53.208000] kingst-la2016: Using seconda
Hi!
(apologies if this is a dupe, it looks like the first one got eaten)
I've just written a new driver for the programmable powersupplies sold by
RDTech on aliexpress and the branch is available at
https://github.com/pelrun/libsigrok/tree/rdtech.
They use Modbus RTU over USB or BT serial, and
Hi, all
> > Wouldn't it be better to invest more time in support for existing
> > logic analyzers? Features like memory compression support for
> > pulseview would help the project a lot more in my opinion.
>
> No, because frankly, what's currently out there is crap.
New user here. not sure if my
Chris Obbard wrote:
> > Heck, Cypress even has a datapump
> > demo firmware for the FX3 written already. It's all there.
> >
> > https://github.com/esden/bitmagic is what I'm betting on because he
> > has commercial interest. It's obvious that such a design will be
> > cloned by Chinese vendors,
stall is very out-of-date so this
feature may have already been added; I plan to update when I finish setting up
my new laptop.
From: Soeren Apel
Sent: Friday, January 26, 2018 3:22 AM
To: Vlad Ivanov; Chris Obbard
Cc: sigrok-devel@lists.sourceforg
> Using an FPGA as a front-end and RAM interface to shovel the data
> into, then pushing the data over a slow serial (UART or USB2)
> interface into the PC when the RAM is full and acquisition has stopped
> is a concept that worked well for years but it's totally outdated
> now.
But still, for ho
I wouldn't recommend this LA to anyone. I bought this almost 2 years ago
and tried to get access to the information needed to add the support
without success. There is a thread on the mailing list about this.
The specs are nice on papers, but have had crashes on their latest app
version on w
For what it's worth, I recently purchased an Asix Omega and it seems to be
a pretty decent bit of kit. I've not pushed it to the limit, but so far it
does what it says on the tin. Only criticism of the hardware would be that,
for the price, I found the quality of the supplied probes a bit wanting
(
> Nah... 90% of the work is *proving* that it works and writing the
> sigrok driver. At that point, the floodgates will open and it will be
> cloned since others already did the legwork for the Chinese vendors.
> They have software to ship with their hardware, the firmware is
> available, the hardw
On Fri, 2018-01-26 at 11:26 +, Chris Obbard wrote:
> >
> > Heck, Cypress even has a datapump
> > demo firmware for the FX3 written already. It's all there.
> >
> > https://github.com/esden/bitmagic is what I'm betting on because he
> > has commercial interest. It's obvious that such a design
> Heck, Cypress even has a datapump
> demo firmware for the FX3 written already. It's all there.
>
> https://github.com/esden/bitmagic is what I'm betting on because he
> has commercial interest. It's obvious that such a design will be
> cloned by Chinese vendors, which is both good and bad. Either
Hello folks,
> Wouldn't it be better to invest more time in support for existing
> logic analyzers? Features like memory compression support for
> pulseview would help the project a lot more in my opinion.
No, because frankly, what's currently out there is crap.
Using an FPGA as a front-end and
On 01/26/18 00:23, Soeren Apel wrote:
-) Initially, they created a kickstarter [1]. You can see their claims
of open hardware and open software. Initially, they had removed all
traces of sigrok/PV from the UI, even though they did retain certain
copyright notices and sigrok references in the sour
What abount the SUMP2?
--
Uwe Bonnesb...@elektron.ikp.physik.tu-darmstadt.de
Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt
- Tel. 06151 1623569 --- Fax. 06151 1623305 -
--
> Yeah, very good point. This goes back to my original question
> then, which high-end (polished!) hardware would be best for most
> people who "just want a logic analyser (that's not Sal*e)" to use?
High-end is costly. If we're talking about several Gs/second it's
definitely not something th
> So this goes onto my next question, who's interested in designing an
> open-source logic-analyser with good chassis, cables etc for Sigrok?
Wouldn't it be better to invest more time in support for existing
logic analyzers? Features like memory compression support for pulseview
would help the pro
>> So this goes onto my next question, who's interested in designing an
>> open-source logic-analyser with good chassis, cables etc for Sigrok?
>
> Wouldn't it be better to invest more time in support for existing
> logic analyzers? Features like memory compression support for pulseview
> would hel
> It's been a while and I'm not aware of an "official" collection of
> events, but here's a list of the things I remember:
>
> -) Initially, they created a kickstarter [1]. You can see their claims
> of open hardware and open software. Initially, they had removed all
> traces of sigrok/PV from the
Hi Wolram,
> > insist that DreamsSource labs is not an ethical company since they
> > treated (and still treat) the sigrok project like shit.
>
> Didn't know that, but really good to know! Uwe Bonnes pointed to the
> same direction. Any pointers for details?
It's been a while and I'm not aware o
On Donnerstag, 25. Januar 2018 16:33:56 CET Chris Obbard wrote:
> I saw an interesting video from a chap called CNLohr about using the
> Cypress USB3 dev board as a logic analyser.
>
> Not sure whether he was planning to support Sigrok?
>
> https://youtu.be/_LnZrXrdC00
>
> On Thu, 25 Jan 2018 at
Hi!
> > with an Openbench Logic Sniffer (open hardware/firmware), a Saanlima
> > Pipistrello (open hardware/firmware)
>
> Unfortunately the Pipistrello with 64 MB DRAM appear to be discontinued:
Yes :( I plan to update all OLS based wiki entries, hopefully in
February. Such information will be a
Hi Soeren,
> insist that DreamsSource labs is not an ethical company since they
> treated (and still treat) the sigrok project like shit.
Didn't know that, but really good to know! Uwe Bonnes pointed to the
same direction. Any pointers for details?
I submitted a talk about measuring with free HW
On 01/25/18 16:24, Soeren Apel wrote:
insist that DreamsSource labs is not an ethical company since they
treated (and still treat) the sigrok project like shit.
Hence, I strongly advice against the DSLogic. I am well aware that
unfortunately, the hardware looks good and offers features a lot
of
> "Wolfram" == Wolfram Sang writes:
>> Both look like pretty good ideas, but I am really after something in
>> a case that I could chuck into a tool bag if needed.
Wolfram> I don't have this one, but maybe someone else can add
Wolfram> experiences with it?
Wolfram> https
Hi Wolfram and Chris,
Chris, you asked for an ethical company and for a product that
you can recommend to colleagues. In this case, I must strongly
insist that DreamsSource labs is not an ethical company since they
treated (and still treat) the sigrok project like shit.
Hence, I strongly advice a
I saw an interesting video from a chap called CNLohr about using the
Cypress USB3 dev board as a logic analyser.
Not sure whether he was planning to support Sigrok?
https://youtu.be/_LnZrXrdC00
On Thu, 25 Jan 2018 at 15:31, Uwe Bonnes <
b...@elektron.ikp.physik.tu-darmstadt.de> wrote:
> > "
> Both look like pretty good ideas, but I am really after something in a
> case that I could chuck into a tool bag if needed.
I don't have this one, but maybe someone else can add experiences with
it?
https://sigrok.org/wiki/DreamSourceLab_DSLogic
In their Kickstarter, they claimed "OpenHardwar
> I do such kind of measurements with an Openbench Logic Sniffer.
> Reasonable price and around for years.
>
> I just bought this "OLS on steroids" [1] [2] with much more RAM but I am
> unsure about its future availability.
>
> Finding the best firmware initially is the biggest obstacle. I will
> u
> I am often going to be looking at 4+ channels at over 10MHz per
> channel and really want the hardware to be Open Source/from a decent,
> ethical company that will last a long time (so I can recommend them to
> colleagues).
I do such kind of measurements with an Openbench Logic Sniffer.
Reasona
Hey guys
I am after a "decent" logic analyser that works well with Sigrok &
PulseView, I have the cheapo Salae clone and am dissatisfied at the
20MHz claim.
I am often going to be looking at 4+ channels at over 10MHz per
channel and really want the hardware to be Open Source/from a decent,
ethica
Hi,
On Wed, Sep 21, 2016 at 12:18:30PM +, John wrote:
> Dear Sigrok developers.I have Hantek MSO5102D .Can You help with connecting
> to the PulseView ?
This device is not yet supported by sigrok as far as we know.
You could start with providing a "lsusb -v" (as root) and if it's USBTMC
the
Dear Sigrok developers.I have Hantek MSO5102D .Can You help with connecting to
the PulseView ?--
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Hi,
On Mon, May 25, 2015 at 06:01:21PM +0200, code.warr...@voila.fr wrote:
> I'm trying to use a VICTOR 86D with pulseview.
> I saw it was listed in your multimeter comparison :
> http://sigrok.org/wiki/Multimeter_comparison
> but it's not detected.
PulseView doesn't currently support multimeter
Hello,
I'm trying to use a VICTOR 86D with pulseview.
I saw it was listed in your multimeter comparison :
http://sigrok.org/wiki/Multimeter_comparison
but it's not detected.
As this 6000 points meter is fine, I would like to know if ther's a chance to
have it detected and supported.
As I'm a dev
These patches add BeagleLogic support to libsigrok.
The implementation currently supports:
* One-shot sampling only (continuous sampling is implemented but not
recommended)
* Software triggers with no pre-trigger samples currently
* Sample rate configuration is fully supported
* Number of cha
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