Module Name:src
Committed By: skrll
Date: Thu Apr 9 06:49:37 UTC 2020
Modified Files:
src/sys/arch/mips/mips: trap.c
Log Message:
Wrap a REALLY long line
To generate a diff of this commit:
cvs rdiff -u -r1.252 -r1.253 src/sys/arch/mips/mips/trap.c
Please note that diff
Module Name:src
Committed By: skrll
Date: Thu Apr 9 06:47:50 UTC 2020
Modified Files:
src/sys/arch/mips/mips: trap.c
Log Message:
Fix UVMHIST build
To generate a diff of this commit:
cvs rdiff -u -r1.251 -r1.252 src/sys/arch/mips/mips/trap.c
Please note that diffs are
Module Name:src
Committed By: thorpej
Date: Fri Mar 13 03:49:39 UTC 2020
Modified Files:
src/sys/arch/mips/mips: bus_dma.c
Log Message:
Allow len == 0 in bus_dmamap_sync().
XXX pullup-9
To generate a diff of this commit:
cvs rdiff -u -r1.38 -r1.39 src/sys/arch/mips/mips
Module Name:src
Committed By: thorpej
Date: Tue Mar 10 04:04:45 UTC 2020
Modified Files:
src/sys/arch/mips/mips: trap.c
Log Message:
Comment out the diagnostic message in the TLB_MOD handler that's logged if
pmap_tlb_update_addr() indicates that the VA+ASID was not found i
Module Name:src
Committed By: thorpej
Date: Sat Mar 7 18:49:49 UTC 2020
Modified Files:
src/sys/arch/mips/mips: trap.c
Log Message:
Add missing newline to a diagnostic printf.
To generate a diff of this commit:
cvs rdiff -u -r1.249 -r1.250 src/sys/arch/mips/mips/trap.c
Module Name:src
Committed By: skrll
Date: Sat Feb 15 17:01:01 UTC 2020
Modified Files:
src/sys/arch/mips/mips: mipsX_subr.S
Log Message:
Fix two comments
To generate a diff of this commit:
cvs rdiff -u -r1.106 -r1.107 src/sys/arch/mips/mips/mipsX_subr.S
Please note that
Module Name:src
Committed By: skrll
Date: Sat Feb 15 16:56:15 UTC 2020
Modified Files:
src/sys/arch/mips/mips: mipsX_subr.S
Log Message:
typo in comment
To generate a diff of this commit:
cvs rdiff -u -r1.105 -r1.106 src/sys/arch/mips/mips/mipsX_subr.S
Please note that
Module Name:src
Committed By: msaitoh
Date: Fri Dec 27 09:47:18 UTC 2019
Modified Files:
src/sys/arch/mips/mips: cache.c
Log Message:
s/defintion/definition/ in comment.
To generate a diff of this commit:
cvs rdiff -u -r1.60 -r1.61 src/sys/arch/mips/mips/cache.c
Please
Module Name:src
Committed By: maya
Date: Sat Apr 13 21:39:46 UTC 2019
Modified Files:
src/sys/arch/mips/mips: cache_octeon.c
Log Message:
Remove unused declaration of __BIT and __BITS
it's defined already, tested with #error.
To generate a diff of this commit:
cvs rdiff
Module Name:src
Committed By: skrll
Date: Fri Apr 12 21:12:21 UTC 2019
Modified Files:
src/sys/arch/mips/mips: spl.S
Log Message:
Typo in comment
To generate a diff of this commit:
cvs rdiff -u -r1.16 -r1.17 src/sys/arch/mips/mips/spl.S
Please note that diffs are not pu
Module Name:src
Committed By: simonb
Date: Thu Apr 4 22:49:46 UTC 2019
Modified Files:
src/sys/arch/mips/mips: db_interface.c
Log Message:
Consistently use db_printf() instead of printf() for machine specific
commands.
To generate a diff of this commit:
cvs rdiff -u -r1
Module Name:src
Committed By: simonb
Date: Fri Mar 29 05:23:12 UTC 2019
Modified Files:
src/sys/arch/mips/mips: mips_machdep.c
Log Message:
Add entry for MIPS 25Kf.
To generate a diff of this commit:
cvs rdiff -u -r1.278 -r1.279 src/sys/arch/mips/mips/mips_machdep.c
Ple
Module Name:src
Committed By: riastradh
Date: Wed Dec 19 15:10:46 UTC 2018
Modified Files:
src/sys/arch/mips/mips: fp.S
Log Message:
Load curlwp into a0 to call fpu_save(curlwp), not fpu_save(garbage).
The lwp argument to fpu_save was added by chuq in revision 1.14 of
mip
Module Name:src
Committed By: macallan
Date: Fri Sep 7 21:14:45 UTC 2018
Modified Files:
src/sys/arch/mips/mips: locore.S
Log Message:
re-enable 64bit addressing in n32 kernels
Now these work again, at least on my Indy.
To generate a diff of this commit:
cvs rdiff -u -r
Module Name:src
Committed By: mrg
Date: Sun Aug 19 10:33:49 UTC 2018
Modified Files:
src/sys/arch/mips/mips: cpu_exec.c
Log Message:
fix a bug in the previous change: don't hide the break; behind DEBUG_EXEC.
should fix PR#53538. tested on erlite.
To generate a diff of t
Module Name:src
Committed By: simonb
Date: Wed Aug 8 07:50:12 UTC 2018
Modified Files:
src/sys/arch/mips/mips: cpu_exec.c
Log Message:
Make change of ABI printf()s #ifdef DEBUG_EXEC.
To generate a diff of this commit:
cvs rdiff -u -r1.65 -r1.66 src/sys/arch/mips/mips/cp
Module Name:src
Committed By: maya
Date: Wed Mar 28 17:56:52 UTC 2018
Modified Files:
src/sys/arch/mips/mips: locore.S
Log Message:
Leave TS and RE alone for the benefit of emips, which failed
to boot even earlier after locore.S:1.211.
Do this unconditionally to avoid int
Module Name:src
Committed By: maya
Date: Wed Mar 7 20:48:00 UTC 2018
Modified Files:
src/sys/arch/mips/mips: locore.S
Log Message:
Remove now duplicate code for enabling FPU before reading FPU_ID
To generate a diff of this commit:
cvs rdiff -u -r1.216 -r1.217 src/sys/ar
Module Name:src
Committed By: maya
Date: Wed Mar 7 20:46:06 UTC 2018
Modified Files:
src/sys/arch/mips/mips: locore.S
Log Message:
Remove now duplicate code to read FPU_ID into t1
To generate a diff of this commit:
cvs rdiff -u -r1.215 -r1.216 src/sys/arch/mips/mips/loc
Module Name:src
Committed By: maya
Date: Wed Mar 7 20:43:54 UTC 2018
Modified Files:
src/sys/arch/mips/mips: locore.S
Log Message:
Remove duplicate confused code for enabling 64bit addressing
To generate a diff of this commit:
cvs rdiff -u -r1.214 -r1.215 src/sys/arch/m
Module Name:src
Committed By: maya
Date: Wed Mar 7 15:56:34 UTC 2018
Modified Files:
src/sys/arch/mips/mips: locore.S
Log Message:
Add duplicate code to read the FPU ID.
enable & disable the FPU around it.
To generate a diff of this commit:
cvs rdiff -u -r1.213 -r1.214
Module Name:src
Committed By: maya
Date: Wed Mar 7 15:52:43 UTC 2018
Modified Files:
src/sys/arch/mips/mips: locore.S
Log Message:
Move the hpcmips L1 cache disable hack up
where another machine-specific hacks exists.
Note that no existing kernel seems to enable this opt
Module Name:src
Committed By: maya
Date: Wed Mar 7 15:49:45 UTC 2018
Modified Files:
src/sys/arch/mips/mips: locore.S
Log Message:
Add duplicate code that enables 64bit addressing under the right
macro conditions that is, _LP64.
The existing, previous code uses NOFPU as
Module Name:src
Committed By: maya
Date: Wed Mar 7 15:44:15 UTC 2018
Modified Files:
src/sys/arch/mips/mips: locore.S
Log Message:
Replace early interrupt disable code.
As suggested by dh, carefully disable interrupts before frobbing
interrupt mask, which might trigger m
Module Name:src
Committed By: flxd
Date: Sat Mar 3 15:47:50 UTC 2018
Modified Files:
src/sys/arch/mips/mips: cache.c
Log Message:
Add missing call to mips_dcache_compute_align() affecting "modern" MIPS
(MIPS32{,R2}/MIPS64{,R2}). Thanks jmcneill@; OK skrll@.
To generate
Module Name:src
Committed By: maya
Date: Fri Jan 26 05:29:43 UTC 2018
Modified Files:
src/sys/arch/mips/mips: locore_mips3.S
Log Message:
Don't warn about MIPS1 MULTIPROCESSOR in a mips3 file.
To generate a diff of this commit:
cvs rdiff -u -r1.113 -r1.114 src/sys/arch/m
Module Name:src
Committed By: maya
Date: Wed Jan 24 03:13:36 UTC 2018
Modified Files:
src/sys/arch/mips/mips: locore.S
Log Message:
Clarify this is a load delay nop.
To generate a diff of this commit:
cvs rdiff -u -r1.209 -r1.210 src/sys/arch/mips/mips/locore.S
Please n
Module Name:src
Committed By: maya
Date: Wed Jan 24 03:11:30 UTC 2018
Modified Files:
src/sys/arch/mips/mips: locore.S
Log Message:
Add whitespace for clarity.
To generate a diff of this commit:
cvs rdiff -u -r1.208 -r1.209 src/sys/arch/mips/mips/locore.S
Please note th
Module Name:src
Committed By: flxd
Date: Mon Jan 22 18:15:57 UTC 2018
Modified Files:
src/sys/arch/mips/mips: bus_space_alignstride_chipdep.c
Log Message:
Use right variable as revealed by previous typo...
To generate a diff of this commit:
cvs rdiff -u -r1.30 -r1.31 \
Module Name:src
Committed By: flxd
Date: Sun Jan 21 16:38:25 UTC 2018
Modified Files:
src/sys/arch/mips/mips: bus_space_alignstride_chipdep.c
Log Message:
fix typo
To generate a diff of this commit:
cvs rdiff -u -r1.29 -r1.30 \
src/sys/arch/mips/mips/bus_space_aligns
Module Name:src
Committed By: maya
Date: Fri Dec 22 22:59:26 UTC 2017
Modified Files:
src/sys/arch/mips/mips: trap.c
Log Message:
Don't handle emulations overriding e_fault.
No existing emulations do this.
(COMPAT_IRIX did, but was removed)
To generate a diff of this co
Module Name:src
Committed By: mrg
Date: Thu Aug 24 23:45:08 UTC 2017
Modified Files:
src/sys/arch/mips/mips: bds_emul.S
Log Message:
mips_emul_daddi and mips_emul_daddiu don't exist, but there are
bcemul_daddi and bcemul_daddiu here that should be used. however,
bcemul_da
Module Name:src
Committed By: maya
Date: Thu Aug 24 14:26:16 UTC 2017
Modified Files:
src/sys/arch/mips/mips: lock_stubs_llsc.S
Log Message:
Eliminate redundant load delays.
Machines that need load delays do not have ll/sc instructions.
To generate a diff of this commit
Module Name:src
Committed By: maxv
Date: Sun Aug 20 11:06:36 UTC 2017
Modified Files:
src/sys/arch/mips/mips: cpu_subr.c
Log Message:
spl leak, found by mootja
To generate a diff of this commit:
cvs rdiff -u -r1.32 -r1.33 src/sys/arch/mips/mips/cpu_subr.c
Please note th
Module Name:src
Committed By: maya
Date: Sun Aug 20 09:47:14 UTC 2017
Modified Files:
src/sys/arch/mips/mips: mipsX_subr.S
Log Message:
use meaningful name for errata hack, dedup
To generate a diff of this commit:
cvs rdiff -u -r1.103 -r1.104 src/sys/arch/mips/mips/mipsX
Module Name:src
Committed By: maya
Date: Sun Aug 20 09:21:54 UTC 2017
Modified Files:
src/sys/arch/mips/mips: mipsX_subr.S
Log Message:
Don't need the errata workaround on user return
It's reported that the MMU will block such invalid reads in userland,
and it's only neede
Module Name:src
Committed By: maya
Date: Tue Aug 8 09:34:59 UTC 2017
Modified Files:
src/sys/arch/mips/mips: mipsX_subr.S
Log Message:
Remove whitespace I just introduced
To generate a diff of this commit:
cvs rdiff -u -r1.101 -r1.102 src/sys/arch/mips/mips/mipsX_subr.S
Module Name:src
Committed By: maya
Date: Tue Aug 8 09:33:41 UTC 2017
Modified Files:
src/sys/arch/mips/mips: mipsX_subr.S
Log Message:
In working around loongson errata clear BTB and RAS, same as
other operating systems.
15 Errata: Issue of Out-of-order in loongson (tran
Module Name:src
Committed By: christos
Date: Fri Jul 14 20:32:32 UTC 2017
Modified Files:
src/sys/arch/mips/mips: trap.c
Log Message:
Advance the PC on breakpoint instruction to avoid infinite loop DoS!
To generate a diff of this commit:
cvs rdiff -u -r1.243 -r1.244 src/
Module Name:src
Committed By: christos
Date: Fri Jul 14 17:54:00 UTC 2017
Modified Files:
src/sys/arch/mips/mips: vm_machdep.c
Log Message:
KASSERT Fires for MIPS1, disable.
To generate a diff of this commit:
cvs rdiff -u -r1.158 -r1.159 src/sys/arch/mips/mips/vm_machdep
Module Name:src
Committed By: skrll
Date: Fri Jun 9 06:43:30 UTC 2017
Modified Files:
src/sys/arch/mips/mips: mips_machdep.c
Log Message:
Maintain the split of physical memory into the defined freelists, but
only force pool pages to VM_FREELIST_FIRST512M for non _LP64
T
Module Name:src
Committed By: skrll
Date: Fri Jun 9 06:39:24 UTC 2017
Modified Files:
src/sys/arch/mips/mips: pmap_machdep.c
Log Message:
Always use XKPHYS for pool pages on _LP64; otherwise use KSEG0
To generate a diff of this commit:
cvs rdiff -u -r1.20 -r1.21 src/sys
Module Name:src
Committed By: skrll
Date: Thu Jun 8 05:46:57 UTC 2017
Modified Files:
src/sys/arch/mips/mips: locore_mips1.S
Log Message:
Add a missing ".set at" to make previous build
To generate a diff of this commit:
cvs rdiff -u -r1.92 -r1.93 src/sys/arch/mips/mips/
Module Name:src
Committed By: skrll
Date: Wed Jun 7 08:45:51 UTC 2017
Modified Files:
src/sys/arch/mips/mips: locore_mips1.S
Log Message:
fix tlb_record_asids 2nd arg to match usage - it's a maximum asid value
and not a mask
To generate a diff of this commit:
cvs rdiff
Module Name:src
Committed By: skrll
Date: Mon Jun 5 10:45:36 UTC 2017
Modified Files:
src/sys/arch/mips/mips: pmap_machdep.c
Log Message:
Fix the PMAP_NO_PV_UNCACHED pmap_md_vca_add case where the pmap_update
call would cause problems for pmap_remove_all case where the de
Module Name:src
Committed By: skrll
Date: Thu May 18 13:20:37 UTC 2017
Modified Files:
src/sys/arch/mips/mips: pmap_machdep.c
Log Message:
Don't use index cache operations unnecessarily.
To generate a diff of this commit:
cvs rdiff -u -r1.18 -r1.19 src/sys/arch/mips/mips
Module Name:src
Committed By: skrll
Date: Mon May 15 10:59:24 UTC 2017
Modified Files:
src/sys/arch/mips/mips: mipsX_subr.S
Log Message:
Fix off-by-one in tlb_record_asids
To generate a diff of this commit:
cvs rdiff -u -r1.99 -r1.100 src/sys/arch/mips/mips/mipsX_subr.S
Module Name:src
Committed By: skrll
Date: Sun May 14 15:36:46 UTC 2017
Modified Files:
src/sys/arch/mips/mips: pmap_machdep.c
Log Message:
Remove #if 0'ed old style cache handling in pmap_md_unmap_poolpage
To generate a diff of this commit:
cvs rdiff -u -r1.17 -r1.18 src
Module Name:src
Committed By: skrll
Date: Sun May 14 11:46:22 UTC 2017
Modified Files:
src/sys/arch/mips/mips: pmap_machdep.c
Log Message:
Handle the maximum number of colors across [di]caches
To generate a diff of this commit:
cvs rdiff -u -r1.16 -r1.17 src/sys/arch/mip
Module Name:src
Committed By: skrll
Date: Sun May 14 09:37:13 UTC 2017
Modified Files:
src/sys/arch/mips/mips: cache.c
Log Message:
Set mci_{,i}cache_alias_mask for all variants that can have virtual cache
aliases
Set ncolors appropriately
These align to dcache and expec
Module Name:src
Committed By: skrll
Date: Sun May 14 09:33:17 UTC 2017
Modified Files:
src/sys/arch/mips/mips: cache.c
Log Message:
Really fix typo that got dcache alias mask set from icache way_mask
To generate a diff of this commit:
cvs rdiff -u -r1.56 -r1.57 src/sys/a
Module Name:src
Committed By: skrll
Date: Sun May 14 09:32:01 UTC 2017
Modified Files:
src/sys/arch/mips/mips: cache.c
Log Message:
Fix typo that got dcache alias mask set from icache way_mask
To generate a diff of this commit:
cvs rdiff -u -r1.55 -r1.56 src/sys/arch/mip
Module Name:src
Committed By: skrll
Date: Fri May 12 06:49:31 UTC 2017
Modified Files:
src/sys/arch/mips/mips: pmap_machdep.c
Log Message:
Sprinkle some KASSERTs
To generate a diff of this commit:
cvs rdiff -u -r1.15 -r1.16 src/sys/arch/mips/mips/pmap_machdep.c
Please n
Module Name:src
Committed By: skrll
Date: Fri May 12 06:43:42 UTC 2017
Modified Files:
src/sys/arch/mips/mips: pmap_machdep.c
Log Message:
Code style and add a comment
To generate a diff of this commit:
cvs rdiff -u -r1.14 -r1.15 src/sys/arch/mips/mips/pmap_machdep.c
Pl
Module Name:src
Committed By: skrll
Date: Fri May 12 06:38:18 UTC 2017
Modified Files:
src/sys/arch/mips/mips: pmap_machdep.c
Log Message:
Don't access pg before the KASSERT it's not NULL
To generate a diff of this commit:
cvs rdiff -u -r1.13 -r1.14 src/sys/arch/mips/mip
Module Name:src
Committed By: skrll
Date: Thu May 11 09:09:54 UTC 2017
Modified Files:
src/sys/arch/mips/mips: vm_machdep.c
Log Message:
Fix non-DIAGNOSTIC build
To generate a diff of this commit:
cvs rdiff -u -r1.157 -r1.158 src/sys/arch/mips/mips/vm_machdep.c
Please n
Module Name:src
Committed By: skrll
Date: Wed May 10 22:23:13 UTC 2017
Modified Files:
src/sys/arch/mips/mips: vm_machdep.c
Log Message:
Add a KASSERT
To generate a diff of this commit:
cvs rdiff -u -r1.156 -r1.157 src/sys/arch/mips/mips/vm_machdep.c
Please note that di
Module Name:src
Committed By: skrll
Date: Wed May 10 22:19:31 UTC 2017
Modified Files:
src/sys/arch/mips/mips: vm_machdep.c
Log Message:
Make cpu_uarea_{alloc,free} conditional on PMAP_{,UN}MAP_POOLPAGE and
use PMAP_{,UN}_POOLPAGE to ensure cache aliases are handled correc
Module Name:src
Committed By: skrll
Date: Wed May 10 12:12:21 UTC 2017
Modified Files:
src/sys/arch/mips/mips: vm_machdep.c
Log Message:
Allow cpu_uarea_alloc to return NULL for non-system LWPs in the non-_LP64
case. That way TLB mapped KVA can be found by uarea_poolpage_
Module Name:src
Committed By: skrll
Date: Wed May 10 11:27:14 UTC 2017
Modified Files:
src/sys/arch/mips/mips: vm_machdep.c
Log Message:
Improve comment wording.
To generate a diff of this commit:
cvs rdiff -u -r1.153 -r1.154 src/sys/arch/mips/mips/vm_machdep.c
Please n
Module Name:src
Committed By: skrll
Date: Sun May 7 05:50:39 UTC 2017
Modified Files:
src/sys/arch/mips/mips: mipsX_subr.S
Log Message:
Check the TLB entry ASID against base (a0) and limit (a1), and not
limit (a1) and random register value (a2)
While here shave an instru
Module Name:src
Committed By: skrll
Date: Sun May 7 05:48:01 UTC 2017
Modified Files:
src/sys/arch/mips/mips: mipsX_subr.S
Log Message:
Save/restore pgMask in tlb_record_asids
To generate a diff of this commit:
cvs rdiff -u -r1.97 -r1.98 src/sys/arch/mips/mips/mipsX_sub
Module Name:src
Committed By: skrll
Date: Sun May 7 05:45:07 UTC 2017
Modified Files:
src/sys/arch/mips/mips: mips3_clock.c mips_dsp.c mips_fpu.c
mips_machdep.c
Log Message:
opt_multiprocessor.h police
To generate a diff of this commit:
cvs rdiff -u -r1.13 -
Module Name:src
Committed By: skrll
Date: Sun May 7 04:59:19 UTC 2017
Modified Files:
src/sys/arch/mips/mips: mipsX_subr.S
Log Message:
Call an ASID an ASID in comments
To generate a diff of this commit:
cvs rdiff -u -r1.96 -r1.97 src/sys/arch/mips/mips/mipsX_subr.S
Pl
Module Name:src
Committed By: skrll
Date: Sun May 7 04:14:20 UTC 2017
Modified Files:
src/sys/arch/mips/mips: cpu_subr.c pmap_machdep.c
Log Message:
KNF
To generate a diff of this commit:
cvs rdiff -u -r1.31 -r1.32 src/sys/arch/mips/mips/cpu_subr.c
cvs rdiff -u -r1.12 -
Module Name:src
Committed By: skrll
Date: Thu Apr 27 20:05:09 UTC 2017
Modified Files:
src/sys/arch/mips/mips: cache_r5k.c
Log Message:
Typo in comment
To generate a diff of this commit:
cvs rdiff -u -r1.19 -r1.20 src/sys/arch/mips/mips/cache_r5k.c
Please note that diff
Module Name:src
Committed By: skrll
Date: Thu Apr 27 19:40:55 UTC 2017
Modified Files:
src/sys/arch/mips/mips: cache_r4k_subr.S
Log Message:
Typo in comment
To generate a diff of this commit:
cvs rdiff -u -r1.2 -r1.3 src/sys/arch/mips/mips/cache_r4k_subr.S
Please note t
Module Name:src
Committed By: skrll
Date: Sat Apr 22 20:32:35 UTC 2017
Modified Files:
src/sys/arch/mips/mips: cache.c
Log Message:
Comment indentation
To generate a diff of this commit:
cvs rdiff -u -r1.54 -r1.55 src/sys/arch/mips/mips/cache.c
Please note that diffs ar
Module Name:src
Committed By: skrll
Date: Wed Mar 1 11:54:53 UTC 2017
Modified Files:
src/sys/arch/mips/mips: lock_stubs_ras.S
Log Message:
Can't profile ras_atomic_cas_noupdate
To generate a diff of this commit:
cvs rdiff -u -r1.8 -r1.9 src/sys/arch/mips/mips/lock_stub
Module Name:src
Committed By: chs
Date: Mon Feb 27 06:57:45 UTC 2017
Modified Files:
src/sys/arch/mips/mips: fp.S
Log Message:
in mips_emul_fp(), clear all pending FP exceptions rather than
just a particular one, otherwise the kernel can take another
FPU trap when it write
Module Name:src
Committed By: chs
Date: Mon Feb 27 06:56:33 UTC 2017
Modified Files:
src/sys/arch/mips/mips: db_disasm.c
Log Message:
the second operand to cfc1/ctc1 isn't an FPU data register
so don't make it look like one.
To generate a diff of this commit:
cvs rdiff -
Module Name:src
Committed By: mrg
Date: Thu Dec 22 07:56:38 UTC 2016
Modified Files:
src/sys/arch/mips/mips: mips_machdep.c
Log Message:
fix lp64 kvm access for many kernel addresses.
in mm_md_kernacc() allow an address if it matches MIPS_KSEG0_P().
now a static n64 kvm-u
Module Name:src
Committed By: skrll
Date: Sat Nov 19 09:05:50 UTC 2016
Modified Files:
src/sys/arch/mips/mips: mipsX_subr.S
Log Message:
Optimise the interrupt vector a litte. From matt@
To generate a diff of this commit:
cvs rdiff -u -r1.95 -r1.96 src/sys/arch/mips/mip
Module Name:src
Committed By: skrll
Date: Fri Nov 18 16:23:40 UTC 2016
Modified Files:
src/sys/arch/mips/mips: spl.S
Log Message:
Sprinkle MFC0_HAZARD for previous and PARANOIA
To generate a diff of this commit:
cvs rdiff -u -r1.15 -r1.16 src/sys/arch/mips/mips/spl.S
Pl
Module Name:src
Committed By: macallan
Date: Fri Nov 18 13:50:36 UTC 2016
Modified Files:
src/sys/arch/mips/mips: spl.S
Log Message:
don't blindly zero STATUS in order to disable interrupts, instead take care
to preserve bits like KX in case we catch an interrupt between m
Module Name:src
Committed By: maya
Date: Fri Nov 11 16:49:30 UTC 2016
Modified Files:
src/sys/arch/mips/mips: spl.S
Log Message:
switch post-mfc0 call "hazard barrier" from NOP_L to MFC0_HAZARD.
this means it will be applied if MIPS3 too, and now with the prior
commit, it
Module Name:src
Committed By: maya
Date: Fri Nov 11 16:45:14 UTC 2016
Modified Files:
src/sys/arch/mips/mips: spl.S
Log Message:
remove redundant NOP_L. we do not use the register immediately after
load, so it's not needed.
To generate a diff of this commit:
cvs rdiff -u
Module Name:src
Committed By: maxv
Date: Sun Oct 16 10:57:58 UTC 2016
Modified Files:
src/sys/arch/mips/mips: cpu_exec.c
Log Message:
Remove unused (and buggy) function. Not even compile-tested, but I've
been told to go ahead anyway.
To generate a diff of this commit:
cv
Module Name:src
Committed By: macallan
Date: Thu Oct 13 18:58:00 UTC 2016
Modified Files:
src/sys/arch/mips/mips: locore.S
Log Message:
include locore.h for MIPS3_PLUS, while there annotate some #else and #endif
To generate a diff of this commit:
cvs rdiff -u -r1.206 -r1
Module Name:src
Committed By: macallan
Date: Thu Oct 13 18:54:46 UTC 2016
Modified Files:
src/sys/arch/mips/mips: fp.S
Log Message:
include locore.h so MIPS3_PLUS is visible and we build support for MIPS-III
and newer FPUs as needed
no more SIGILLs on trunc.d.* with n32 us
Module Name:src
Committed By: skrll
Date: Mon Oct 10 07:37:56 UTC 2016
Modified Files:
src/sys/arch/mips/mips: cache_r5k.c
Log Message:
Trailing whitespace
To generate a diff of this commit:
cvs rdiff -u -r1.18 -r1.19 src/sys/arch/mips/mips/cache_r5k.c
Please note that
Module Name:src
Committed By: skrll
Date: Mon Oct 10 07:37:17 UTC 2016
Modified Files:
src/sys/arch/mips/mips: cache_r5k.c
Log Message:
vaddr_t -> register_t in range cache ops
To generate a diff of this commit:
cvs rdiff -u -r1.17 -r1.18 src/sys/arch/mips/mips/cache_r5k
Module Name:src
Committed By: skrll
Date: Sat Oct 8 08:19:22 UTC 2016
Modified Files:
src/sys/arch/mips/mips: mips_fixup.c
Log Message:
Sign extend VA for cache operations.
OK matt@
To generate a diff of this commit:
cvs rdiff -u -r1.18 -r1.19 src/sys/arch/mips/mips/mi
Module Name:src
Committed By: macallan
Date: Sat Oct 8 00:39:53 UTC 2016
Modified Files:
src/sys/arch/mips/mips: cache_r5k.c
Log Message:
- don't clear KX when disabling interrupts
- sign extend addresses as needed
- use PAGE_SIZE instead of blindly assuming 4KB
now n32 k
Module Name:src
Committed By: maya
Date: Sun Oct 2 09:06:35 UTC 2016
Modified Files:
src/sys/arch/mips/mips: mipsX_subr.S
Log Message:
Simplify. LOONGSON2 and MIPSNNR2 not possible.
To generate a diff of this commit:
cvs rdiff -u -r1.93 -r1.94 src/sys/arch/mips/mips/mip
Module Name:src
Committed By: skrll
Date: Sat Sep 10 13:42:11 UTC 2016
Modified Files:
src/sys/arch/mips/mips: trap.c
Log Message:
Remove stray assignment.
To generate a diff of this commit:
cvs rdiff -u -r1.242 -r1.243 src/sys/arch/mips/mips/trap.c
Please note that dif
Module Name:src
Committed By: skrll
Date: Sat Sep 10 13:40:14 UTC 2016
Modified Files:
src/sys/arch/mips/mips: trap.c
Log Message:
Fixup siginfo
To generate a diff of this commit:
cvs rdiff -u -r1.241 -r1.242 src/sys/arch/mips/mips/trap.c
Please note that diffs are not
Module Name:src
Committed By: skrll
Date: Mon Sep 5 06:59:25 UTC 2016
Modified Files:
src/sys/arch/mips/mips: pmap_machdep.c
Log Message:
Flush the dcache before syncing the icache as previous mappings (UBC)
might have used the same colo(u)r and the dcache won't have been
Module Name:src
Committed By: skrll
Date: Sun Sep 4 15:25:11 UTC 2016
Modified Files:
src/sys/arch/mips/mips: pmap_machdep.c
Log Message:
Another typo... that's what you get for not compile testing
To generate a diff of this commit:
cvs rdiff -u -r1.9 -r1.10 src/sys/arc
Module Name:src
Committed By: skrll
Date: Sun Sep 4 15:23:15 UTC 2016
Modified Files:
src/sys/arch/mips/mips: pmap_machdep.c
Log Message:
Typo in previous
To generate a diff of this commit:
cvs rdiff -u -r1.8 -r1.9 src/sys/arch/mips/mips/pmap_machdep.c
Please note that
Module Name:src
Committed By: skrll
Date: Sun Sep 4 15:21:54 UTC 2016
Modified Files:
src/sys/arch/mips/mips: pmap_machdep.c
Log Message:
Safely remove non-PV_KENTER pages from pv_list
To generate a diff of this commit:
cvs rdiff -u -r1.7 -r1.8 src/sys/arch/mips/mips/pm
Module Name:src
Committed By: skrll
Date: Sun Sep 4 07:47:12 UTC 2016
Modified Files:
src/sys/arch/mips/mips: pmap_machdep.c
Log Message:
Sign extend va for use with cache ops
To generate a diff of this commit:
cvs rdiff -u -r1.6 -r1.7 src/sys/arch/mips/mips/pmap_machde
Module Name:src
Committed By: skrll
Date: Sun Sep 4 07:38:45 UTC 2016
Modified Files:
src/sys/arch/mips/mips: pmap_machdep.c
Log Message:
More debug
To generate a diff of this commit:
cvs rdiff -u -r1.5 -r1.6 src/sys/arch/mips/mips/pmap_machdep.c
Please note that diffs
Module Name:src
Committed By: skrll
Date: Sun Sep 4 07:30:52 UTC 2016
Modified Files:
src/sys/arch/mips/mips: cache.c
Log Message:
Remove old and incorrect comments
To generate a diff of this commit:
cvs rdiff -u -r1.53 -r1.54 src/sys/arch/mips/mips/cache.c
Please note
Module Name:src
Committed By: skrll
Date: Sat Aug 27 07:22:15 UTC 2016
Modified Files:
src/sys/arch/mips/mips: mipsX_subr.S
Log Message:
Comment consistency. No functional change.
To generate a diff of this commit:
cvs rdiff -u -r1.92 -r1.93 src/sys/arch/mips/mips/mipsX
Module Name:src
Committed By: skrll
Date: Tue Aug 23 07:29:46 UTC 2016
Modified Files:
src/sys/arch/mips/mips: cpu_subr.c
Log Message:
Whitespcae
To generate a diff of this commit:
cvs rdiff -u -r1.28 -r1.29 src/sys/arch/mips/mips/cpu_subr.c
Please note that diffs are n
Module Name:src
Committed By: skrll
Date: Mon Aug 22 11:34:42 UTC 2016
Modified Files:
src/sys/arch/mips/mips: pmap_machdep.c
Log Message:
KNF
To generate a diff of this commit:
cvs rdiff -u -r1.4 -r1.5 src/sys/arch/mips/mips/pmap_machdep.c
Please note that diffs are no
Module Name:src
Committed By: skrll
Date: Mon Aug 22 11:34:06 UTC 2016
Modified Files:
src/sys/arch/mips/mips: pmap_machdep.c
Log Message:
Can't KASSERT that a lock isn't held.
To generate a diff of this commit:
cvs rdiff -u -r1.3 -r1.4 src/sys/arch/mips/mips/pmap_machde
Module Name:src
Committed By: skrll
Date: Fri Aug 19 10:05:35 UTC 2016
Modified Files:
src/sys/arch/mips/mips: cache.c lock_stubs_llsc.S lock_stubs_ras.S
locore.S pmap_machdep.c
Log Message:
Trailing whitespace
To generate a diff of this commit:
cvs rdiff -u
Module Name:src
Committed By: skrll
Date: Thu Aug 18 19:25:34 UTC 2016
Modified Files:
src/sys/arch/mips/mips: mips_fixup.c
Log Message:
Trailing whitespace
To generate a diff of this commit:
cvs rdiff -u -r1.17 -r1.18 src/sys/arch/mips/mips/mips_fixup.c
Please note tha
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