Anders
You can set the overall PLL divider to any even value between 4 and 66
as there is a fixed /2 prescaler preceding the programmable divider, so
with a 20MHz reference (from a 10MHz source) set the overall divider to
50 to give 1GHz - not sure if you set N to 50 or 25 in the Eval.
Some more testing today. It turns out that AD's schematic for the
evaluation board doesn't match with reality - and so I had not connected
the PLL filter components at all previously! Now they are 'in the loop' and
I get reasonable results without the 2x reference clock setting. With 2x
activated
On 12/31/13 8:07 AM, Anders Wallin wrote:
Could the remaining -60 dBc spurs at +/- 50 kHz be due to my 10MHz clock
source, an Agilent 33120A?
Yes the spurs could be from your source. that's a function generator/ARB
and spectral purity isn't one of the big design criteria for that kind
of
Hej Anders,
On 31/12/13 08:31, Anders Wallin wrote:
Thanks for all replies so far!
It looks like I will play around with the evaluation board some more, and
see if I can get the on-chip PLL to behave better.
The settings with 2x edge-detector and 60x PLL were the only ones I could
find where
On 12/30/2013 9:37 AM, Gerhard Hoffmann wrote:
Driving the DDS system clock from an expensive RF generator (e.g. HP
8648A)
would be possible but I'd prefer a PLL from 10MHz if it's doable
simply/cheaply.
Although expensive from a hobbyist viewpoint, the HP8648A is
far from HP/Agilent's best,
-hochfrequenz.de; time-nuts@febo.com
Subject: Re: [time-nuts] sysclock source for AD9912 DDS?
On 12/30/2013 9:37 AM, Gerhard Hoffmann wrote:
Driving the DDS system clock from an expensive RF generator (e.g. HP
8648A)
would be possible but I'd prefer a PLL from 10MHz if it's doable
simply
I've tested the AD9912 evaluation board:
http://www.anderswallin.net/wp-content/uploads/2013/12/dds_test_2013-12-30.png
I want to use it with a 10MHz external input clock, but it looks like the
on-board PLL that generates a 1200MHz sample clock from my input isn't that
great, since I get strong
On 12/30/13 7:56 AM, Anders Wallin wrote:
I've tested the AD9912 evaluation board:
http://www.anderswallin.net/wp-content/uploads/2013/12/dds_test_2013-12-30.png
I want to use it with a 10MHz external input clock, but it looks like the
on-board PLL that generates a 1200MHz sample clock from my
My lab has had good luck with the ADF4350 eval boards as clock generators.
The snippet description on the analog devices website of them is incorrect
though, they can accept a 10 MHz clock ref. The datasheet is definitely
more accurate than the description.
-Ben
On Mon, Dec 30, 2013 at 9:36
Anders,
I used an AD9858 years ago in our FireFox synthesizer product clocked at 1GHz
locked to the on-board 10MHz GPSDO.
I used an ADF4002 or 4000 (can't remember) pll with integer division driving a
UMC (now Sirenza) VCO. It worked very well and there where no 10MHz spurs
measurable. Its
Am 30.12.2013 16:56, schrieb Anders Wallin:
I've tested the AD9912 evaluation board:
http://www.anderswallin.net/wp-content/uploads/2013/12/dds_test_2013-12-30.png
I want to use it with a 10MHz external input clock, but it looks like the
on-board PLL that generates a 1200MHz sample clock from
measurement
Emne: [time-nuts] sysclock source for AD9912 DDS?
I've tested the AD9912 evaluation board:
http://www.anderswallin.net/wp-content/uploads/2013/12/dds_test_2013-12-30.p
ng
I want to use it with a 10MHz external input clock, but it looks like the
on-board PLL that generates a 1200MHz sample
, the highest being 900-1000MHz. I'd be
surprised if it locks at 1200MHz.
First thing is to try a 1000MHz clock.
regards
Grant Hodgson
From: Anders Wallin anders.e.e.wal...@gmail.com
To: Discussion of precise time and frequency measurement
time-nuts@febo.com
Subject: [time-nuts] sysclock
From: Said Jackson
Today I would not use a simple (cheap) 1GHz VCO anymore because of
the relatively high phase noise, and some if them require up to
20V drive voltage. I would use a Crystal based product such as our
ULN-1G 1GHz crystal oscillator. That part may be overkill since
Hi Anders,
Have a look at my AD9910 quadrature DDS
http://members.wideband.net.au/gzimmer/QuadDDS/default.html
I used a Crystek 1GHz SAW oscillator
regards Zim
___
time-nuts mailing list -- time-nuts@febo.com
To unsubscribe, go to
Thanks for all replies so far!
It looks like I will play around with the evaluation board some more, and
see if I can get the on-chip PLL to behave better.
The settings with 2x edge-detector and 60x PLL were the only ones I could
find where the output frequency setting in the software
16 matches
Mail list logo
