Re: [time-nuts] Digital Mixing with a BeagleBone Black and D Flip Flop
The current implementation used in WR was developed by Tomasz Wlostowski in the frame of his MSc thesis, following the ideas of Pablo Alvarez which Bruce pointed to earlier. As you can see in Tomasz's dissertation [1], there was not a lot of investigation on optimal strategies for DDTMD noise. The precision at the time was deemed more than adequate. It is very timely that you bring up this subject now, because I hope to start looking at ways to optimize phase noise in WR in the coming months, and noise coming from the DDMTD phase detector is definitely something I want to look at. I will be very interested in your ideas and findings regarding optimal strategies for the de-glitcher. Hi Simon and Javier, I arrive late to this discussion but I would like to add my grain of salt. As Javier says there was not a detailed optimization of the DDMTD architecture as jitter was already limited by all the surrounding electronics. I would like to add that much of the noise rejection is due to the implementation of a median estimator for the incoming edge position respect to the slightly-offset oscillator. It is easy and fun to proof that this median estimator can be implemented with a counter counting the number of sampled zeros and a simple state machine state machine that places counter start in a safe zone. In fact, when you think it out, the most curious thing is that this algorithm is nothing more than a sort of generalization of the bang-bang architecture to measure phase offsets. Cheers, Pablo ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Digital Mixing with a BeagleBone Black and D Flip Flop
Thanks Pablo. I've been finding that my implementation is a very good noise detector (in all kinds of fun ways) and my most recent effort has been at the hardware level in better layout, shielding and in reducing the number of noise sources. The impact of non-random noise is that transitions near an edge get quantised to the noise source, particularly the first and last transitions of a set. This leads to some of the simpler edge detection algorithms perfoming very poorly as they carry through this quantisation. Clearly, the cleaner the hardware implementation the less impact external noise will be until, hopefully, it is below requirements. At some point though I may get to a hardware/software tradeoff where the cost of reducing noise via hardware becomes more expensive than a complex edge detection algorithm that could remove the noise in software instead. Of course, everyone will have their own definition of what 'cost' and 'more expensive' means but in my case software solutions are relatively cheap as I'm using a general purpose processor rather than FPGA. Cheers Simon On 24/11/2014 11:59, pablo alvarez wrote: The current implementation used in WR was developed by Tomasz Wlostowski in the frame of his MSc thesis, following the ideas of Pablo Alvarez which Bruce pointed to earlier. As you can see in Tomasz's dissertation [1], there was not a lot of investigation on optimal strategies for DDTMD noise. The precision at the time was deemed more than adequate. It is very timely that you bring up this subject now, because I hope to start looking at ways to optimize phase noise in WR in the coming months, and noise coming from the DDMTD phase detector is definitely something I want to look at. I will be very interested in your ideas and findings regarding optimal strategies for the de-glitcher. Hi Simon and Javier, I arrive late to this discussion but I would like to add my grain of salt. As Javier says there was not a detailed optimization of the DDMTD architecture as jitter was already limited by all the surrounding electronics. I would like to add that much of the noise rejection is due to the implementation of a median estimator for the incoming edge position respect to the slightly-offset oscillator. It is easy and fun to proof that this median estimator can be implemented with a counter counting the number of sampled zeros and a simple state machine state machine that places counter start in a safe zone. In fact, when you think it out, the most curious thing is that this algorithm is nothing more than a sort of generalization of the bang-bang architecture to measure phase offsets. Cheers, Pablo ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Digital Mixing with a BeagleBone Black and D Flip Flop
http://trs-new.jpl.nasa.gov/dspace/bitstream/2014/36903/1/01-2617.pdf among other things illustrates a modified approach to the offset generator by replacing the intermediate phase locked VCXO with a bandpass filter. Bruce On Thursday, October 16, 2014 1:03 PM, Bert Kehren via time-nuts time-nuts@febo.com wrote: Take a look at Potato chips yes Potato I have used them with good results Bert Kehren 330551715157 In a message dated 10/15/2014 6:44:47 P.M. Eastern Daylight Time, kb...@n1k.org writes: Hi Most ECL families have more trouble with 1/F noise than fast silicon saturated logic. That makes them poor candidates for this sort of thing. Bob On Oct 15, 2014, at 9:13 AM, Gerhard Hoffmann dk...@arcor.de wrote: Am 15.10.2014 um 11:29 schrieb Bruce Griffiths: Typically a 74HC164 shift register has internal cycle to cycle sampling jitter of about 4ps or so when used as a mixer, a 74AC device has about 1/4 of this jitter or around 1ps. Faster CMOS devices have even less internal jitter. Hi, do you have any data on MC100EP51 friends? In the datasheet they seem to claim sth. in the low ps also, which would be disappointing in comparison to 74AC or 74LVC regards, Gerhard ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Digital Mixing with a BeagleBone Black and D Flip Flop
Hi I wonder what they are using for the “lpf / zero crossers” in that version. Bob On Oct 16, 2014, at 4:07 AM, Bruce Griffiths bruce.griffi...@xtra.co.nz wrote: http://trs-new.jpl.nasa.gov/dspace/bitstream/2014/36903/1/01-2617.pdf among other things illustrates a modified approach to the offset generator by replacing the intermediate phase locked VCXO with a bandpass filter. Bruce On Thursday, October 16, 2014 1:03 PM, Bert Kehren via time-nuts time-nuts@febo.com wrote: Take a look at Potato chips yes Potato I have used them with good results Bert Kehren 330551715157 In a message dated 10/15/2014 6:44:47 P.M. Eastern Daylight Time, kb...@n1k.org writes: Hi Most ECL families have more trouble with 1/F noise than fast silicon saturated logic. That makes them poor candidates for this sort of thing. Bob On Oct 15, 2014, at 9:13 AM, Gerhard Hoffmann dk...@arcor.de wrote: Am 15.10.2014 um 11:29 schrieb Bruce Griffiths: Typically a 74HC164 shift register has internal cycle to cycle sampling jitter of about 4ps or so when used as a mixer, a 74AC device has about 1/4 of this jitter or around 1ps. Faster CMOS devices have even less internal jitter. Hi, do you have any data on MC100EP51 friends? In the datasheet they seem to claim sth. in the low ps also, which would be disappointing in comparison to 74AC or 74LVC regards, Gerhard ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Digital Mixing with a BeagleBone Black and D Flip Flop
On 10/16/14, 3:59 AM, Bob Camp wrote: Hi I wonder what they are using for the “lpf / zero crossers” in that version. Aren't those the usual limiter chain? Described in earlier papers by the same folks. There was a lot of discussion about this architecture on the list a few years ago. https://www.febo.com/pipermail/time-nuts/2006-October/021837.html Here's something you might want to take a look at: http://www.wriley.com/A%20Small%20DMTD%20System.pdf By the way.. here's the reference from the list Dick / Kuhnle / Sydnor: Zero-crossing detector with sub microsecond jitter and crosstalk http://tycho.usno.navy.mil/ptti/1990papers/Vol%2022_20.pdf www.dtic.mil/cgi-bin/GetTRDoc?AD=ADA515384 the paper http://www.dtic.mil/cgi-bin/GetTRDoc?AD=ADA239372 the entire PTTI proceedings ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Digital Mixing with a BeagleBone Black and D Flip Flop
Am 16.10.2014 um 02:02 schrieb Bert Kehren via time-nuts: Take a look at Potato chips yes Potato I have used them with good results Bert Kehren 330551715157 They don't impress me much. Yes, they can drive my 0.6pF active probes without a problem, but connecting just one of their own inputs to an output slows it down to half speed. The word line driver for their '125 seems somewhat optimistic. Propagation delay vs. load capacitance could be a problem with them. In a message dated 10/15/2014 6:44:47 P.M. Eastern Daylight Time, kb...@n1k.org writes: Hi Most ECL families have more trouble with 1/F noise than fast silicon saturated logic. That makes them poor candidates for this sort of thing. Motorola's Mosaic3 process was really ugly, and with PECL you get all the VCC noise unattenuated to the output in the high state. But is is seldom that MOSFETs outdo bipolars wrt 1/f corners. I think I'll give the 100EP a try. Gerhard ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Digital Mixing with a BeagleBone Black and D Flip Flop
Hi I guess I should have been a bit more specific. The latest paper is from about 10 years after their papers on limiters. I wonder if they have any “new stuff” in the limiter part of the new(er) system. I also wonder if there’s been any progress in the 8 years since the latest paper. Bob On Oct 16, 2014, at 8:22 AM, Jim Lux jim...@earthlink.net wrote: On 10/16/14, 3:59 AM, Bob Camp wrote: Hi I wonder what they are using for the “lpf / zero crossers” in that version. Aren't those the usual limiter chain? Described in earlier papers by the same folks. There was a lot of discussion about this architecture on the list a few years ago. https://www.febo.com/pipermail/time-nuts/2006-October/021837.html Here's something you might want to take a look at: http://www.wriley.com/A%20Small%20DMTD%20System.pdf By the way.. here's the reference from the list Dick / Kuhnle / Sydnor: Zero-crossing detector with sub microsecond jitter and crosstalk http://tycho.usno.navy.mil/ptti/1990papers/Vol%2022_20.pdf www.dtic.mil/cgi-bin/GetTRDoc?AD=ADA515384 the paper http://www.dtic.mil/cgi-bin/GetTRDoc?AD=ADA239372 the entire PTTI proceedings ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Digital Mixing with a BeagleBone Black and D Flip Flop
Hi Well, been there / done that in this case. The 100EP noise floor is nothing exciting. It’s 1/F corner isn’t very impressive either. Bob On Oct 16, 2014, at 12:23 PM, Gerhard Hoffmann dk...@arcor.de wrote: Am 16.10.2014 um 02:02 schrieb Bert Kehren via time-nuts: Take a look at Potato chips yes Potato I have used them with good results Bert Kehren 330551715157 They don't impress me much. Yes, they can drive my 0.6pF active probes without a problem, but connecting just one of their own inputs to an output slows it down to half speed. The word line driver for their '125 seems somewhat optimistic. Propagation delay vs. load capacitance could be a problem with them. In a message dated 10/15/2014 6:44:47 P.M. Eastern Daylight Time, kb...@n1k.org writes: Hi Most ECL families have more trouble with 1/F noise than fast silicon saturated logic. That makes them poor candidates for this sort of thing. Motorola's Mosaic3 process was really ugly, and with PECL you get all the VCC noise unattenuated to the output in the high state. But is is seldom that MOSFETs outdo bipolars wrt 1/f corners. I think I'll give the 100EP a try. Gerhard ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
[time-nuts] Digital Mixing with a BeagleBone Black and D Flip Flop
The use of a synchroniser loses no information apart from fine details about the metastability response of the sampling flipflop. With a 10Hz offset and a 10MHz clock the sampling resolution is 100fs with the phase difference between the flipflop clock and data input transitions changing monotonically by 100fs between successive active clock transitions. Phase noise/jitter between the flipflop and data input transitions will typically result in a burst of state transitions at the synchroniser output rather than a single transition when the active clock transition and a data transition coincide.. Typically a 74HC164 shift register has internal cycle to cycle sampling jitter of about 4ps or so when used as a mixer, a 74AC device has about 1/4 of this jitter or around 1ps. Faster CMOS devices have even less internal jitter. Bruce ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Digital Mixing with a BeagleBone Black and D Flip Flop
Hi Simon, I am the initiator and leader of the White Rabbit project, which in the context of these discussions is more a disqualifier than anything, since I do very little technical work these days, unfortunately. Please forgive me if I have misunderstood what you are trying to do. Some tentative answers below: On Wed, Oct 15, 2014 at 1:58 PM, Simon Marsh subscripti...@burble.com wrote: On 15/10/2014 10:29, Bruce Griffiths wrote: The use of a synchroniser loses no information apart from fine details about the metastability response of the sampling flipflop. With a 10Hz offset and a 10MHz clock the sampling resolution is 100fs with the phase difference between the flipflop clock and data input transitions changing monotonically by 100fs between successive active clock transitions. Phase noise/jitter between the flipflop and data input transitions will typically result in a burst of state transitions at the synchroniser output rather than a single transition when the active clock transition and a data transition coincide.. Right, this is my understanding of what the white rabbit articles refers to as glitching and is why I know I have something wrong when I see no noise at all. Do you have a precise idea of what the offset in frequency is between your DUT(s) and the slightly-offset oscillator? If that offset is too big compared with the jitter of your clock signals and your flip-flops, that would explain why you see no glitches. Locking to your DUT frequency is a good way to make sure you control the offset. Small frequency offsets are typically implemented by multiplying by (N-1)/N with N big enough. There is a trick (from NIST I think) for achieving high N by cascading two PLLs which multiply by M-1 and M+1 respectively. The effective multiplication factor is then (M^2 - 1). Making M^2=N and inserting the divide-by-N in between the multipliers gives you the global (N-1)/N. We don't use this trick, but it can be handy in some circumstances. BTW, does anybody have a pointer to the original reference for it? What I'm less sure about is what I should expect to see as the clock/data phase steps through the unstable region of the sampling flip flop's response. Whilst the synchroniser will ensure I get an output of some sort at each cycle, its going to take many cycles @100fs to step through before the sampling flip flop is stable again. Is this likely to appear as (random?) state transitions at the synchroniser output ? perhaps this region just gets lost in the mush of clock jitter ? You should indeed use a synchronizer made of a chain of FFs of length at least two. You should see the typical glitch pattern after the first FF and also after the second, i.e. what you should see in an oscilloscope should pretty much look the same for both FF outputs. Only in the very infrequent cases where you hit the metastability window of the first FF there should be a difference between what you see after the first FF and after the second one (except of course for the fixed one cycle latency). Notice I am abusing the word 'glitch'. These are pulses of at least one clock cycle duration. The current implementation used in WR was developed by Tomasz Wlostowski in the frame of his MSc thesis, following the ideas of Pablo Alvarez which Bruce pointed to earlier. As you can see in Tomasz's dissertation [1], there was not a lot of investigation on optimal strategies for DDTMD noise. The precision at the time was deemed more than adequate. It is very timely that you bring up this subject now, because I hope to start looking at ways to optimize phase noise in WR in the coming months, and noise coming from the DDMTD phase detector is definitely something I want to look at. I will be very interested in your ideas and findings regarding optimal strategies for the de-glitcher. Cheers, Javier [1] http://www.ohwr.org/documents/80 ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Digital Mixing with a BeagleBone Black and D Flip Flop
Am 15.10.2014 um 11:29 schrieb Bruce Griffiths: Typically a 74HC164 shift register has internal cycle to cycle sampling jitter of about 4ps or so when used as a mixer, a 74AC device has about 1/4 of this jitter or around 1ps. Faster CMOS devices have even less internal jitter. Hi, do you have any data on MC100EP51 friends? In the datasheet they seem to claim sth. in the low ps also, which would be disappointing in comparison to 74AC or 74LVC regards, Gerhard ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Digital Mixing with a BeagleBone Black and D Flip Flop
Javier, I'm merely implementing a poor man's copy of the ideas in the White Rabbit project, so thank you for taking the time to post. On 15/10/2014 14:27, Javier Serrano wrote: [snip] Do you have a precise idea of what the offset in frequency is between your DUT(s) and the slightly-offset oscillator? If that offset is too big compared with the jitter of your clock signals and your flip-flops, that would explain why you see no glitches. At the moment I'm very simply using an 'ebay standard' micro crystal ocxo as the offset oscillator, which can tune to about +/-66hz of 10mhz. My DUT is then a 10mhz TCXO. These are not time nut standard by any means, so I do expect to get glitches and lots of them. The lack of glitches (even down to a 5hz beat note) indicates a problem and it's a very reasonable assumption that this is down to my setup. The next steps will be to clean up my hardware and see how it goes. As an aside, whilst I clean up the hardware, Mr Postman should have time to deliver something a bit more time-nuttery to play with :) You should indeed use a synchronizer made of a chain of FFs of length at least two. You should see the typical glitch pattern after the first FF and also after the second, i.e. what you should see in an oscilloscope should pretty much look the same for both FF outputs. Only in the very infrequent cases where you hit the metastability window of the first FF there should be a difference between what you see after the first FF and after the second one (except of course for the fixed one cycle latency). I'm thinking that with a discrete 74AC74 part rather than an FPGA, it's going to be much more frequent (and perhaps a certainty?) that I'll hit the metastability window for an extended period ? Ultimately I suspect this might be where the limit is for my approach and where Bob D will get more accuracy with the FPGA approach. As you can see in Tomasz's dissertation [1], there was not a lot of investigation on optimal strategies for DDTMD noise. The precision at the time was deemed more than adequate. It is very timely that you bring up this subject now, because I hope to start looking at ways to optimize phase noise in WR in the coming months, and noise coming from the DDMTD phase detector is definitely something I want to look at. I will be very interested in your ideas and findings regarding optimal strategies for the de-glitcher. I'm quite unlikely to come up with anything that an undergrad and a few hours couldn't think up. However, thank you for linking to the paper, for some reason I'd missed it in my Googling. On the minus side, the paper confirmed that I had completely misunderstood the 'zero count algorithm' as it had been described in the short summary I'd seen. On the plus side, I'd already been playing around with something similar to the 'bit value median' that is really being used, so it's good to know I was actually on the right track. (For completeness, what I was actually doing was adding zeros and subtracting ones, then taking the edge at the point of maximum value). Cheers Simon ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Digital Mixing with a BeagleBone Black and D Flip Flop
On Wednesday, October 15, 2014 03:27:41 PM Javier Serrano wrote: Do you have a precise idea of what the offset in frequency is between your DUT(s) and the slightly-offset oscillator? If that offset is too big compared with the jitter of your clock signals and your flip-flops, that would explain why you see no glitches. Locking to your DUT frequency is a good way to make sure you control the offset. Small frequency offsets are typically implemented by multiplying by (N-1)/N with N big enough. There is a trick (from NIST I think) for achieving high N by cascading two PLLs which multiply by M-1 and M+1 respectively. The effective multiplication factor is then (M^2 - 1). Making M^2=N and inserting the divide-by-N in between the multipliers gives you the global (N-1)/N. We don't use this trick, but it can be handy in some circumstances. BTW, does anybody have a pointer to the original reference for it? JPL used this in an early version of the offset source for their frequency stability analyser. Starting with a 100MHz clock both the 100MHz and 100MHZ/N were used to drive a LSB (lower sideband mixer) a low noise VCXO is phase locked via the LSB mixer output. The VCXO output and VCXO/N is fed to a USB mixer and the final low noise VCXO is locked via this mixer output to a frequency of 100MHz(1-1/N^2). I'll try and retrieve a link to this paper (by Greenhall??). Bruce The current implementation used in WR was developed by Tomasz Wlostowski in the frame of his MSc thesis, following the ideas of Pablo Alvarez which Bruce pointed to earlier. As you can see in Tomasz's dissertation [1], there was not a lot of investigation on optimal strategies for DDTMD noise. The precision at the time was deemed more than adequate. It is very timely that you bring up this subject now, because I hope to start looking at ways to optimize phase noise in WR in the coming months, and noise coming from the DDMTD phase detector is definitely something I want to look at. I will be very interested in your ideas and findings regarding optimal strategies for the de-glitcher. Cheers, The LTC6957 appears to have significantly lower phase noise (and hence jitter) than the comparator circuit. Its performance at 10MHz appears comparable to that of the Holzworth HX2410. The LTC6957 close in phase noise (with 10MHz input) is better than indicated on the datasheet at least according to my measurements with a Timepod. Bruce Javier [1] http://www.ohwr.org/documents/80 ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Digital Mixing with a BeagleBone Black and D Flip Flop
Hi Simon, I need to find some spare time, something which is not in rich volumen right now. Cheers, Magnus On 10/15/2014 09:53 AM, Simon Marsh wrote: Hi Magnus, What was the outcome ? Did it work, and what were the constraints or problems encountered ? Cheers Simon On 15/10/2014 00:52, Magnus Danielson wrote: Tom, I think I wrote some VHDL code for a project like this... if I should dig it out again? Cheers, Magnus On 10/14/2014 11:19 PM, Tom Van Baak wrote: Hi Simon, Some additional info. I first heard about the D-FF method of frequency comparison in the late 90's (from Rick Hambly, I think) on the old gps mailing list. It sounded really interesting. Since then, the subject has turned up every few years on this list. But each time, the topic seems to go away quietly with little or no data, plots or explanation. In addition, none of the commercial products I've taken apart appear to use this approach. Hmm. So that begs the question -- what's really going on, and why. I'm enjoying this thread because you've shown both technical competence and optimistic persistence. Perhaps once and for all, with your efforts, we can settle this matter. You will either find a working combination with excellent performance, or you will uncover enough uncontrolled variables that you never want to try it again. Either way, we all learn a lot. Keep the photos, data, and plots coming. Thanks, /tvb ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Digital Mixing with a BeagleBone Black and D Flip Flop
Hi Most ECL families have more trouble with 1/F noise than fast silicon saturated logic. That makes them poor candidates for this sort of thing. Bob On Oct 15, 2014, at 9:13 AM, Gerhard Hoffmann dk...@arcor.de wrote: Am 15.10.2014 um 11:29 schrieb Bruce Griffiths: Typically a 74HC164 shift register has internal cycle to cycle sampling jitter of about 4ps or so when used as a mixer, a 74AC device has about 1/4 of this jitter or around 1ps. Faster CMOS devices have even less internal jitter. Hi, do you have any data on MC100EP51 friends? In the datasheet they seem to claim sth. in the low ps also, which would be disappointing in comparison to 74AC or 74LVC regards, Gerhard ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Digital Mixing with a BeagleBone Black and D Flip Flop
Take a look at Potato chips yes Potato I have used them with good results Bert Kehren 330551715157 In a message dated 10/15/2014 6:44:47 P.M. Eastern Daylight Time, kb...@n1k.org writes: Hi Most ECL families have more trouble with 1/F noise than fast silicon saturated logic. That makes them poor candidates for this sort of thing. Bob On Oct 15, 2014, at 9:13 AM, Gerhard Hoffmann dk...@arcor.de wrote: Am 15.10.2014 um 11:29 schrieb Bruce Griffiths: Typically a 74HC164 shift register has internal cycle to cycle sampling jitter of about 4ps or so when used as a mixer, a 74AC device has about 1/4 of this jitter or around 1ps. Faster CMOS devices have even less internal jitter. Hi, do you have any data on MC100EP51 friends? In the datasheet they seem to claim sth. in the low ps also, which would be disappointing in comparison to 74AC or 74LVC regards, Gerhard ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Digital Mixing with a BeagleBone Black and D Flip Flop
You beat me :) http://www.potatosemi.com/ They sell low quantities thru Ebay, like this: http://www.ebay.com/itm/7400-G-Series-GHz-TTL-CMOS-logic-IC-14pin-SOIC-QTY-1-/330772425575?pt=LH_DefaultDomain_0hash=item4d0392ab67 Daniel On 15/10/2014 21:02, Bert Kehren via time-nuts wrote: Take a look at Potato chips yes Potato I have used them with good results Bert Kehren 330551715157 In a message dated 10/15/2014 6:44:47 P.M. Eastern Daylight Time, kb...@n1k.org writes: Hi Most ECL families have more trouble with 1/F noise than fast silicon saturated logic. That makes them poor candidates for this sort of thing. Bob On Oct 15, 2014, at 9:13 AM, Gerhard Hoffmann dk...@arcor.de wrote: Am 15.10.2014 um 11:29 schrieb Bruce Griffiths: Typically a 74HC164 shift register has internal cycle to cycle sampling jitter of about 4ps or so when used as a mixer, a 74AC device has about 1/4 of this jitter or around 1ps. Faster CMOS devices have even less internal jitter. Hi, do you have any data on MC100EP51 friends? In the datasheet they seem to claim sth. in the low ps also, which would be disappointing in comparison to 74AC or 74LVC regards, Gerhard ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Digital Mixing with a BeagleBone Black and D Flip Flop
Hi Is it silicon or is it something more exotic? In general, exotic is not good for 1/F noise. Bob On Oct 15, 2014, at 9:36 PM, Daniel Mendes dmend...@gmail.com wrote: You beat me :) http://www.potatosemi.com/ They sell low quantities thru Ebay, like this: http://www.ebay.com/itm/7400-G-Series-GHz-TTL-CMOS-logic-IC-14pin-SOIC-QTY-1-/330772425575?pt=LH_DefaultDomain_0hash=item4d0392ab67 Daniel On 15/10/2014 21:02, Bert Kehren via time-nuts wrote: Take a look at Potato chips yes Potato I have used them with good results Bert Kehren 330551715157 In a message dated 10/15/2014 6:44:47 P.M. Eastern Daylight Time, kb...@n1k.org writes: Hi Most ECL families have more trouble with 1/F noise than fast silicon saturated logic. That makes them poor candidates for this sort of thing. Bob On Oct 15, 2014, at 9:13 AM, Gerhard Hoffmann dk...@arcor.de wrote: Am 15.10.2014 um 11:29 schrieb Bruce Griffiths: Typically a 74HC164 shift register has internal cycle to cycle sampling jitter of about 4ps or so when used as a mixer, a 74AC device has about 1/4 of this jitter or around 1ps. Faster CMOS devices have even less internal jitter. Hi, do you have any data on MC100EP51 friends? In the datasheet they seem to claim sth. in the low ps also, which would be disappointing in comparison to 74AC or 74LVC regards, Gerhard ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Digital Mixing with a BeagleBone Black and D Flip Flop
kb...@n1k.org said: Is it silicon or is it something more exotic? In general, exotic is not good for 1/F noise. Data sheets say submicron CMOS. -- These are my opinions. I hate spam. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Digital Mixing with a BeagleBone Black and D Flip Flop
Many thanks to Bob D, Bob C, Bruce and Magnus for the links, references and being patient. I've spent a bit of time looking at the glitching with the idea of evaluating a few different algorithms to deal with it. I also looked a bit at the hardware and instead of very simply having a single D-flop doing the sampling, I now have the 2 D-flops in a 74AC74 wired in series so that one does the sampling and the other acts as a shift register before the output is sent on to the BBB. I got so far with this before realising that one of the D-flops was being much more noisy than the other and indeed it was only a single output that was particularly noisy. Switching to the inverted output reduced the noise considerably. After a bit of head scratching I swapped the part with the result that _all_ the glitches vanished. Completely. Even at small beat frequencies (5hz). So, I've managed to go from one extreme to the other. I believe I should be seeing _some_ glitching, so would appreciate any pointers as to what now might be hiding it or how I could diagnose what is going on ? The discussion on slew rates was interesting, I still have this knocked up on some pluggable breadboard, the slew rate is going to be poor and could easily be a contributing factor. Is it possible that poor slew rates mean I have quite a large 'dead zone' when the clock and data edges are co-incident (and where the flip flop is unable to effectively sample) and this is large enough to be masking any intrinsic oscillator noise ? Cheers Simon ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Digital Mixing with a BeagleBone Black and D Flip Flop
two D-flops in series make a synchronizer!? (see the input-channels on Nutt-type time interval counters) http://chipdesignmag.com/print.php?articleId=32?issueId=5 you've lost all your noise - but you've also got rid of all the signal - so not great for improving SNR. On Tue, Oct 14, 2014 at 6:32 PM, Simon Marsh subscripti...@burble.com wrote: I now have the 2 D-flops in a 74AC74 wired in series so that one does the sampling and the other acts as a shift register before the output is sent on to the BBB. I got so far with this before realising that one of the D-flops was being much more noisy than the other and indeed it was only a single output that was particularly noisy. Switching to the inverted output reduced the noise considerably. After a bit of head scratching I swapped the part with the result that _all_ the glitches vanished. Completely. Even at small beat frequencies (5hz). ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Digital Mixing with a BeagleBone Black and D Flip Flop
Yes, I do understand I'm asking for trouble, though I kinda expected to see more noise rather than less. I guess its time to break out the soldering iron. Cheers Simon On 14/10/2014 17:22, Robert LaJeunesse wrote: Using 74AC parts on what I think of as a pluggable breadboard (e.g. http://uk.farnell.com/jsp/search/productdetail.jsp?SKU=2295705MER=bn-me-ca-r1-best-sto-5) is asking for trouble. The parts are RF fast and the pluggable board has not very good contact resistance and certainly more inductance and shunt capacitance than is good for RF. I would highly recommend using dead-bug style on a solid copper plane, as provided by a chunk of unetched PCB material. (Jim Williams did a few like that, see http://1.bp.blogspot.com/-y3xQiBHHzaQ/UP3mLk96qWI/Ass/ZvPbfN8lmTQ/s1600/eep114.jpg.) This approach allows for extremely short lead lengths and power supply bypassing (to the plane) with a near zero lead length capacitor. Bob L. Sent: Tuesday, October 14, 2014 at 11:32 AM From: Simon Marsh subscripti...@burble.com To: Discussion of precise time and frequency measurement time-nuts@febo.com Subject: Re: [time-nuts] Digital Mixing with a BeagleBone Black and D Flip Flop ... 74AC74 ... knocked up on some pluggable breadboard ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Digital Mixing with a BeagleBone Black and D Flip Flop
Hi Simon, Some additional info. I first heard about the D-FF method of frequency comparison in the late 90's (from Rick Hambly, I think) on the old gps mailing list. It sounded really interesting. Since then, the subject has turned up every few years on this list. But each time, the topic seems to go away quietly with little or no data, plots or explanation. In addition, none of the commercial products I've taken apart appear to use this approach. Hmm. So that begs the question -- what's really going on, and why. I'm enjoying this thread because you've shown both technical competence and optimistic persistence. Perhaps once and for all, with your efforts, we can settle this matter. You will either find a working combination with excellent performance, or you will uncover enough uncontrolled variables that you never want to try it again. Either way, we all learn a lot. Keep the photos, data, and plots coming. Thanks, /tvb - Original Message - From: Simon Marsh subscripti...@burble.com To: time-nuts@febo.com Sent: Tuesday, October 14, 2014 9:34 AM Subject: Re: [time-nuts] Digital Mixing with a BeagleBone Black and D Flip Flop Yes, I do understand I'm asking for trouble, though I kinda expected to see more noise rather than less. I guess its time to break out the soldering iron. Cheers Simon ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Digital Mixing with a BeagleBone Black and D Flip Flop
Hi Some of the “cheap printed circuit board outfits are now economical enough that they are a pretty good way to, go even for a fairly speculative breadboard type circuit. You wind up with a double sided board with a good ground. That significantly reduces the guesses and gotcha’s. There have been numerous threads here on the list about who likes which vendor and just how cheap is cheap. — One example of a gotcha - ground bounce may be responsible for the odd behavior when switching from the Q to the Q bar output on the flip flops. Bob On Oct 14, 2014, at 12:34 PM, Simon Marsh subscripti...@burble.com wrote: Yes, I do understand I'm asking for trouble, though I kinda expected to see more noise rather than less. I guess its time to break out the soldering iron. Cheers Simon On 14/10/2014 17:22, Robert LaJeunesse wrote: Using 74AC parts on what I think of as a pluggable breadboard (e.g. http://uk.farnell.com/jsp/search/productdetail.jsp?SKU=2295705MER=bn-me-ca-r1-best-sto-5) is asking for trouble. The parts are RF fast and the pluggable board has not very good contact resistance and certainly more inductance and shunt capacitance than is good for RF. I would highly recommend using dead-bug style on a solid copper plane, as provided by a chunk of unetched PCB material. (Jim Williams did a few like that, see http://1.bp.blogspot.com/-y3xQiBHHzaQ/UP3mLk96qWI/Ass/ZvPbfN8lmTQ/s1600/eep114.jpg.) This approach allows for extremely short lead lengths and power supply bypassing (to the plane) with a near zero lead length capacitor. Bob L. Sent: Tuesday, October 14, 2014 at 11:32 AM From: Simon Marsh subscripti...@burble.com To: Discussion of precise time and frequency measurement time-nuts@febo.com Subject: Re: [time-nuts] Digital Mixing with a BeagleBone Black and D Flip Flop ... 74AC74 ... knocked up on some pluggable breadboard ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Digital Mixing with a BeagleBone Black and D Flip Flop
Tom, I think I wrote some VHDL code for a project like this... if I should dig it out again? Cheers, Magnus On 10/14/2014 11:19 PM, Tom Van Baak wrote: Hi Simon, Some additional info. I first heard about the D-FF method of frequency comparison in the late 90's (from Rick Hambly, I think) on the old gps mailing list. It sounded really interesting. Since then, the subject has turned up every few years on this list. But each time, the topic seems to go away quietly with little or no data, plots or explanation. In addition, none of the commercial products I've taken apart appear to use this approach. Hmm. So that begs the question -- what's really going on, and why. I'm enjoying this thread because you've shown both technical competence and optimistic persistence. Perhaps once and for all, with your efforts, we can settle this matter. You will either find a working combination with excellent performance, or you will uncover enough uncontrolled variables that you never want to try it again. Either way, we all learn a lot. Keep the photos, data, and plots coming. Thanks, /tvb - Original Message - From: Simon Marsh subscripti...@burble.com To: time-nuts@febo.com Sent: Tuesday, October 14, 2014 9:34 AM Subject: Re: [time-nuts] Digital Mixing with a BeagleBone Black and D Flip Flop Yes, I do understand I'm asking for trouble, though I kinda expected to see more noise rather than less. I guess its time to break out the soldering iron. Cheers Simon ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Digital Mixing with a BeagleBone Black and D Flip Flop
Bruce, Thanks, I recall the thread from reading the digests. The CERN code is wonderfully compact but not immediately obvious to a novice to VHDL. Perhaps one day the light will come on. Bob On 10/12/2014 12:27 AM, Bruce Griffiths wrote: Original thread on DDMTD in 2008: https://www.febo.com/pipermail/time-nuts/2008-December/034955.html Later comment on using a shift register to minimise metastability issues: https://www.febo.com/pipermail/time-nuts/2011-August/058648.html Bruce On Sunday, October 12, 2014 12:14:27 AM Robert Darby wrote: Bob Camp, Bob, Simon is talking about the sampler versus a true mixer. This is the idea I asked you about some months ago when I asked about how the digital filter functions. You were kind to explain the filter method in terms of buckets. You are of course correct that the resolution is low, 100 ns for a 10 MHz DUT with a 10 Hz frequency offset but the hetrodyne factor takes the theoretical resolution to 100 fs. That's not shabby for a very low cost DDMTD. And of course, the actual noise floor will not be close to this but potentially it's better than a 5370 and a lot easier to maintain. :o) Simon, I have a 4 channel 1 ns tagger working but I can't successfully link the FTDI library to a c program so doing this in hardware looks far more attractive to me. Here's how I see it at this point: -- Objective: --A four channel DDMTD with 44 bit time tags delivered over the USB port --At least 100 Hz beat frquency on each channel --The hardware is capable of much higher rates but increasing the beat frequency offset --degrades resolution and realistically the device will probably be used at 5 or 10 Hz -- -- Additional Hardware Required: --A wing with three or five LTC6957-1 low phase noise buffers to convert sine inputs into --high speed low-jitter square waves using LVPECL differential outputs --Either an oscillator offset by the beat frequency or a DDS frequency generator --A USB equipped computer -- --Architecture --Differential inputs are fed to the master clock, thence to the D flip-flops clocks --Differential inputs for each channel are fed to the data inputs for each flip-flop --The master clock drives a 44 bit counter which is common to all four channels --Each channel has two independent counters, provisionally 14 bit, designated high and low --The low counter first establishes a low state without transitions i.e. it times out --After the low counter times out, the flip-flop is armed --The first high output at q resets and starts both high and low counters - whichever counts depends on whether q is high or low --Every time the high and low counters match we store the 44 bit count; each new match replaces the previous one --At some point (2^14 highs) the high counter will roll over - hopefully low will have stopped counting much earlier --The highest stored match should meet the equal count criteria as described in the P. Moreira and I. Darwazeh paper --Since there are four channels it will be necessary to multiplex the time tags into the fifo --The multiplexer will add 1 bit per channel for one-hot channel id coding --The 48 bits will clock into a 48 bit to 8 bit fifo thence to an 8 bit USB port I believe you can have multiple points where the two counts match but I don't have any data to confirm that. I played with this in excel and when you feed it ones and zeros in a distribution that looks like the typical output out of a digital sampler it is possible to get multiple matches. My intention is to go with the last crossing and the scheme mentioned above does this rather trivially. Unless, of course, I'm missing something and I usually do. I've got a Pipistrello board and it has the option of an asynchronous fifo USB interface; since I've already paid my dues on that I'll just use that code again. The data rate is so low that snail mail would work. The computer gets a series of time tags and your program has to pair up the channels to get the deltas. Getting time tags lets you compare three or four devices simultaneously and facilitates three-cornered hat calculations. I suspect that's a lot easier to say than do but we'll cross that bridge if we ever get there. Also time tags permit continuous sampling; there's no counter dead-time which I think can be an issue when it causes variable data sampling rates. Bob Camp mention Collins low jitter hard limiters but I suspect that's much more of an issue on the very shallow slopes you see on 5 or 10 Hz mixer outputs. The LTC6957 is probably overkill on 10 MHz inputs but I believe they're a tad better than a 74AC gate, but then again maybe not all that much better. Lot more expensive. Bob C discussed sine to square conversion in a recent post (IIRC) perhaps in connection with 5V to 3.3V conversion, and for a low cost
Re: [time-nuts] Digital Mixing with a BeagleBone Black and D Flip Flop
Hi With *all* of these “drop to a lower frequency” approaches, the theoretical resolution is very good compared to the useful resolution. A straight mix to 1 Hz into a 5370 is a great example. The filter / limiter is the thing that sets the useful resolution rather than the theoretical 1x10^-17 the setup provides. Bob On Oct 12, 2014, at 12:14 AM, Robert Darby bobda...@triad.rr.com wrote: Bob Camp, Bob, Simon is talking about the sampler versus a true mixer. This is the idea I asked you about some months ago when I asked about how the digital filter functions. You were kind to explain the filter method in terms of buckets. You are of course correct that the resolution is low, 100 ns for a 10 MHz DUT with a 10 Hz frequency offset but the hetrodyne factor takes the theoretical resolution to 100 fs. That's not shabby for a very low cost DDMTD. And of course, the actual noise floor will not be close to this but potentially it's better than a 5370 and a lot easier to maintain. :o) Simon, I have a 4 channel 1 ns tagger working but I can't successfully link the FTDI library to a c program so doing this in hardware looks far more attractive to me. Here's how I see it at this point: -- Objective: --A four channel DDMTD with 44 bit time tags delivered over the USB port --At least 100 Hz beat frquency on each channel --The hardware is capable of much higher rates but increasing the beat frequency offset --degrades resolution and realistically the device will probably be used at 5 or 10 Hz -- -- Additional Hardware Required: --A wing with three or five LTC6957-1 low phase noise buffers to convert sine inputs into --high speed low-jitter square waves using LVPECL differential outputs --Either an oscillator offset by the beat frequency or a DDS frequency generator --A USB equipped computer -- --Architecture --Differential inputs are fed to the master clock, thence to the D flip-flops clocks --Differential inputs for each channel are fed to the data inputs for each flip-flop --The master clock drives a 44 bit counter which is common to all four channels --Each channel has two independent counters, provisionally 14 bit, designated high and low --The low counter first establishes a low state without transitions i.e. it times out --After the low counter times out, the flip-flop is armed --The first high output at q resets and starts both high and low counters - whichever counts depends on whether q is high or low --Every time the high and low counters match we store the 44 bit count; each new match replaces the previous one --At some point (2^14 highs) the high counter will roll over - hopefully low will have stopped counting much earlier --The highest stored match should meet the equal count criteria as described in the P. Moreira and I. Darwazeh paper --Since there are four channels it will be necessary to multiplex the time tags into the fifo --The multiplexer will add 1 bit per channel for one-hot channel id coding --The 48 bits will clock into a 48 bit to 8 bit fifo thence to an 8 bit USB port I believe you can have multiple points where the two counts match but I don't have any data to confirm that. I played with this in excel and when you feed it ones and zeros in a distribution that looks like the typical output out of a digital sampler it is possible to get multiple matches. My intention is to go with the last crossing and the scheme mentioned above does this rather trivially. Unless, of course, I'm missing something and I usually do. I've got a Pipistrello board and it has the option of an asynchronous fifo USB interface; since I've already paid my dues on that I'll just use that code again. The data rate is so low that snail mail would work. The computer gets a series of time tags and your program has to pair up the channels to get the deltas. Getting time tags lets you compare three or four devices simultaneously and facilitates three-cornered hat calculations. I suspect that's a lot easier to say than do but we'll cross that bridge if we ever get there. Also time tags permit continuous sampling; there's no counter dead-time which I think can be an issue when it causes variable data sampling rates. Bob Camp mention Collins low jitter hard limiters but I suspect that's much more of an issue on the very shallow slopes you see on 5 or 10 Hz mixer outputs. The LTC6957 is probably overkill on 10 MHz inputs but I believe they're a tad better than a 74AC gate, but then again maybe not all that much better. Lot more expensive. Bob C discussed sine to square conversion in a recent post (IIRC) perhaps in connection with 5V to 3.3V conversion, and for a low cost solution the 74AC gate
Re: [time-nuts] Digital Mixing with a BeagleBone Black and D Flip Flop
Interesting 2008 discussion on using a sound-card ADC for a DMTD system! Did anyone build a DMTD-system and measure the performance using a 24-bit soundcard? Does it matter that the ADC in the sound-card is probably clocked by a crystal clock that is 50ppm off and has bad ADEV? Anders On Sun, Oct 12, 2014 at 7:27 AM, Bruce Griffiths bruce.griffi...@xtra.co.nz wrote: Original thread on DDMTD in 2008: https://www.febo.com/pipermail/time-nuts/2008-December/034955.html Later comment on using a shift register to minimise metastability issues: https://www.febo.com/pipermail/time-nuts/2011-August/058648.html Bruce ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Digital Mixing with a BeagleBone Black and D Flip Flop
anders.e.e.wal...@gmail.com said: Does it matter that the ADC in the sound-card is probably clocked by a crystal clock that is 50ppm off and has bad ADEV? You can calibrate the clock on the ADC. One way is to feed a known reference frequency in on the other channel. (That's assuming you have a stereo setup and don't need the second channel for something else.) Another way is to compare the sample rate with the PC clock. That will correct for any long term drift but may not track shorter transients. -- These are my opinions. I hate spam. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Digital Mixing with a BeagleBone Black and D Flip Flop
Hi If you are mixing down to 10 Hz, and are looking for 1x10^-7 on the 10 Hz, that equates to a stability / accuracy spec of 0.1 ppm on the ADC clock. A 20 to 100 ppm offset on the clock is not all that unusual. Calibrating out initial offset to 1 ppm is pretty simple. If you can poke a counter onto the clock output, you can get a lot closer than that. The clock probably drifts in the 0.1 to 1.0 ppm / C range. If your room cycles 2 C every hour, correcting that to 0.1 ppm is quite do-able via a “spare” channel. You can record on an input or monitor a signal generated on an output. If your room is stable enough / your stability is good enough you may get away without doing real time correction. Unless your clock has really bad specs, it’s ADEV should be below 1x10^-9 at 0.1 to 10 seconds. That’s 100X better than what you are after. If the clock is a lot worse than these numbers, the audio properties of the ADC will begin to degrade. That more than anything else is what makes this all work. Bob On Oct 12, 2014, at 2:37 PM, Hal Murray hmur...@megapathdsl.net wrote: anders.e.e.wal...@gmail.com said: Does it matter that the ADC in the sound-card is probably clocked by a crystal clock that is 50ppm off and has bad ADEV? You can calibrate the clock on the ADC. One way is to feed a known reference frequency in on the other channel. (That's assuming you have a stereo setup and don't need the second channel for something else.) Another way is to compare the sample rate with the PC clock. That will correct for any long term drift but may not track shorter transients. -- These are my opinions. I hate spam. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Digital Mixing with a BeagleBone Black and D Flip Flop
HI A little more information: If you are doing the ADC thing, you still need to estimate zero crossings. In all likelihood you would be doing bandpass filtering first (say 8 Hz to 12 Hz) on your 10 Hz note. Next you would do some sort of estimator to get the zero cross. A curve fit is one sort of estimator, there are others. A simple straight line fit over 4 or so points might do it. A higher order fit over a few more points is possible. Why does that matter? The fit improves your accuracy quite a bit. It also reduces your vulnerability to odd single sample issues like popcorn noise. Since you are running at a very low frequency 1/f noise can be an issue. Bob On Oct 12, 2014, at 2:37 PM, Hal Murray hmur...@megapathdsl.net wrote: anders.e.e.wal...@gmail.com said: Does it matter that the ADC in the sound-card is probably clocked by a crystal clock that is 50ppm off and has bad ADEV? You can calibrate the clock on the ADC. One way is to feed a known reference frequency in on the other channel. (That's assuming you have a stereo setup and don't need the second channel for something else.) Another way is to compare the sample rate with the PC clock. That will correct for any long term drift but may not track shorter transients. -- These are my opinions. I hate spam. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Digital Mixing with a BeagleBone Black and D Flip Flop
Robert, Bob Camp mention Collins low jitter hard limiters but I suspect that's much more of an issue on the very shallow slopes you see on 5 or 10 Hz mixer outputs. The LTC6957 is probably overkill on 10 MHz inputs but I believe they're a tad better than a 74AC gate, but then again maybe not all that much better. Lot more expensive. Bob C discussed sine to square conversion in a recent post (IIRC) perhaps in connection with 5V to 3.3V conversion, and for a low cost solution the 74AC gate looks pretty good and they're easy to dead bug. Sine-to-square conversion and Collins low jitter hard limiters is related to slew-rate limited resolution. If you have 1E-12 resolution, and see about 20 steps, then over a period of 20 ps the sampler is unable to make a stable sampling. For a 74AC that is not very surprising. You might benefit from some slew-rate improvement on the input. Maybe look at the TADD-2 input for inspiration. The slew-rate adaptation aims to reduce the slew-rate as being the major impact on noise, but the inputs inherent noise then needs to be handled. This is both the samplers/DFF jitter and the other signals jitter. Cheers, Magnus ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Digital Mixing with a BeagleBone Black and D Flip Flop
Hi, Some attempts have been made. Never got around to write the needed code. On 10/12/2014 08:37 PM, Hal Murray wrote: anders.e.e.wal...@gmail.com said: Does it matter that the ADC in the sound-card is probably clocked by a crystal clock that is 50ppm off and has bad ADEV? You can calibrate the clock on the ADC. One way is to feed a known reference frequency in on the other channel. (That's assuming you have a stereo setup and don't need the second channel for something else.) Another way is to compare the sample rate with the PC clock. That will correct for any long term drift but may not track shorter transients. Many more professional audio interfaces allows you to supply a word-clock, so synthesizing that from suitable source would provide good means of adjustment. 48 kHz or multiples is often used. Cheers, Magnus ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Digital Mixing with a BeagleBone Black and D Flip Flop
Increasing the beat frequency to find a balance between 1/f noise and f/delta-f amplification may be worth doing and have been seen done to find optimum performance. If you use hard limiters or audio channels to achieve it is however a little detail. The benefit of audio channels is that the A/B channels does not disperse out in time, such that you loose cross-correlation of transfer oscillator noise. Some AD inputs may need to be modified to remove DC-blocking cap. Not all ADCs is happy with this. Some boards already have that and do DC-removal in digital filters. Cheers, Magnus On 10/12/2014 11:09 PM, Bob Camp wrote: HI A little more information: If you are doing the ADC thing, you still need to estimate zero crossings. In all likelihood you would be doing bandpass filtering first (say 8 Hz to 12 Hz) on your 10 Hz note. Next you would do some sort of estimator to get the zero cross. A curve fit is one sort of estimator, there are others. A simple straight line fit over 4 or so points might do it. A higher order fit over a few more points is possible. Why does that matter? The fit improves your accuracy quite a bit. It also reduces your vulnerability to odd single sample issues like popcorn noise. Since you are running at a very low frequency 1/f noise can be an issue. Bob On Oct 12, 2014, at 2:37 PM, Hal Murray hmur...@megapathdsl.net wrote: anders.e.e.wal...@gmail.com said: Does it matter that the ADC in the sound-card is probably clocked by a crystal clock that is 50ppm off and has bad ADEV? You can calibrate the clock on the ADC. One way is to feed a known reference frequency in on the other channel. (That's assuming you have a stereo setup and don't need the second channel for something else.) Another way is to compare the sample rate with the PC clock. That will correct for any long term drift but may not track shorter transients. -- These are my opinions. I hate spam. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Digital Mixing with a BeagleBone Black and D Flip Flop
Hi The 1/F noise vs beat note “amplification” tradeoff is what pushes me up to 10 Hz rather than staying down around 1 Hz with most setups. It’s also a rational offset to achieve at 10 MHz with common OCXO’s. Once you get past about 20 Hz, your OCXO choices diminish. Bob On Oct 12, 2014, at 7:57 PM, Magnus Danielson mag...@rubidium.dyndns.org wrote: Increasing the beat frequency to find a balance between 1/f noise and f/delta-f amplification may be worth doing and have been seen done to find optimum performance. If you use hard limiters or audio channels to achieve it is however a little detail. The benefit of audio channels is that the A/B channels does not disperse out in time, such that you loose cross-correlation of transfer oscillator noise. Some AD inputs may need to be modified to remove DC-blocking cap. Not all ADCs is happy with this. Some boards already have that and do DC-removal in digital filters. Cheers, Magnus On 10/12/2014 11:09 PM, Bob Camp wrote: HI A little more information: If you are doing the ADC thing, you still need to estimate zero crossings. In all likelihood you would be doing bandpass filtering first (say 8 Hz to 12 Hz) on your 10 Hz note. Next you would do some sort of estimator to get the zero cross. A curve fit is one sort of estimator, there are others. A simple straight line fit over 4 or so points might do it. A higher order fit over a few more points is possible. Why does that matter? The fit improves your accuracy quite a bit. It also reduces your vulnerability to odd single sample issues like popcorn noise. Since you are running at a very low frequency 1/f noise can be an issue. Bob On Oct 12, 2014, at 2:37 PM, Hal Murray hmur...@megapathdsl.net wrote: anders.e.e.wal...@gmail.com said: Does it matter that the ADC in the sound-card is probably clocked by a crystal clock that is 50ppm off and has bad ADEV? You can calibrate the clock on the ADC. One way is to feed a known reference frequency in on the other channel. (That's assuming you have a stereo setup and don't need the second channel for something else.) Another way is to compare the sample rate with the PC clock. That will correct for any long term drift but may not track shorter transients. -- These are my opinions. I hate spam. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Digital Mixing with a BeagleBone Black and D Flip Flop
Bob, I know, and I know you know. Just let others see how things connect up. Still have some 10.000110 MHz OCXOs lying around. Cheers, Magnus On 10/13/2014 02:15 AM, Bob Camp wrote: Hi The 1/F noise vs beat note “amplification” tradeoff is what pushes me up to 10 Hz rather than staying down around 1 Hz with most setups. It’s also a rational offset to achieve at 10 MHz with common OCXO’s. Once you get past about 20 Hz, your OCXO choices diminish. Bob On Oct 12, 2014, at 7:57 PM, Magnus Danielson mag...@rubidium.dyndns.org wrote: Increasing the beat frequency to find a balance between 1/f noise and f/delta-f amplification may be worth doing and have been seen done to find optimum performance. If you use hard limiters or audio channels to achieve it is however a little detail. The benefit of audio channels is that the A/B channels does not disperse out in time, such that you loose cross-correlation of transfer oscillator noise. Some AD inputs may need to be modified to remove DC-blocking cap. Not all ADCs is happy with this. Some boards already have that and do DC-removal in digital filters. Cheers, Magnus On 10/12/2014 11:09 PM, Bob Camp wrote: HI A little more information: If you are doing the ADC thing, you still need to estimate zero crossings. In all likelihood you would be doing bandpass filtering first (say 8 Hz to 12 Hz) on your 10 Hz note. Next you would do some sort of estimator to get the zero cross. A curve fit is one sort of estimator, there are others. A simple straight line fit over 4 or so points might do it. A higher order fit over a few more points is possible. Why does that matter? The fit improves your accuracy quite a bit. It also reduces your vulnerability to odd single sample issues like popcorn noise. Since you are running at a very low frequency 1/f noise can be an issue. Bob On Oct 12, 2014, at 2:37 PM, Hal Murray hmur...@megapathdsl.net wrote: anders.e.e.wal...@gmail.com said: Does it matter that the ADC in the sound-card is probably clocked by a crystal clock that is 50ppm off and has bad ADEV? You can calibrate the clock on the ADC. One way is to feed a known reference frequency in on the other channel. (That's assuming you have a stereo setup and don't need the second channel for something else.) Another way is to compare the sample rate with the PC clock. That will correct for any long term drift but may not track shorter transients. -- These are my opinions. I hate spam. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Digital Mixing with a BeagleBone Black and D Flip Flop
Hi If odd “almost 10 MHz OCXO’s were more common, you could indeed have a bit more freedom on the offset. DDS is sometimes used. DDS spurs (which can be *very* close in) can be both hard to predict and hard to spot in the data. An OCXO is a much better bet unless you have a lot of time on your hands or a really good spectrum analyzer. Much easier to get a $20 Trimble OCXO at auction and ground the EFC pin…. Bob On Oct 12, 2014, at 8:25 PM, Magnus Danielson mag...@rubidium.dyndns.org wrote: Bob, I know, and I know you know. Just let others see how things connect up. Still have some 10.000110 MHz OCXOs lying around. Cheers, Magnus On 10/13/2014 02:15 AM, Bob Camp wrote: Hi The 1/F noise vs beat note “amplification” tradeoff is what pushes me up to 10 Hz rather than staying down around 1 Hz with most setups. It’s also a rational offset to achieve at 10 MHz with common OCXO’s. Once you get past about 20 Hz, your OCXO choices diminish. Bob On Oct 12, 2014, at 7:57 PM, Magnus Danielson mag...@rubidium.dyndns.org wrote: Increasing the beat frequency to find a balance between 1/f noise and f/delta-f amplification may be worth doing and have been seen done to find optimum performance. If you use hard limiters or audio channels to achieve it is however a little detail. The benefit of audio channels is that the A/B channels does not disperse out in time, such that you loose cross-correlation of transfer oscillator noise. Some AD inputs may need to be modified to remove DC-blocking cap. Not all ADCs is happy with this. Some boards already have that and do DC-removal in digital filters. Cheers, Magnus On 10/12/2014 11:09 PM, Bob Camp wrote: HI A little more information: If you are doing the ADC thing, you still need to estimate zero crossings. In all likelihood you would be doing bandpass filtering first (say 8 Hz to 12 Hz) on your 10 Hz note. Next you would do some sort of estimator to get the zero cross. A curve fit is one sort of estimator, there are others. A simple straight line fit over 4 or so points might do it. A higher order fit over a few more points is possible. Why does that matter? The fit improves your accuracy quite a bit. It also reduces your vulnerability to odd single sample issues like popcorn noise. Since you are running at a very low frequency 1/f noise can be an issue. Bob On Oct 12, 2014, at 2:37 PM, Hal Murray hmur...@megapathdsl.net wrote: anders.e.e.wal...@gmail.com said: Does it matter that the ADC in the sound-card is probably clocked by a crystal clock that is 50ppm off and has bad ADEV? You can calibrate the clock on the ADC. One way is to feed a known reference frequency in on the other channel. (That's assuming you have a stereo setup and don't need the second channel for something else.) Another way is to compare the sample rate with the PC clock. That will correct for any long term drift but may not track shorter transients. -- These are my opinions. I hate spam. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Digital Mixing with a BeagleBone Black and D Flip Flop
Simon, Welcome to the tangential world. I'm sure the clean edge I saw was an aberration, perhaps analogous to phase locking in oscillators; I don't think it's desirable because common sense tells you that with imperfect clocks and small phase differences there are bound to be some number of glitches at each transition. I did nothing specific to eliminate the glitches, it just happened that the positive going transition was very clean but there's no reason I am aware of to suggest that one transition should be better in this respect than another. Perhaps the flip flop I was using had a shorter set-up time on negative to positive transitions than vice versa; the smaller the set-up time the more likely one is to capture borderline events? I seem to recall that Didier Juges and Bruce Griffiths had some discussions re DDMTD's (although I can't find it in the archives) but in any event you could do far worse than dropping them a note directly to ask them about their thoughts on the matter. I'm sorry I can't provide any analysis of your data; just not in my skill set. Perhaps Marcus or TVB could comment. Bob Darby On 10/10/2014 3:46 PM, Simon Marsh wrote: Bob, It's good to know someone else is trying this and it's not just me going off on a tangent somewhere. I'd be very interested in understanding how you'd set this up and how you'd got a nice clean rising edge. My understanding is that the 'glitches' occur because the clocks are being sampled at a higher resolution than the cycle to cycle noise inherent in both the clocks and the setup. Certainly, I don't expect any of the oscillators I have available to be perfectly stable at ~1E-12 resolution, I'm sure they are all over the place The clock phase noise shows up as fast transitions near the actual beat edge as the clocks wander backwards and forwards over a few cycles. I'm sure analysis of the glitches themselves would probably say quite a lot about the cycle to cycle noise. I've attached an example of the transitions near an edge for a random TCXO. The edge goes from 0 at the start to 1 at the end and shows noise over about 180 samples (@10mhz). This corresponds to about ± 5E-11. The crossing line of the zero one counts is where the edge is measured from the software point of view. ± 50ps sounds high to me, but I'm open to views as to whether that seems reasonable or just shows my shoddy setup ? For fun, also attached is plot of the transitions for a UBLOX8 GPS module outputing 10mhz. Compared to the TCXO that has about 10k transitions in a second's worth of data, the UBLOX module has over 1.3M (this is with a beat frequency of ~60hz). I think this is down to how the gps module is inserting/removing cycles to get 10mhz from its internal clock frequency (as has been discussed on here recently). Unfortunately, I don't have any expensive counters, that's part of my motivation for doing this, so I'm interested in ways that I can understand the noise floor. I tried passing one clock through a 74AC hex inverter and then measuring the phase between the inverted/non-inverted signals on the basis that this should be more or less constant and what I'd be measuring was noise. It's certainly a good way of measuring how long the wire was that I used to make the connection This seems to yield an ADEV of 5.92E-11 @ 1 sec, plots also attached. Interestingly the phase seems to drift over the measurement interval, I'm open to suggestions on this, but guess this may be temperature related ? (open on bench, non-airconditioned etc) If the plots don't come through as attached, they are also on google drive here: https://drive.google.com/open?id=0BzvFGRfj4aFkSEdYV3lXcmZIVTAauthuser=0 Cheers Simon On 10/10/2014 02:01, Robert Darby wrote: Simon, I breadboaded a set-up in March using 74AC74's and two 10 MHz Micro Crystal oscillators (5V square wave), one as the coherent source and one as the 10Hz offset clock. I had no glitch filtering as described in the article you cite (CERN's White Rabbit Project, sub nanosecond timing over ethernet) but found the positive zero crossing was very clean. The negative crossing not so much; no idea why one edge was clean and the other not. To ensure I only measured the rising clock edge and not the noise on the falling clock, I programmed ATiny's (digital 555?) to arm the D-flops only after a period of continuous low states. In any event, the lash up, as measure by a 5370, produced a clean linear noise floor of 8e-12 at 1s. I regret to note that's very slightly better than my results from the Bill Riley DMTD device. That's an indictment of my analog building skills, not his design. It's also nicely below a 5370 on it's own and needs only a simple 10 MHz counter for output. The zero crossing detectors for sine wave oscillator input will perhaps be more critical. This was encouraging enough that I thought I'd try to build an FPGA version of the same.
Re: [time-nuts] Digital Mixing with a BeagleBone Black and D Flip Flop
Hi If you are looking at the low frequency beat note out of a mixer and seeing multiple transitions on an edge - you filtering or your limiter are not up to the task. In most cases it’s the filter, but it can be either. Bob On Oct 11, 2014, at 9:10 AM, Robert Darby bobda...@triad.rr.com wrote: Simon, Welcome to the tangential world. I'm sure the clean edge I saw was an aberration, perhaps analogous to phase locking in oscillators; I don't think it's desirable because common sense tells you that with imperfect clocks and small phase differences there are bound to be some number of glitches at each transition. I did nothing specific to eliminate the glitches, it just happened that the positive going transition was very clean but there's no reason I am aware of to suggest that one transition should be better in this respect than another. Perhaps the flip flop I was using had a shorter set-up time on negative to positive transitions than vice versa; the smaller the set-up time the more likely one is to capture borderline events? I seem to recall that Didier Juges and Bruce Griffiths had some discussions re DDMTD's (although I can't find it in the archives) but in any event you could do far worse than dropping them a note directly to ask them about their thoughts on the matter. I'm sorry I can't provide any analysis of your data; just not in my skill set. Perhaps Marcus or TVB could comment. Bob Darby On 10/10/2014 3:46 PM, Simon Marsh wrote: Bob, It's good to know someone else is trying this and it's not just me going off on a tangent somewhere. I'd be very interested in understanding how you'd set this up and how you'd got a nice clean rising edge. My understanding is that the 'glitches' occur because the clocks are being sampled at a higher resolution than the cycle to cycle noise inherent in both the clocks and the setup. Certainly, I don't expect any of the oscillators I have available to be perfectly stable at ~1E-12 resolution, I'm sure they are all over the place The clock phase noise shows up as fast transitions near the actual beat edge as the clocks wander backwards and forwards over a few cycles. I'm sure analysis of the glitches themselves would probably say quite a lot about the cycle to cycle noise. I've attached an example of the transitions near an edge for a random TCXO. The edge goes from 0 at the start to 1 at the end and shows noise over about 180 samples (@10mhz). This corresponds to about ± 5E-11. The crossing line of the zero one counts is where the edge is measured from the software point of view. ± 50ps sounds high to me, but I'm open to views as to whether that seems reasonable or just shows my shoddy setup ? For fun, also attached is plot of the transitions for a UBLOX8 GPS module outputing 10mhz. Compared to the TCXO that has about 10k transitions in a second's worth of data, the UBLOX module has over 1.3M (this is with a beat frequency of ~60hz). I think this is down to how the gps module is inserting/removing cycles to get 10mhz from its internal clock frequency (as has been discussed on here recently). Unfortunately, I don't have any expensive counters, that's part of my motivation for doing this, so I'm interested in ways that I can understand the noise floor. I tried passing one clock through a 74AC hex inverter and then measuring the phase between the inverted/non-inverted signals on the basis that this should be more or less constant and what I'd be measuring was noise. It's certainly a good way of measuring how long the wire was that I used to make the connection This seems to yield an ADEV of 5.92E-11 @ 1 sec, plots also attached. Interestingly the phase seems to drift over the measurement interval, I'm open to suggestions on this, but guess this may be temperature related ? (open on bench, non-airconditioned etc) If the plots don't come through as attached, they are also on google drive here: https://drive.google.com/open?id=0BzvFGRfj4aFkSEdYV3lXcmZIVTAauthuser=0 Cheers Simon On 10/10/2014 02:01, Robert Darby wrote: Simon, I breadboaded a set-up in March using 74AC74's and two 10 MHz Micro Crystal oscillators (5V square wave), one as the coherent source and one as the 10Hz offset clock. I had no glitch filtering as described in the article you cite (CERN's White Rabbit Project, sub nanosecond timing over ethernet) but found the positive zero crossing was very clean. The negative crossing not so much; no idea why one edge was clean and the other not. To ensure I only measured the rising clock edge and not the noise on the falling clock, I programmed ATiny's (digital 555?) to arm the D-flops only after a period of continuous low states. In any event, the lash up, as measure by a 5370, produced a clean linear noise floor of 8e-12 at 1s. I regret to note that's very slightly better than my results
Re: [time-nuts] Digital Mixing with a BeagleBone Black and D Flip Flop
In this case, it seems reasonable that these multiple transitions are to be expected as there isn't any filtering that takes place in hardware prior to samples being captured by the BBB. The equivalent of the filtering/zero crossing detection takes place in software in the edge detection routine. Cheers Simon On 11/10/2014 15:19, Bob Camp wrote: Hi If you are looking at the low frequency beat note out of a mixer and seeing multiple transitions on an edge - you filtering or your limiter are not up to the task. In most cases it’s the filter, but it can be either. Bob On Oct 11, 2014, at 9:10 AM, Robert Darby bobda...@triad.rr.com wrote: Simon, Welcome to the tangential world. I'm sure the clean edge I saw was an aberration, perhaps analogous to phase locking in oscillators; I don't think it's desirable because common sense tells you that with imperfect clocks and small phase differences there are bound to be some number of glitches at each transition. I did nothing specific to eliminate the glitches, it just happened that the positive going transition was very clean but there's no reason I am aware of to suggest that one transition should be better in this respect than another. Perhaps the flip flop I was using had a shorter set-up time on negative to positive transitions than vice versa; the smaller the set-up time the more likely one is to capture borderline events? I seem to recall that Didier Juges and Bruce Griffiths had some discussions re DDMTD's (although I can't find it in the archives) but in any event you could do far worse than dropping them a note directly to ask them about their thoughts on the matter. I'm sorry I can't provide any analysis of your data; just not in my skill set. Perhaps Marcus or TVB could comment. Bob Darby On 10/10/2014 3:46 PM, Simon Marsh wrote: Bob, It's good to know someone else is trying this and it's not just me going off on a tangent somewhere. I'd be very interested in understanding how you'd set this up and how you'd got a nice clean rising edge. My understanding is that the 'glitches' occur because the clocks are being sampled at a higher resolution than the cycle to cycle noise inherent in both the clocks and the setup. Certainly, I don't expect any of the oscillators I have available to be perfectly stable at ~1E-12 resolution, I'm sure they are all over the place The clock phase noise shows up as fast transitions near the actual beat edge as the clocks wander backwards and forwards over a few cycles. I'm sure analysis of the glitches themselves would probably say quite a lot about the cycle to cycle noise. I've attached an example of the transitions near an edge for a random TCXO. The edge goes from 0 at the start to 1 at the end and shows noise over about 180 samples (@10mhz). This corresponds to about ± 5E-11. The crossing line of the zero one counts is where the edge is measured from the software point of view. ± 50ps sounds high to me, but I'm open to views as to whether that seems reasonable or just shows my shoddy setup ? For fun, also attached is plot of the transitions for a UBLOX8 GPS module outputing 10mhz. Compared to the TCXO that has about 10k transitions in a second's worth of data, the UBLOX module has over 1.3M (this is with a beat frequency of ~60hz). I think this is down to how the gps module is inserting/removing cycles to get 10mhz from its internal clock frequency (as has been discussed on here recently). Unfortunately, I don't have any expensive counters, that's part of my motivation for doing this, so I'm interested in ways that I can understand the noise floor. I tried passing one clock through a 74AC hex inverter and then measuring the phase between the inverted/non-inverted signals on the basis that this should be more or less constant and what I'd be measuring was noise. It's certainly a good way of measuring how long the wire was that I used to make the connection This seems to yield an ADEV of 5.92E-11 @ 1 sec, plots also attached. Interestingly the phase seems to drift over the measurement interval, I'm open to suggestions on this, but guess this may be temperature related ? (open on bench, non-airconditioned etc) If the plots don't come through as attached, they are also on google drive here: https://drive.google.com/open?id=0BzvFGRfj4aFkSEdYV3lXcmZIVTAauthuser=0 Cheers Simon On 10/10/2014 02:01, Robert Darby wrote: Simon, I breadboaded a set-up in March using 74AC74's and two 10 MHz Micro Crystal oscillators (5V square wave), one as the coherent source and one as the 10Hz offset clock. I had no glitch filtering as described in the article you cite (CERN's White Rabbit Project, sub nanosecond timing over ethernet) but found the positive zero crossing was very clean. The negative crossing not so much; no idea why one edge was clean and the other not. To ensure I only measured the rising clock edge and not the noise on the falling clock, I
Re: [time-nuts] Digital Mixing with a BeagleBone Black and D Flip Flop
Bob we are using digital mixers in some other applications but what surprised me is your comment on the Riley DMTD. We have a couple of slightly modified Riley's and see any where from 1.44 to 3.84 E-14 at 1 second. Bill also sows data below 1 E-13 at 1 second. Presently looking at braking the 1 E-14 level at the same time reducing cost. Bert Kehren. In a message dated 10/9/2014 9:01:24 P.M. Eastern Daylight Time, bobda...@triad.rr.com writes: Simon, I breadboaded a set-up in March using 74AC74's and two 10 MHz Micro Crystal oscillators (5V square wave), one as the coherent source and one as the 10Hz offset clock. I had no glitch filtering as described in the article you cite (CERN's White Rabbit Project, sub nanosecond timing over ethernet) but found the positive zero crossing was very clean. The negative crossing not so much; no idea why one edge was clean and the other not. To ensure I only measured the rising clock edge and not the noise on the falling clock, I programmed ATiny's (digital 555?) to arm the D-flops only after a period of continuous low states. In any event, the lash up, as measure by a 5370, produced a clean linear noise floor of 8e-12 at 1s. I regret to note that's very slightly better than my results from the Bill Riley DMTD device. That's an indictment of my analog building skills, not his design. It's also nicely below a 5370 on it's own and needs only a simple 10 MHz counter for output. The zero crossing detectors for sine wave oscillator input will perhaps be more critical. This was encouraging enough that I thought I'd try to build an FPGA version of the same. The DDMTD is temporarily on back burner while I try to get a four channel 1ns resolution time tagger running on the FPGA to use with the DMTD. Almost there. I look forward to hearing your results with the BBB; keep us posted. Bob Darby On 10/9/2014 1:34 AM, Andrew Rodland wrote: Simon, This is a fantastic idea and I have every intention of trying to replicate it at home with tools on hand. Thanks for sharing, and I hope you can show off some results. On Wed, Oct 8, 2014 at 1:09 PM, Simon Marsh subscripti...@burble.com wrote: I've been a lurker on time-nuts for a while, most of the discussion being way over my head, but I thought there may be interest in some proof of concept code I've written for simple digital hetrodyne mixing using just a BeagleBone Black and an external dual D Flip Flop. The idea is based on the following article which describes creating a digital DMTD with an FPGA for clocks @ 125mhz: http://www.ee.ucl.ac.uk/lcs/previous/LCS2011/LCS1136.pdf My setup follows the same principle, but scaled down to 10mhz to make it as simple as possible (and not require an FPGA). The hardware side is just a 74AC74 dual flip flop to sample the input clocks being tested. Instead of having a helper PLL for the mixer frequency, I simply have a 3rd, de-tuned oscillator. The output from the two flip-flops together with the mixer clock are fed to the BBB. On the BBB, the approach is to do as little as possible in real time using a PRU core, and then post-process on the ARM core afterwards. The BBB PRU has a 16-bit, asynchronous, parallel, capture mode, where 16 GPIO pins can be latched based on an external clock (described in section 4.4.1.2.3.2 of the TRM for those interested). In this case, the external clock is the mixer oscillator. All the PRU needs to do is wait for the sample to take place, read the GPIOs and store the results in main memory. The PRU is plenty fast enough to capture samples @10mhz and, in theory at least, each PRU could sample up to 16 clocks simultaneously (depending on whether the relevant GPIO pins were free). Once the sampling is complete, the ARM core can process the results in its own time, and this includes any more complicated algorithms for de-glitching etc The theoretical minimum time resolution depends on the beat frequency and is described in the article, for example with a beat frequency of 50 hz the minimum resolution is 50 / (1000 - 50)*1000 = ~5E-13. In practice the available accuracy is determined by the stability of the mixer clock and noise of the setup. The impact of this noise is described in the article as glitching and there are some suggested ways for processing this out. I'm trying this on an open bench, with basic oscillators, using pluggable breadboard and lots of hanging wires, I'm not at risk of getting near the theoretical limit quite yet :) Note that the BBB itself has no impact on the accuracy or noise of the raw data. Once the input is latched at the flip-flop, the only bit of critical timing required is to ensure that samples can be captured fast enough and that the flip-flop state is captured when it is stable (i.e. not transitioning). I make no excuses that this is very
Re: [time-nuts] Digital Mixing with a BeagleBone Black and D Flip Flop
Yeah, breaks my heart but I'm not real good (try real bad) at troubleshooting electronics (so why am i here?). As I noted in my earlier post, the issue lies in my construction and lack of knowledge re electronic fundamentals. I have the greatest respect for Mr. Riley and I do not want my ineptitude to in any way reflect on his design. All problems with my DMTD are of my making, not his. bob On 10/11/2014 3:10 PM, Bert Kehren via time-nuts wrote: Bob we are using digital mixers in some other applications but what surprised me is your comment on the Riley DMTD. We have a couple of slightly modified Riley's and see any where from 1.44 to 3.84 E-14 at 1 second. Bill also sows data below 1 E-13 at 1 second. Presently looking at braking the 1 E-14 level at the same time reducing cost. Bert Kehren. In a message dated 10/9/2014 9:01:24 P.M. Eastern Daylight Time, bobda...@triad.rr.com writes: Simon, I breadboaded a set-up in March using 74AC74's and two 10 MHz Micro Crystal oscillators (5V square wave), one as the coherent source and one as the 10Hz offset clock. I had no glitch filtering as described in the article you cite (CERN's White Rabbit Project, sub nanosecond timing over ethernet) but found the positive zero crossing was very clean. The negative crossing not so much; no idea why one edge was clean and the other not. To ensure I only measured the rising clock edge and not the noise on the falling clock, I programmed ATiny's (digital 555?) to arm the D-flops only after a period of continuous low states. In any event, the lash up, as measure by a 5370, produced a clean linear noise floor of 8e-12 at 1s. I regret to note that's very slightly better than my results from the Bill Riley DMTD device. That's an indictment of my analog building skills, not his design. It's also nicely below a 5370 on it's own and needs only a simple 10 MHz counter for output. The zero crossing detectors for sine wave oscillator input will perhaps be more critical. This was encouraging enough that I thought I'd try to build an FPGA version of the same. The DDMTD is temporarily on back burner while I try to get a four channel 1ns resolution time tagger running on the FPGA to use with the DMTD. Almost there. I look forward to hearing your results with the BBB; keep us posted. Bob Darby On 10/9/2014 1:34 AM, Andrew Rodland wrote: Simon, This is a fantastic idea and I have every intention of trying to replicate it at home with tools on hand. Thanks for sharing, and I hope you can show off some results. On Wed, Oct 8, 2014 at 1:09 PM, Simon Marsh subscripti...@burble.com wrote: I've been a lurker on time-nuts for a while, most of the discussion being way over my head, but I thought there may be interest in some proof of concept code I've written for simple digital hetrodyne mixing using just a BeagleBone Black and an external dual D Flip Flop. The idea is based on the following article which describes creating a digital DMTD with an FPGA for clocks @ 125mhz: http://www.ee.ucl.ac.uk/lcs/previous/LCS2011/LCS1136.pdf My setup follows the same principle, but scaled down to 10mhz to make it as simple as possible (and not require an FPGA). The hardware side is just a 74AC74 dual flip flop to sample the input clocks being tested. Instead of having a helper PLL for the mixer frequency, I simply have a 3rd, de-tuned oscillator. The output from the two flip-flops together with the mixer clock are fed to the BBB. On the BBB, the approach is to do as little as possible in real time using a PRU core, and then post-process on the ARM core afterwards. The BBB PRU has a 16-bit, asynchronous, parallel, capture mode, where 16 GPIO pins can be latched based on an external clock (described in section 4.4.1.2.3.2 of the TRM for those interested). In this case, the external clock is the mixer oscillator. All the PRU needs to do is wait for the sample to take place, read the GPIOs and store the results in main memory. The PRU is plenty fast enough to capture samples @10mhz and, in theory at least, each PRU could sample up to 16 clocks simultaneously (depending on whether the relevant GPIO pins were free). Once the sampling is complete, the ARM core can process the results in its own time, and this includes any more complicated algorithms for de-glitching etc The theoretical minimum time resolution depends on the beat frequency and is described in the article, for example with a beat frequency of 50 hz the minimum resolution is 50 / (1000 - 50)*1000 = ~5E-13. In practice the available accuracy is determined by the stability of the mixer clock and noise of the setup. The impact of this noise is described in the article as glitching and there are some suggested ways for processing this out. I'm trying this on an open bench, with basic oscillators, using pluggable breadboard and lots of hanging wires, I'm not at
Re: [time-nuts] Digital Mixing with a BeagleBone Black and D Flip Flop
Simon, If I can rephrase your first post, you plan to capture the state transitions along with their timing and subsequently post-process them to determine the time from one zero-crossing to another. Each zero-crossing is the sum of number of closely spaced state changes (glitches) and some algorithm can be used to determine when the real zero-crossing occurred. Given the low speed of the clock, a deep memory one bit data logger would suffice for each channel. Alternately, you can store time tags for each state transition; the time being measured in offset clock cycles. This reduces the device to an offset clock, analog to digital conversion for sine wave inputs, at least two d-flops, and the BBB for data capture and analysis. Correct? The glitches are to be expected and, as I noted, the absence of them on the negative to positive transition of my breadboarded set-up made me suspect the accuracy but also made it easy to get a back of the envelop noise floor number that should only get better, provide the de-glitch filter is robust. Just as another thought, an FTDI asynchronous fifo can move 10 MB/s and a synchronous fifo can move 60 MB/s. You could probably capture the D-flop outputs directly through a USB port and process the byte wide stream in real time. But that's what the BBB's going to do in any case. As I mentioned, I want to try this in an fpga and the filter is the only hard part there. I'm thinking a state machine that first establishes a stable low state, time tags the first positive transition and then looks for some number of stable high states. With a time tag at that point, it's easy to work back to the last positive transition and establish the mean time. I'm still trying to get my head around how I can do the zero count filter but hopefully it will come. The reason the fpga is attractive is because a $40 Papilio includes the D-Flops and is largely self contained. Add a wing pad with the input conversion and your beat clock and you're good to go. bob On 10/11/2014 11:17 AM, Simon Marsh wrote: In this case, it seems reasonable that these multiple transitions are to be expected as there isn't any filtering that takes place in hardware prior to samples being captured by the BBB. The equivalent of the filtering/zero crossing detection takes place in software in the edge detection routine. Cheers Simon On 11/10/2014 15:19, Bob Camp wrote: Hi If you are looking at the low frequency beat note out of a mixer and seeing multiple transitions on an edge - you filtering or your limiter are not up to the task. In most cases it’s the filter, but it can be either. Bob On Oct 11, 2014, at 9:10 AM, Robert Darby bobda...@triad.rr.com wrote: Simon, Welcome to the tangential world. I'm sure the clean edge I saw was an aberration, perhaps analogous to phase locking in oscillators; I don't think it's desirable because common sense tells you that with imperfect clocks and small phase differences there are bound to be some number of glitches at each transition. I did nothing specific to eliminate the glitches, it just happened that the positive going transition was very clean but there's no reason I am aware of to suggest that one transition should be better in this respect than another. Perhaps the flip flop I was using had a shorter set-up time on negative to positive transitions than vice versa; the smaller the set-up time the more likely one is to capture borderline events? I seem to recall that Didier Juges and Bruce Griffiths had some discussions re DDMTD's (although I can't find it in the archives) but in any event you could do far worse than dropping them a note directly to ask them about their thoughts on the matter. I'm sorry I can't provide any analysis of your data; just not in my skill set. Perhaps Marcus or TVB could comment. Bob Darby On 10/10/2014 3:46 PM, Simon Marsh wrote: Bob, It's good to know someone else is trying this and it's not just me going off on a tangent somewhere. I'd be very interested in understanding how you'd set this up and how you'd got a nice clean rising edge. My understanding is that the 'glitches' occur because the clocks are being sampled at a higher resolution than the cycle to cycle noise inherent in both the clocks and the setup. Certainly, I don't expect any of the oscillators I have available to be perfectly stable at ~1E-12 resolution, I'm sure they are all over the place The clock phase noise shows up as fast transitions near the actual beat edge as the clocks wander backwards and forwards over a few cycles. I'm sure analysis of the glitches themselves would probably say quite a lot about the cycle to cycle noise. I've attached an example of the transitions near an edge for a random TCXO. The edge goes from 0 at the start to 1 at the end and shows noise over about 180 samples (@10mhz). This corresponds to about ± 5E-11. The crossing line of the zero one
Re: [time-nuts] Digital Mixing with a BeagleBone Black and D Flip Flop
Hi Your glitches are (in part) coming from the 20 MHz (10 + 10) component on the mixed signal. Since they have no direct relation to the beat note, filtering them after limiting is not a simple task. It is far easier to keep filter the signal pre-limit than to do so post limit. The other component of the glitches is related to the limiting process. The paper by Collins is a good one to read for information on gain, bandwidth and the limiting process. Again, there is very little you can do “post limit” to sort things out. None of the zero crossings you are getting may be “correct”. It’s not simply a process of picking one out of the group. —— Some math: You have two 10 MHz signals and a (say) 10 Hz beat note. You are looking for 1x10^-13. You get 1x10^-6 from the downconversion. You need to get 1x10^-7 out of the beat note. Put another way, 1x10^-13 at 10 MHz is 1x10^-5 Hz. If your beat note is 3 V p-p, it will cover 6V every 1/10 second. It’s about 1.2X faster than a triangle wave as it zero crosses (memory may be failing me here), so that makes it equal to a 7.2V triangle excursion. 1x10^-6 of 7.2V is 7.2 microvolts. That’s how accurate your limiter / filter combination needs to be, pre-limiting. It can be in a fairly narrow bandwidth, so it’s not quite as daunting as a radio front end. Since you have a very large signal, and very small noise, the normal “dithering will help me” effect of the noise can not be counted on. The thing you *want* to come up with is essentially a random signal (ADEV), so massive filtering will not do the trick either. Bob On Oct 11, 2014, at 3:33 PM, Robert Darby bobda...@triad.rr.com wrote: Simon, If I can rephrase your first post, you plan to capture the state transitions along with their timing and subsequently post-process them to determine the time from one zero-crossing to another. Each zero-crossing is the sum of number of closely spaced state changes (glitches) and some algorithm can be used to determine when the real zero-crossing occurred. Given the low speed of the clock, a deep memory one bit data logger would suffice for each channel. Alternately, you can store time tags for each state transition; the time being measured in offset clock cycles. This reduces the device to an offset clock, analog to digital conversion for sine wave inputs, at least two d-flops, and the BBB for data capture and analysis. Correct? The glitches are to be expected and, as I noted, the absence of them on the negative to positive transition of my breadboarded set-up made me suspect the accuracy but also made it easy to get a back of the envelop noise floor number that should only get better, provide the de-glitch filter is robust. Just as another thought, an FTDI asynchronous fifo can move 10 MB/s and a synchronous fifo can move 60 MB/s. You could probably capture the D-flop outputs directly through a USB port and process the byte wide stream in real time. But that's what the BBB's going to do in any case. As I mentioned, I want to try this in an fpga and the filter is the only hard part there. I'm thinking a state machine that first establishes a stable low state, time tags the first positive transition and then looks for some number of stable high states. With a time tag at that point, it's easy to work back to the last positive transition and establish the mean time. I'm still trying to get my head around how I can do the zero count filter but hopefully it will come. The reason the fpga is attractive is because a $40 Papilio includes the D-Flops and is largely self contained. Add a wing pad with the input conversion and your beat clock and you're good to go. bob On 10/11/2014 11:17 AM, Simon Marsh wrote: In this case, it seems reasonable that these multiple transitions are to be expected as there isn't any filtering that takes place in hardware prior to samples being captured by the BBB. The equivalent of the filtering/zero crossing detection takes place in software in the edge detection routine. Cheers Simon On 11/10/2014 15:19, Bob Camp wrote: Hi If you are looking at the low frequency beat note out of a mixer and seeing multiple transitions on an edge - you filtering or your limiter are not up to the task. In most cases it’s the filter, but it can be either. Bob On Oct 11, 2014, at 9:10 AM, Robert Darby bobda...@triad.rr.com wrote: Simon, Welcome to the tangential world. I'm sure the clean edge I saw was an aberration, perhaps analogous to phase locking in oscillators; I don't think it's desirable because common sense tells you that with imperfect clocks and small phase differences there are bound to be some number of glitches at each transition. I did nothing specific to eliminate the glitches, it just happened that the positive going transition was very clean but there's no reason I am aware of to suggest that
Re: [time-nuts] Digital Mixing with a BeagleBone Black and D Flip Flop
I (mostly) understand this when considering an analogue mixer, but I'm lost on whether there are any similar effects going on with a digital signal ? TBH, I'm not really sure 'mixing' is the right phrase in the digital case, and my apologies if I got that wrong. What's actually going on is sampling one (digital) signal at a rate close to the signal frequency. This gives a vernier effect and the result is a purely digital set of pulses at the beat frequency, aligned to when the signal and sample clock are in phase. It does not have a high frequency component to filter out. Cheers Simon On 11/10/2014 21:11, Bob Camp wrote: Hi Your glitches are (in part) coming from the 20 MHz (10 + 10) component on the mixed signal. Since they have no direct relation to the beat note, filtering them after limiting is not a simple task. It is far easier to keep filter the signal pre-limit than to do so post limit. The other component of the glitches is related to the limiting process. The paper by Collins is a good one to read for information on gain, bandwidth and the limiting process. Again, there is very little you can do “post limit” to sort things out. None of the zero crossings you are getting may be “correct”. It’s not simply a process of picking one out of the group. —— Some math: You have two 10 MHz signals and a (say) 10 Hz beat note. You are looking for 1x10^-13. You get 1x10^-6 from the downconversion. You need to get 1x10^-7 out of the beat note. Put another way, 1x10^-13 at 10 MHz is 1x10^-5 Hz. If your beat note is 3 V p-p, it will cover 6V every 1/10 second. It’s about 1.2X faster than a triangle wave as it zero crosses (memory may be failing me here), so that makes it equal to a 7.2V triangle excursion. 1x10^-6 of 7.2V is 7.2 microvolts. That’s how accurate your limiter / filter combination needs to be, pre-limiting. It can be in a fairly narrow bandwidth, so it’s not quite as daunting as a radio front end. Since you have a very large signal, and very small noise, the normal “dithering will help me” effect of the noise can not be counted on. The thing you *want* to come up with is essentially a random signal (ADEV), so massive filtering will not do the trick either. Bob On Oct 11, 2014, at 3:33 PM, Robert Darby bobda...@triad.rr.com wrote: ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Digital Mixing with a BeagleBone Black and D Flip Flop
On 11/10/2014 20:33, Robert Darby wrote: If I can rephrase your first post, you plan to capture the state transitions along with their timing and subsequently post-process them to determine the time from one zero-crossing to another. Each zero-crossing is the sum of number of closely spaced state changes (glitches) and some algorithm can be used to determine when the real zero-crossing occurred. Given the low speed of the clock, a deep memory one bit data logger would suffice for each channel. Alternately, you can store time tags for each state transition; the time being measured in offset clock cycles. Spot on, and indeed, the code I posted uses the one bit data logger idea. I intend to replace with time tagging to save some memory, save some ARM CPU time and enabling continuous logging. This reduces the device to an offset clock, analog to digital conversion for sine wave inputs, at least two d-flops, and the BBB for data capture and analysis. Correct? Yes, exactly. Of course, it also needs a bunch of software to do the processing. Just as another thought, an FTDI asynchronous fifo can move 10 MB/s and a synchronous fifo can move 60 MB/s. You could probably capture the D-flop outputs directly through a USB port and process the byte wide stream in real time. But that's what the BBB's going to do in any case. Interesting idea, but yes again, this is what I have the PRU on the BBB doing. As I mentioned, I want to try this in an fpga and the filter is the only hard part there. I'm thinking a state machine that first establishes a stable low state, time tags the first positive transition and then looks for some number of stable high states. With a time tag at that point, it's easy to work back to the last positive transition and establish the mean time. I'm still trying to get my head around how I can do the zero count filter but hopefully it will come. The reason the fpga is attractive is because a $40 Papilio includes the D-Flops and is largely self contained. Add a wing pad with the input conversion and your beat clock and you're good to go. I have a Papilio around somewhere too, but admit I find it easier messing around in software. Are you intending to output time stamped edges (or phase ?) from FPGA and then log/post-process somewhere else ? I used the zero count method, but no doubt this was easier in C than it will be on an FPGA. The paper I linked to has some discussion on a few algorithms, and they think the zero count is better than a mean. I'm not one to argue with clever folks at CERN, but I think it will be interesting to see if I can get to the point of showing if there is actually a difference at my scale, or even whether there are some smarter approaches when having the luxury of implementing in software. All I did was identify the first transition after a stable period and then count ones and zeros until ones zeros. The only gotcha is that (by definition) the first transition after a bunch of zeros will always be a one so you have to make sure you count the next set of zeros before checking if ones zeros (otherwise, of course, ones will always be zero on the first transition). This also means you need to have a limit built in for when there are no glitches (i.e. no zeros arrive before you determine the number of ones means you are in a new stable period). I'd be very interested at what you intend to do for the input conversion. Getting the signal squared up and delivered to the D-flop would seem to the hard part and where all the noise will be. Once you have a digital signal at the flip flop its downhill all the way. bob [snipped] Cheers Simon ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Digital Mixing with a BeagleBone Black and D Flip Flop
Hi The mixer you are using will give you a sine wave output *if* it’s properly filtered. A mixer is a mixer. Bob On Oct 11, 2014, at 6:31 PM, Simon Marsh subscripti...@burble.com wrote: I (mostly) understand this when considering an analogue mixer, but I'm lost on whether there are any similar effects going on with a digital signal ? TBH, I'm not really sure 'mixing' is the right phrase in the digital case, and my apologies if I got that wrong. What's actually going on is sampling one (digital) signal at a rate close to the signal frequency. This gives a vernier effect and the result is a purely digital set of pulses at the beat frequency, aligned to when the signal and sample clock are in phase. It does not have a high frequency component to filter out. Cheers Simon On 11/10/2014 21:11, Bob Camp wrote: Hi Your glitches are (in part) coming from the 20 MHz (10 + 10) component on the mixed signal. Since they have no direct relation to the beat note, filtering them after limiting is not a simple task. It is far easier to keep filter the signal pre-limit than to do so post limit. The other component of the glitches is related to the limiting process. The paper by Collins is a good one to read for information on gain, bandwidth and the limiting process. Again, there is very little you can do “post limit” to sort things out. None of the zero crossings you are getting may be “correct”. It’s not simply a process of picking one out of the group. —— Some math: You have two 10 MHz signals and a (say) 10 Hz beat note. You are looking for 1x10^-13. You get 1x10^-6 from the downconversion. You need to get 1x10^-7 out of the beat note. Put another way, 1x10^-13 at 10 MHz is 1x10^-5 Hz. If your beat note is 3 V p-p, it will cover 6V every 1/10 second. It’s about 1.2X faster than a triangle wave as it zero crosses (memory may be failing me here), so that makes it equal to a 7.2V triangle excursion. 1x10^-6 of 7.2V is 7.2 microvolts. That’s how accurate your limiter / filter combination needs to be, pre-limiting. It can be in a fairly narrow bandwidth, so it’s not quite as daunting as a radio front end. Since you have a very large signal, and very small noise, the normal “dithering will help me” effect of the noise can not be counted on. The thing you *want* to come up with is essentially a random signal (ADEV), so massive filtering will not do the trick either. Bob On Oct 11, 2014, at 3:33 PM, Robert Darby bobda...@triad.rr.com wrote: ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Digital Mixing with a BeagleBone Black and D Flip Flop
Hi Ok, a little more data: You can hook your flip flop up as a sampler or as a full blown mixer. Hooked up as a full blown mixer, you get the 20 MHz and 10 Hz signals. You also get more resolution on the 10 Hz. Either way, the 10 Hz is still a beat note. In the case of a sampler, the filter is there for edge jitter. With a sampler, your data is only modulo 100 ns. With a 100 ms beat note period, you only get 1x10^-6 at best. That’s very different than what you get with the same chip used as a mixer (or an XOR gate). The true mixer connection gives you data the instant the edge changes. The sampler goes to sleep and lets you know up to 100 ns later ... Bob On Oct 11, 2014, at 6:31 PM, Simon Marsh subscripti...@burble.com wrote: I (mostly) understand this when considering an analogue mixer, but I'm lost on whether there are any similar effects going on with a digital signal ? TBH, I'm not really sure 'mixing' is the right phrase in the digital case, and my apologies if I got that wrong. What's actually going on is sampling one (digital) signal at a rate close to the signal frequency. This gives a vernier effect and the result is a purely digital set of pulses at the beat frequency, aligned to when the signal and sample clock are in phase. It does not have a high frequency component to filter out. Cheers Simon On 11/10/2014 21:11, Bob Camp wrote: Hi Your glitches are (in part) coming from the 20 MHz (10 + 10) component on the mixed signal. Since they have no direct relation to the beat note, filtering them after limiting is not a simple task. It is far easier to keep filter the signal pre-limit than to do so post limit. The other component of the glitches is related to the limiting process. The paper by Collins is a good one to read for information on gain, bandwidth and the limiting process. Again, there is very little you can do “post limit” to sort things out. None of the zero crossings you are getting may be “correct”. It’s not simply a process of picking one out of the group. —— Some math: You have two 10 MHz signals and a (say) 10 Hz beat note. You are looking for 1x10^-13. You get 1x10^-6 from the downconversion. You need to get 1x10^-7 out of the beat note. Put another way, 1x10^-13 at 10 MHz is 1x10^-5 Hz. If your beat note is 3 V p-p, it will cover 6V every 1/10 second. It’s about 1.2X faster than a triangle wave as it zero crosses (memory may be failing me here), so that makes it equal to a 7.2V triangle excursion. 1x10^-6 of 7.2V is 7.2 microvolts. That’s how accurate your limiter / filter combination needs to be, pre-limiting. It can be in a fairly narrow bandwidth, so it’s not quite as daunting as a radio front end. Since you have a very large signal, and very small noise, the normal “dithering will help me” effect of the noise can not be counted on. The thing you *want* to come up with is essentially a random signal (ADEV), so massive filtering will not do the trick either. Bob On Oct 11, 2014, at 3:33 PM, Robert Darby bobda...@triad.rr.com wrote: ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Digital Mixing with a BeagleBone Black and D Flip Flop
Bob Camp, Bob, Simon is talking about the sampler versus a true mixer. This is the idea I asked you about some months ago when I asked about how the digital filter functions. You were kind to explain the filter method in terms of buckets. You are of course correct that the resolution is low, 100 ns for a 10 MHz DUT with a 10 Hz frequency offset but the hetrodyne factor takes the theoretical resolution to 100 fs. That's not shabby for a very low cost DDMTD. And of course, the actual noise floor will not be close to this but potentially it's better than a 5370 and a lot easier to maintain. :o) Simon, I have a 4 channel 1 ns tagger working but I can't successfully link the FTDI library to a c program so doing this in hardware looks far more attractive to me. Here's how I see it at this point: -- Objective: --A four channel DDMTD with 44 bit time tags delivered over the USB port --At least 100 Hz beat frquency on each channel --The hardware is capable of much higher rates but increasing the beat frequency offset --degrades resolution and realistically the device will probably be used at 5 or 10 Hz -- -- Additional Hardware Required: --A wing with three or five LTC6957-1 low phase noise buffers to convert sine inputs into --high speed low-jitter square waves using LVPECL differential outputs --Either an oscillator offset by the beat frequency or a DDS frequency generator --A USB equipped computer -- --Architecture --Differential inputs are fed to the master clock, thence to the D flip-flops clocks --Differential inputs for each channel are fed to the data inputs for each flip-flop --The master clock drives a 44 bit counter which is common to all four channels --Each channel has two independent counters, provisionally 14 bit, designated high and low --The low counter first establishes a low state without transitions i.e. it times out --After the low counter times out, the flip-flop is armed --The first high output at q resets and starts both high and low counters - whichever counts depends on whether q is high or low --Every time the high and low counters match we store the 44 bit count; each new match replaces the previous one --At some point (2^14 highs) the high counter will roll over - hopefully low will have stopped counting much earlier --The highest stored match should meet the equal count criteria as described in the P. Moreira and I. Darwazeh paper --Since there are four channels it will be necessary to multiplex the time tags into the fifo --The multiplexer will add 1 bit per channel for one-hot channel id coding --The 48 bits will clock into a 48 bit to 8 bit fifo thence to an 8 bit USB port I believe you can have multiple points where the two counts match but I don't have any data to confirm that. I played with this in excel and when you feed it ones and zeros in a distribution that looks like the typical output out of a digital sampler it is possible to get multiple matches. My intention is to go with the last crossing and the scheme mentioned above does this rather trivially. Unless, of course, I'm missing something and I usually do. I've got a Pipistrello board and it has the option of an asynchronous fifo USB interface; since I've already paid my dues on that I'll just use that code again. The data rate is so low that snail mail would work. The computer gets a series of time tags and your program has to pair up the channels to get the deltas. Getting time tags lets you compare three or four devices simultaneously and facilitates three-cornered hat calculations. I suspect that's a lot easier to say than do but we'll cross that bridge if we ever get there. Also time tags permit continuous sampling; there's no counter dead-time which I think can be an issue when it causes variable data sampling rates. Bob Camp mention Collins low jitter hard limiters but I suspect that's much more of an issue on the very shallow slopes you see on 5 or 10 Hz mixer outputs. The LTC6957 is probably overkill on 10 MHz inputs but I believe they're a tad better than a 74AC gate, but then again maybe not all that much better. Lot more expensive. Bob C discussed sine to square conversion in a recent post (IIRC) perhaps in connection with 5V to 3.3V conversion, and for a low cost solution the 74AC gate looks pretty good and they're easy to dead bug. I'm out of spit. Later bob On 10/11/2014 9:17 PM, Bob Camp wrote: Hi Ok, a little more data: You can hook your flip flop up as a sampler or as a full blown mixer. Hooked up as a full blown mixer, you get the 20 MHz and 10 Hz signals. You also get more resolution on the 10 Hz. Either way, the 10 Hz is still a beat note. In the case of a sampler, the filter is there for edge jitter. With a sampler, your data is
Re: [time-nuts] Digital Mixing with a BeagleBone Black and D Flip Flop
Original thread on DDMTD in 2008: https://www.febo.com/pipermail/time-nuts/2008-December/034955.html Later comment on using a shift register to minimise metastability issues: https://www.febo.com/pipermail/time-nuts/2011-August/058648.html Bruce On Sunday, October 12, 2014 12:14:27 AM Robert Darby wrote: Bob Camp, Bob, Simon is talking about the sampler versus a true mixer. This is the idea I asked you about some months ago when I asked about how the digital filter functions. You were kind to explain the filter method in terms of buckets. You are of course correct that the resolution is low, 100 ns for a 10 MHz DUT with a 10 Hz frequency offset but the hetrodyne factor takes the theoretical resolution to 100 fs. That's not shabby for a very low cost DDMTD. And of course, the actual noise floor will not be close to this but potentially it's better than a 5370 and a lot easier to maintain. :o) Simon, I have a 4 channel 1 ns tagger working but I can't successfully link the FTDI library to a c program so doing this in hardware looks far more attractive to me. Here's how I see it at this point: -- Objective: --A four channel DDMTD with 44 bit time tags delivered over the USB port --At least 100 Hz beat frquency on each channel --The hardware is capable of much higher rates but increasing the beat frequency offset --degrades resolution and realistically the device will probably be used at 5 or 10 Hz -- -- Additional Hardware Required: --A wing with three or five LTC6957-1 low phase noise buffers to convert sine inputs into --high speed low-jitter square waves using LVPECL differential outputs --Either an oscillator offset by the beat frequency or a DDS frequency generator --A USB equipped computer -- --Architecture --Differential inputs are fed to the master clock, thence to the D flip-flops clocks --Differential inputs for each channel are fed to the data inputs for each flip-flop --The master clock drives a 44 bit counter which is common to all four channels --Each channel has two independent counters, provisionally 14 bit, designated high and low --The low counter first establishes a low state without transitions i.e. it times out --After the low counter times out, the flip-flop is armed --The first high output at q resets and starts both high and low counters - whichever counts depends on whether q is high or low --Every time the high and low counters match we store the 44 bit count; each new match replaces the previous one --At some point (2^14 highs) the high counter will roll over - hopefully low will have stopped counting much earlier --The highest stored match should meet the equal count criteria as described in the P. Moreira and I. Darwazeh paper --Since there are four channels it will be necessary to multiplex the time tags into the fifo --The multiplexer will add 1 bit per channel for one-hot channel id coding --The 48 bits will clock into a 48 bit to 8 bit fifo thence to an 8 bit USB port I believe you can have multiple points where the two counts match but I don't have any data to confirm that. I played with this in excel and when you feed it ones and zeros in a distribution that looks like the typical output out of a digital sampler it is possible to get multiple matches. My intention is to go with the last crossing and the scheme mentioned above does this rather trivially. Unless, of course, I'm missing something and I usually do. I've got a Pipistrello board and it has the option of an asynchronous fifo USB interface; since I've already paid my dues on that I'll just use that code again. The data rate is so low that snail mail would work. The computer gets a series of time tags and your program has to pair up the channels to get the deltas. Getting time tags lets you compare three or four devices simultaneously and facilitates three-cornered hat calculations. I suspect that's a lot easier to say than do but we'll cross that bridge if we ever get there. Also time tags permit continuous sampling; there's no counter dead-time which I think can be an issue when it causes variable data sampling rates. Bob Camp mention Collins low jitter hard limiters but I suspect that's much more of an issue on the very shallow slopes you see on 5 or 10 Hz mixer outputs. The LTC6957 is probably overkill on 10 MHz inputs but I believe they're a tad better than a 74AC gate, but then again maybe not all that much better. Lot more expensive. Bob C discussed sine to square conversion in a recent post (IIRC) perhaps in connection with 5V to 3.3V conversion, and for a low cost solution the 74AC gate looks pretty good and they're easy to dead bug. I'm out of spit. Later bob On 10/11/2014 9:17 PM, Bob Camp wrote: Hi Ok,
Re: [time-nuts] Digital Mixing with a BeagleBone Black and D Flip Flop
Simon, This is a fantastic idea and I have every intention of trying to replicate it at home with tools on hand. Thanks for sharing, and I hope you can show off some results. On Wed, Oct 8, 2014 at 1:09 PM, Simon Marsh subscripti...@burble.com wrote: I've been a lurker on time-nuts for a while, most of the discussion being way over my head, but I thought there may be interest in some proof of concept code I've written for simple digital hetrodyne mixing using just a BeagleBone Black and an external dual D Flip Flop. The idea is based on the following article which describes creating a digital DMTD with an FPGA for clocks @ 125mhz: http://www.ee.ucl.ac.uk/lcs/previous/LCS2011/LCS1136.pdf My setup follows the same principle, but scaled down to 10mhz to make it as simple as possible (and not require an FPGA). The hardware side is just a 74AC74 dual flip flop to sample the input clocks being tested. Instead of having a helper PLL for the mixer frequency, I simply have a 3rd, de-tuned oscillator. The output from the two flip-flops together with the mixer clock are fed to the BBB. On the BBB, the approach is to do as little as possible in real time using a PRU core, and then post-process on the ARM core afterwards. The BBB PRU has a 16-bit, asynchronous, parallel, capture mode, where 16 GPIO pins can be latched based on an external clock (described in section 4.4.1.2.3.2 of the TRM for those interested). In this case, the external clock is the mixer oscillator. All the PRU needs to do is wait for the sample to take place, read the GPIOs and store the results in main memory. The PRU is plenty fast enough to capture samples @10mhz and, in theory at least, each PRU could sample up to 16 clocks simultaneously (depending on whether the relevant GPIO pins were free). Once the sampling is complete, the ARM core can process the results in its own time, and this includes any more complicated algorithms for de-glitching etc The theoretical minimum time resolution depends on the beat frequency and is described in the article, for example with a beat frequency of 50 hz the minimum resolution is 50 / (1000 - 50)*1000 = ~5E-13. In practice the available accuracy is determined by the stability of the mixer clock and noise of the setup. The impact of this noise is described in the article as glitching and there are some suggested ways for processing this out. I'm trying this on an open bench, with basic oscillators, using pluggable breadboard and lots of hanging wires, I'm not at risk of getting near the theoretical limit quite yet :) Note that the BBB itself has no impact on the accuracy or noise of the raw data. Once the input is latched at the flip-flop, the only bit of critical timing required is to ensure that samples can be captured fast enough and that the flip-flop state is captured when it is stable (i.e. not transitioning). I make no excuses that this is very simplistic, and there are many, many ways that it can (should!) be improved. For me the next steps will probably be: 1) Get off the breadboard and focus a bit more on getting the signals to the flip-flop with a 'reasonable' amount of noise. 2) Improve the PRU code so that it stores transitions and not just the raw samples, this would offload a significant bit of work from the ARM core, save a load of memory and allow continuous streaming of data (instead of the current one shot approach). 3) Experimentation with different algorithms for processing the data on the ARM. I don't think anyone has posted a similar set up, so any feedback on whether the approach is viable or I'm wasting my time are welcome. I've posted the code to Google drive for anyone to take a look. It shouldn't be too difficult to reproduce if someone wants to, but again please remember it's just 'prove it can be done' code. https://drive.google.com/open?id=0BzvFGRfj4aFkblAwcWxGNHdCSDgauthuser=0 Cheers Simon ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Digital Mixing with a BeagleBone Black and D Flip Flop
Simon, I breadboaded a set-up in March using 74AC74's and two 10 MHz Micro Crystal oscillators (5V square wave), one as the coherent source and one as the 10Hz offset clock. I had no glitch filtering as described in the article you cite (CERN's White Rabbit Project, sub nanosecond timing over ethernet) but found the positive zero crossing was very clean. The negative crossing not so much; no idea why one edge was clean and the other not. To ensure I only measured the rising clock edge and not the noise on the falling clock, I programmed ATiny's (digital 555?) to arm the D-flops only after a period of continuous low states. In any event, the lash up, as measure by a 5370, produced a clean linear noise floor of 8e-12 at 1s. I regret to note that's very slightly better than my results from the Bill Riley DMTD device. That's an indictment of my analog building skills, not his design. It's also nicely below a 5370 on it's own and needs only a simple 10 MHz counter for output. The zero crossing detectors for sine wave oscillator input will perhaps be more critical. This was encouraging enough that I thought I'd try to build an FPGA version of the same. The DDMTD is temporarily on back burner while I try to get a four channel 1ns resolution time tagger running on the FPGA to use with the DMTD. Almost there. I look forward to hearing your results with the BBB; keep us posted. Bob Darby On 10/9/2014 1:34 AM, Andrew Rodland wrote: Simon, This is a fantastic idea and I have every intention of trying to replicate it at home with tools on hand. Thanks for sharing, and I hope you can show off some results. On Wed, Oct 8, 2014 at 1:09 PM, Simon Marsh subscripti...@burble.com wrote: I've been a lurker on time-nuts for a while, most of the discussion being way over my head, but I thought there may be interest in some proof of concept code I've written for simple digital hetrodyne mixing using just a BeagleBone Black and an external dual D Flip Flop. The idea is based on the following article which describes creating a digital DMTD with an FPGA for clocks @ 125mhz: http://www.ee.ucl.ac.uk/lcs/previous/LCS2011/LCS1136.pdf My setup follows the same principle, but scaled down to 10mhz to make it as simple as possible (and not require an FPGA). The hardware side is just a 74AC74 dual flip flop to sample the input clocks being tested. Instead of having a helper PLL for the mixer frequency, I simply have a 3rd, de-tuned oscillator. The output from the two flip-flops together with the mixer clock are fed to the BBB. On the BBB, the approach is to do as little as possible in real time using a PRU core, and then post-process on the ARM core afterwards. The BBB PRU has a 16-bit, asynchronous, parallel, capture mode, where 16 GPIO pins can be latched based on an external clock (described in section 4.4.1.2.3.2 of the TRM for those interested). In this case, the external clock is the mixer oscillator. All the PRU needs to do is wait for the sample to take place, read the GPIOs and store the results in main memory. The PRU is plenty fast enough to capture samples @10mhz and, in theory at least, each PRU could sample up to 16 clocks simultaneously (depending on whether the relevant GPIO pins were free). Once the sampling is complete, the ARM core can process the results in its own time, and this includes any more complicated algorithms for de-glitching etc The theoretical minimum time resolution depends on the beat frequency and is described in the article, for example with a beat frequency of 50 hz the minimum resolution is 50 / (1000 - 50)*1000 = ~5E-13. In practice the available accuracy is determined by the stability of the mixer clock and noise of the setup. The impact of this noise is described in the article as glitching and there are some suggested ways for processing this out. I'm trying this on an open bench, with basic oscillators, using pluggable breadboard and lots of hanging wires, I'm not at risk of getting near the theoretical limit quite yet :) Note that the BBB itself has no impact on the accuracy or noise of the raw data. Once the input is latched at the flip-flop, the only bit of critical timing required is to ensure that samples can be captured fast enough and that the flip-flop state is captured when it is stable (i.e. not transitioning). I make no excuses that this is very simplistic, and there are many, many ways that it can (should!) be improved. For me the next steps will probably be: 1) Get off the breadboard and focus a bit more on getting the signals to the flip-flop with a 'reasonable' amount of noise. 2) Improve the PRU code so that it stores transitions and not just the raw samples, this would offload a significant bit of work from the ARM core, save a load of memory and allow continuous streaming of data (instead of the current one shot approach). 3) Experimentation with different algorithms for processing the data on the ARM. I don't think anyone
[time-nuts] Digital Mixing with a BeagleBone Black and D Flip Flop
I've been a lurker on time-nuts for a while, most of the discussion being way over my head, but I thought there may be interest in some proof of concept code I've written for simple digital hetrodyne mixing using just a BeagleBone Black and an external dual D Flip Flop. The idea is based on the following article which describes creating a digital DMTD with an FPGA for clocks @ 125mhz: http://www.ee.ucl.ac.uk/lcs/previous/LCS2011/LCS1136.pdf My setup follows the same principle, but scaled down to 10mhz to make it as simple as possible (and not require an FPGA). The hardware side is just a 74AC74 dual flip flop to sample the input clocks being tested. Instead of having a helper PLL for the mixer frequency, I simply have a 3rd, de-tuned oscillator. The output from the two flip-flops together with the mixer clock are fed to the BBB. On the BBB, the approach is to do as little as possible in real time using a PRU core, and then post-process on the ARM core afterwards. The BBB PRU has a 16-bit, asynchronous, parallel, capture mode, where 16 GPIO pins can be latched based on an external clock (described in section 4.4.1.2.3.2 of the TRM for those interested). In this case, the external clock is the mixer oscillator. All the PRU needs to do is wait for the sample to take place, read the GPIOs and store the results in main memory. The PRU is plenty fast enough to capture samples @10mhz and, in theory at least, each PRU could sample up to 16 clocks simultaneously (depending on whether the relevant GPIO pins were free). Once the sampling is complete, the ARM core can process the results in its own time, and this includes any more complicated algorithms for de-glitching etc The theoretical minimum time resolution depends on the beat frequency and is described in the article, for example with a beat frequency of 50 hz the minimum resolution is 50 / (1000 - 50)*1000 = ~5E-13. In practice the available accuracy is determined by the stability of the mixer clock and noise of the setup. The impact of this noise is described in the article as glitching and there are some suggested ways for processing this out. I'm trying this on an open bench, with basic oscillators, using pluggable breadboard and lots of hanging wires, I'm not at risk of getting near the theoretical limit quite yet :) Note that the BBB itself has no impact on the accuracy or noise of the raw data. Once the input is latched at the flip-flop, the only bit of critical timing required is to ensure that samples can be captured fast enough and that the flip-flop state is captured when it is stable (i.e. not transitioning). I make no excuses that this is very simplistic, and there are many, many ways that it can (should!) be improved. For me the next steps will probably be: 1) Get off the breadboard and focus a bit more on getting the signals to the flip-flop with a 'reasonable' amount of noise. 2) Improve the PRU code so that it stores transitions and not just the raw samples, this would offload a significant bit of work from the ARM core, save a load of memory and allow continuous streaming of data (instead of the current one shot approach). 3) Experimentation with different algorithms for processing the data on the ARM. I don't think anyone has posted a similar set up, so any feedback on whether the approach is viable or I'm wasting my time are welcome. I've posted the code to Google drive for anyone to take a look. It shouldn't be too difficult to reproduce if someone wants to, but again please remember it's just 'prove it can be done' code. https://drive.google.com/open?id=0BzvFGRfj4aFkblAwcWxGNHdCSDgauthuser=0 Cheers Simon ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
