The current implementation used in WR was developed by Tomasz
Wlostowski in the frame of his MSc thesis, following the ideas of
Pablo Alvarez which Bruce pointed to earlier. As you can see in
Tomasz's dissertation [1], there was not a lot of investigation on
optimal strategies for DDTMD
Thanks Pablo.
I've been finding that my implementation is a very good noise detector
(in all kinds of fun ways) and my most recent effort has been at the
hardware level in better layout, shielding and in reducing the number of
noise sources.
The impact of non-random noise is that
http://trs-new.jpl.nasa.gov/dspace/bitstream/2014/36903/1/01-2617.pdf
among other things illustrates a modified approach to the offset generator by
replacing the intermediate phase locked VCXO with a bandpass filter.
Bruce
On Thursday, October 16, 2014 1:03 PM, Bert Kehren via time-nuts
Hi
I wonder what they are using for the “lpf / zero crossers” in that version.
Bob
On Oct 16, 2014, at 4:07 AM, Bruce Griffiths bruce.griffi...@xtra.co.nz wrote:
http://trs-new.jpl.nasa.gov/dspace/bitstream/2014/36903/1/01-2617.pdf
among other things illustrates a modified approach to the
On 10/16/14, 3:59 AM, Bob Camp wrote:
Hi
I wonder what they are using for the “lpf / zero crossers” in that version.
Aren't those the usual limiter chain? Described in earlier papers by the
same folks. There was a lot of discussion about this architecture on
the list a few years ago.
Am 16.10.2014 um 02:02 schrieb Bert Kehren via time-nuts:
Take a look at Potato chips yes Potato I have used them with good results
Bert Kehren
330551715157
They don't impress me much. Yes, they can drive my 0.6pF active probes
without a
problem, but connecting just one of their own
Hi
I guess I should have been a bit more specific.
The latest paper is from about 10 years after their papers on limiters. I
wonder if they have any “new stuff” in the limiter part of the new(er) system.
I also wonder if there’s been any progress in the 8 years since the latest
paper.
Bob
Hi
Well, been there / done that in this case. The 100EP noise floor is nothing
exciting. It’s 1/F corner isn’t very impressive either.
Bob
On Oct 16, 2014, at 12:23 PM, Gerhard Hoffmann dk...@arcor.de wrote:
Am 16.10.2014 um 02:02 schrieb Bert Kehren via time-nuts:
Take a look at Potato
The use of a synchroniser loses no information apart from fine details about
the metastability response of the sampling flipflop. With a 10Hz offset and a
10MHz clock the sampling resolution is 100fs with the phase difference between
the flipflop clock and data input transitions changing
Hi Simon, I am the initiator and leader of the White Rabbit project,
which in the context of these discussions is more a disqualifier than
anything, since I do very little technical work these days,
unfortunately. Please forgive me if I have misunderstood what you are
trying to do. Some tentative
Am 15.10.2014 um 11:29 schrieb Bruce Griffiths:
Typically a 74HC164 shift register has internal cycle to cycle sampling jitter
of about 4ps or so when used as a mixer, a 74AC device has about 1/4 of this
jitter or around 1ps. Faster CMOS devices have even less internal jitter.
Hi,
do you
Javier,
I'm merely implementing a poor man's copy of the ideas in the White
Rabbit project, so thank you for taking the time to post.
On 15/10/2014 14:27, Javier Serrano wrote:
[snip]
Do you have a precise idea of what the offset in frequency is between
your DUT(s) and the slightly-offset
On Wednesday, October 15, 2014 03:27:41 PM Javier Serrano wrote:
Do you have a precise idea of what the offset in frequency is between
your DUT(s) and the slightly-offset oscillator? If that offset is too
big compared with the jitter of your clock signals and your
flip-flops, that would
Hi Simon,
I need to find some spare time, something which is not in rich volumen
right now.
Cheers,
Magnus
On 10/15/2014 09:53 AM, Simon Marsh wrote:
Hi Magnus,
What was the outcome ? Did it work, and what were the constraints or
problems encountered ?
Cheers
Simon
On 15/10/2014
Hi
Most ECL families have more trouble with 1/F noise than fast silicon saturated
logic. That makes them poor candidates for this sort of thing.
Bob
On Oct 15, 2014, at 9:13 AM, Gerhard Hoffmann dk...@arcor.de wrote:
Am 15.10.2014 um 11:29 schrieb Bruce Griffiths:
Typically a 74HC164 shift
Take a look at Potato chips yes Potato I have used them with good results
Bert Kehren
330551715157
In a message dated 10/15/2014 6:44:47 P.M. Eastern Daylight Time,
kb...@n1k.org writes:
Hi
Most ECL families have more trouble with 1/F noise than fast silicon
saturated
You beat me :)
http://www.potatosemi.com/
They sell low quantities thru Ebay, like this:
http://www.ebay.com/itm/7400-G-Series-GHz-TTL-CMOS-logic-IC-14pin-SOIC-QTY-1-/330772425575?pt=LH_DefaultDomain_0hash=item4d0392ab67
Daniel
On 15/10/2014 21:02, Bert Kehren via time-nuts wrote:
Take a
Hi
Is it silicon or is it something more exotic? In general, exotic is not good
for 1/F noise.
Bob
On Oct 15, 2014, at 9:36 PM, Daniel Mendes dmend...@gmail.com wrote:
You beat me :)
http://www.potatosemi.com/
They sell low quantities thru Ebay, like this:
kb...@n1k.org said:
Is it silicon or is it something more exotic? In general, exotic is not good
for 1/F noise.
Data sheets say submicron CMOS.
--
These are my opinions. I hate spam.
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To
Many thanks to Bob D, Bob C, Bruce and Magnus for the links, references
and being patient.
I've spent a bit of time looking at the glitching with the idea of
evaluating a few different algorithms to deal with it. I also looked a
bit at the hardware and instead of very simply having a single
two D-flops in series make a synchronizer!? (see the input-channels on
Nutt-type time interval counters)
http://chipdesignmag.com/print.php?articleId=32?issueId=5
you've lost all your noise - but you've also got rid of all the signal - so
not great for improving SNR.
On Tue, Oct 14, 2014 at 6:32
(to the plane) with a near zero lead length capacitor.
Bob L.
Sent: Tuesday, October 14, 2014 at 11:32 AM
From: Simon Marsh subscripti...@burble.com
To: Discussion of precise time and frequency measurement time-nuts@febo.com
Subject: Re: [time-nuts] Digital Mixing with a BeagleBone Black and D
the photos, data,
and plots coming.
Thanks,
/tvb
- Original Message -
From: Simon Marsh subscripti...@burble.com
To: time-nuts@febo.com
Sent: Tuesday, October 14, 2014 9:34 AM
Subject: Re: [time-nuts] Digital Mixing with a BeagleBone Black and D Flip Flop
Yes, I do understand I'm
: Re: [time-nuts] Digital Mixing with a BeagleBone Black and D Flip
Flop
... 74AC74 ... knocked up on some pluggable breadboard
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Sent: Tuesday, October 14, 2014 9:34 AM
Subject: Re: [time-nuts] Digital Mixing with a BeagleBone Black and D Flip Flop
Yes, I do understand I'm asking for trouble, though I kinda expected to
see more noise rather than less.
I guess its time to break out the soldering iron.
Cheers
Simon
Bruce,
Thanks, I recall the thread from reading the digests. The CERN code is
wonderfully compact but not immediately obvious to a novice to VHDL.
Perhaps one day the light will come on.
Bob
On 10/12/2014 12:27 AM, Bruce Griffiths wrote:
Original thread on DDMTD in 2008:
Hi
With *all* of these “drop to a lower frequency” approaches, the theoretical
resolution is very good compared to the useful resolution. A straight mix to 1
Hz into a 5370 is a great example. The filter / limiter is the thing that sets
the useful resolution rather than the theoretical
Interesting 2008 discussion on using a sound-card ADC for a DMTD system!
Did anyone build a DMTD-system and measure the performance using a 24-bit
soundcard?
Does it matter that the ADC in the sound-card is probably clocked by a
crystal clock that is 50ppm off and has bad ADEV?
Anders
On Sun,
anders.e.e.wal...@gmail.com said:
Does it matter that the ADC in the sound-card is probably clocked by a
crystal clock that is 50ppm off and has bad ADEV?
You can calibrate the clock on the ADC.
One way is to feed a known reference frequency in on the other channel.
(That's assuming you
Hi
If you are mixing down to 10 Hz, and are looking for 1x10^-7 on the 10 Hz, that
equates to a stability / accuracy spec of 0.1 ppm on the ADC clock.
A 20 to 100 ppm offset on the clock is not all that unusual. Calibrating out
initial offset to 1 ppm is pretty simple. If you can poke a
HI
A little more information:
If you are doing the ADC thing, you still need to estimate zero crossings. In
all likelihood you would be doing bandpass filtering first (say 8 Hz to 12 Hz)
on your 10 Hz note. Next you would do some sort of estimator to get the zero
cross. A curve fit is one
Robert,
Bob Camp mention Collins low jitter hard limiters but I suspect that's
much more of an issue on the very shallow slopes you see on 5 or 10 Hz
mixer outputs. The LTC6957 is probably overkill on 10 MHz inputs but I
believe they're a tad better than a 74AC gate, but then again maybe not
Hi,
Some attempts have been made. Never got around to write the needed code.
On 10/12/2014 08:37 PM, Hal Murray wrote:
anders.e.e.wal...@gmail.com said:
Does it matter that the ADC in the sound-card is probably clocked by a
crystal clock that is 50ppm off and has bad ADEV?
You can
Increasing the beat frequency to find a balance between 1/f noise and
f/delta-f amplification may be worth doing and have been seen done to
find optimum performance. If you use hard limiters or audio channels
to achieve it is however a little detail.
The benefit of audio channels is that the
Hi
The 1/F noise vs beat note “amplification” tradeoff is what pushes me up to 10
Hz rather than staying down around 1 Hz with most setups. It’s also a rational
offset to achieve at 10 MHz with common OCXO’s. Once you get past about 20 Hz,
your OCXO choices diminish.
Bob
On Oct 12, 2014, at
Bob,
I know, and I know you know. Just let others see how things connect up.
Still have some 10.000110 MHz OCXOs lying around.
Cheers,
Magnus
On 10/13/2014 02:15 AM, Bob Camp wrote:
Hi
The 1/F noise vs beat note “amplification” tradeoff is what pushes me up to 10
Hz rather than staying
Hi
If odd “almost 10 MHz OCXO’s were more common, you could indeed have a bit more
freedom on the offset. DDS is sometimes used. DDS spurs (which can be *very*
close in) can be both hard to predict and hard to spot in the data. An OCXO is
a much better bet unless you have a lot of time on your
Simon,
Welcome to the tangential world.
I'm sure the clean edge I saw was an aberration, perhaps analogous to
phase locking in oscillators; I don't think it's desirable because
common sense tells you that with imperfect clocks and small phase
differences there are bound to be some number of
Hi
If you are looking at the low frequency beat note out of a mixer and seeing
multiple transitions on an edge - you filtering or your limiter are not up to
the task. In most cases it’s the filter, but it can be either.
Bob
On Oct 11, 2014, at 9:10 AM, Robert Darby bobda...@triad.rr.com
In this case, it seems reasonable that these multiple transitions are to
be expected as there isn't any filtering that takes place in hardware
prior to samples being captured by the BBB. The equivalent of the
filtering/zero crossing detection takes place in software in the edge
detection
Bob we are using digital mixers in some other applications but what
surprised me is your comment on the Riley DMTD. We have a couple of slightly
modified Riley's and see any where from 1.44 to 3.84 E-14 at 1 second. Bill
also
sows data below 1 E-13 at 1 second. Presently looking at braking
Yeah, breaks my heart but I'm not real good (try real bad) at
troubleshooting electronics (so why am i here?).
As I noted in my earlier post, the issue lies in my construction and
lack of knowledge re electronic fundamentals. I have the greatest
respect for Mr. Riley and I do not want my
Simon,
If I can rephrase your first post, you plan to capture the state
transitions along with their timing and subsequently post-process them
to determine the time from one zero-crossing to another. Each
zero-crossing is the sum of number of closely spaced state changes
(glitches) and some
Hi
Your glitches are (in part) coming from the 20 MHz (10 + 10) component on the
mixed signal. Since they have no direct relation to the beat note, filtering
them after limiting is not a simple task. It is far easier to keep filter the
signal pre-limit than to do so post limit.
The other
I (mostly) understand this when considering an analogue mixer, but I'm
lost on whether there are any similar effects going on with a digital
signal ?
TBH, I'm not really sure 'mixing' is the right phrase in the digital
case, and my apologies if I got that wrong.
What's actually going on is
On 11/10/2014 20:33, Robert Darby wrote:
If I can rephrase your first post, you plan to capture the state
transitions along with their timing and subsequently post-process them
to determine the time from one zero-crossing to another. Each
zero-crossing is the sum of number of closely spaced
Hi
The mixer you are using will give you a sine wave output *if* it’s properly
filtered. A mixer is a mixer.
Bob
On Oct 11, 2014, at 6:31 PM, Simon Marsh subscripti...@burble.com wrote:
I (mostly) understand this when considering an analogue mixer, but I'm lost
on whether there are any
Hi
Ok, a little more data:
You can hook your flip flop up as a sampler or as a full blown mixer. Hooked up
as a full blown mixer, you get the 20 MHz and 10 Hz signals. You also get more
resolution on the 10 Hz. Either way, the 10 Hz is still a beat note. In the
case of a sampler, the filter
Bob Camp,
Bob, Simon is talking about the sampler versus a true mixer. This is
the idea I asked you about some months ago when I asked about how the
digital filter functions. You were kind to explain the filter method in
terms of buckets. You are of course correct that the resolution is
Original thread on DDMTD in 2008:
https://www.febo.com/pipermail/time-nuts/2008-December/034955.html
Later comment on using a shift register to
minimise metastability issues:
https://www.febo.com/pipermail/time-nuts/2011-August/058648.html
Bruce
On Sunday, October 12, 2014 12:14:27 AM Robert
Simon,
This is a fantastic idea and I have every intention of trying to
replicate it at home with tools on hand. Thanks for sharing, and I
hope you can show off some results.
On Wed, Oct 8, 2014 at 1:09 PM, Simon Marsh subscripti...@burble.com wrote:
I've been a lurker on time-nuts for a while,
Simon,
I breadboaded a set-up in March using 74AC74's and two 10 MHz Micro
Crystal oscillators (5V square wave), one as the coherent source and one
as the 10Hz offset clock. I had no glitch filtering as described in the
article you cite (CERN's White Rabbit Project, sub nanosecond timing
I've been a lurker on time-nuts for a while, most of the discussion
being way over my head, but I thought there may be interest in some
proof of concept code I've written for simple digital hetrodyne mixing
using just a BeagleBone Black and an external dual D Flip Flop.
The idea is based on
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