On 31/08/2021 12:46, Heinrich Schuchardt wrote:
>
>
>
> *Von:* Ard Biesheuvel
> *Gesendet:* 31. August 2021 12:33:56 MESZ
> *An:* Heinrich Schuchardt
> *CC:* Kristian Amlie
> *Betreff:* Re: [PATCH] efi_loader: Omit
Hi Tom,
please pull the following watchdog related patches:
- handling all DM watchdogs in watchdog_reset() (Rasmus)
Here the Azure build, without any issues:
I will take a look on it?
30.08.21 20:39, Tom Rini пише:
> Hey all,
>
> Here's the latest report.
>
> - Forwarded message from scan-ad...@coverity.com -
>
> Date: Mon, 30 Aug 2021 16:58:54 + (UTC)
> From: scan-ad...@coverity.com
> To: tom.r...@gmail.com
> Subject: New Defects reported
There are trivial typos in the Kconfig file. Fix them.
Fixes: d56b4b1974 ("configs: Migrate RBTREE, LZO, CMD_MTDPARTS, CMD_UBI and
CMD_UBIFS")
Fixes: 7264f2928b ("spl: fit: Eanble GZIP support for image decompression")
Signed-off-by: Oleksandr Suvorov
---
lib/Kconfig | 4 ++--
1 file changed,
>From b2516d965ee933bdb10fc158e36dedcf65bd7ce9 Mon Sep 17 00:00:00 2001
From: Dzmitry Sankouski
Date: Fri, 27 Aug 2021 17:47:22 +0300
Subject: [PATCH 1/6 v2] serial: qcom: add support for GENI serial driver
Generic Interface (GENI) Serial Engine (SE) based uart
can be found on newer qualcomm
Hi Pratyush
Thanks for your reply, I want to create "CONFIG_SPI_EXT_INVERT"
to separate extension types.
Changed as below, do you have any suggestion?
ext = nor->cmd_ext_type;
if (!nor->cmd_ext_type) {
nor->cmd_ext_type = SPI_NOR_EXT_REPEAT;
#ifdef
>From b65826c49fee93dd7ded11a848814d8fa79fdb2e Mon Sep 17 00:00:00 2001
From: Dzmitry Sankouski
Date: Sat, 28 Aug 2021 13:53:42 +0300
Subject: [PATCH 2/6 v2] spmi: msm: add arbiter version 5 support
Currently driver supports only version 1 and 2.
Version 5 has slightly different registers
>From 94e21cc200e09c51752e4bb86cfac320a92c48a5 Mon Sep 17 00:00:00 2001
From: Dzmitry Sankouski
Date: Tue, 31 Aug 2021 11:25:37 +0300
Subject: [PATCH 0/6] Add support for SDM845 based boards, and SM-G9600
Snapdragon 845 - hi-end qualcomm chip, introduced in late 2017.
Mostly used in flagship
On Wed, Aug 25, 2021 at 10:12 AM Vladimir Oltean wrote:
>
> On Wed, Aug 25, 2021 at 10:26:10AM -0400, Tom Rini wrote:
> > On Wed, Aug 25, 2021 at 05:18:16PM +0300, Vladimir Oltean wrote:
> > > On Wed, Aug 25, 2021 at 10:00:45AM -0400, Tom Rini wrote:
> > > > On Wed, Aug 25, 2021 at 03:58:10PM
On Tue, Aug 31, 2021 at 7:58 PM Oleksandr Suvorov
wrote:
>
> There are trivial typos in the Kconfig file. Fix them.
>
> Fixes: d56b4b1974 ("configs: Migrate RBTREE, LZO, CMD_MTDPARTS, CMD_UBI and
> CMD_UBIFS")
> Fixes: 7264f2928b ("spl: fit: Eanble GZIP support for image decompression")
>
Enable dynamic DDR calibration to have a reliable behavior on edge
temperatures conditions.
Signed-off-by: Max Krummenacher
Signed-off-by: Francesco Dolcini
---
board/toradex/apalis_imx6/apalis_imx6.c | 19 +++
configs/apalis_imx6_defconfig | 1 +
2 files changed,
Enable dynamic DDR calibration to have a reliable behavior on edge
temperatures conditions.
Signed-off-by: Max Krummenacher
Signed-off-by: Francesco Dolcini
---
board/toradex/colibri_imx6/colibri_imx6.c | 22 ++
configs/colibri_imx6_defconfig| 1 +
2 files
Enable dynamic DDR calibration to have a reliable behavior on edge
temperatures conditions for Toradex Apalis and Colibri iMX6 boards.
Francesco Dolcini (2):
colibri-imx6: use dynamic DDR calibration
apalis-imx6: use dynamic DDR calibration
board/toradex/apalis_imx6/apalis_imx6.c | 19
Hi Oleksandr,
On Tue, Aug 31, 2021 at 8:53 AM Oleksandr Suvorov
wrote:
>
> From: Ricardo Salveti
>
> Get Unique ID of SoC iMX7ULP, using the logic described in Fusemap
> (IMX7ULPRMB2_Rev0_Fusemap) attached in the i.MX 7ULP APRM [1].
>
> [1]
>
Hi Tom,
On Tue, Aug 31, 2021 at 9:13 PM Tom Rini wrote:
>
> At least on qemu, and likely other platforms, a load address of
> 0x0200 ends up without our protected range currently. Move this
> down to 0x0100.
What is the protected range?
>
> Cc: Bin Meng
> Signed-off-by: Tom Rini
>
On 31.08.21 11:29, Rasmus Villemoes wrote:
On 31/08/2021 10.17, Stefan Roese wrote:
Hi Rasmus,
I've pulled this patchset now into next [1] and have run it through
CI via Azure. Here an error occurs:
On Tue, Aug 31, 2021 at 11:29:51AM +0200, Rasmus Villemoes wrote:
> On 31/08/2021 10.17, Stefan Roese wrote:
> > Hi Rasmus,
> >
> > I've pulled this patchset now into next [1] and have run it through
> > CI via Azure. Here an error occurs:
> >
> >
On 8/31/21 9:35 AM, Rob Herring wrote:
On Wed, Aug 25, 2021 at 10:12 AM Vladimir Oltean wrote:
On Wed, Aug 25, 2021 at 10:26:10AM -0400, Tom Rini wrote:
On Wed, Aug 25, 2021 at 05:18:16PM +0300, Vladimir Oltean wrote:
On Wed, Aug 25, 2021 at 10:00:45AM -0400, Tom Rini wrote:
On Wed, Aug
Hi Alexandru,
On 8/26/21 11:47 PM, Alexandru Gagniuc wrote:
Hi Patrick,
I proposing a better fix fir the issues I outlined earlier, I made a
classification of the currently supported boot modes.
1) BL1 -> SPL -> U-Boot
2) BL1 -> SPL -> OP-TEE
On Tue, Aug 31, 2021 at 10:11:36PM +0800, Bin Meng wrote:
> Hi Tom,
>
> On Tue, Aug 31, 2021 at 9:13 PM Tom Rini wrote:
> >
> > At least on qemu, and likely other platforms, a load address of
> > 0x0200 ends up without our protected range currently. Move this
> > down to 0x0100.
>
>
>From 520bc565a5a6f62c59f87bbd15a194ee61c103af Mon Sep 17 00:00:00 2001
From: Dzmitry Sankouski
Date: Sun, 29 Aug 2021 21:53:40 +0300
Subject: [PATCH 3/6] pinctrl: qcom: add pinctrl and gpio drivers for SDM845
SoC
Signed-off-by: Dzmitry Sankouski
Cc: Ramon Fried
---
>From 94e21cc200e09c51752e4bb86cfac320a92c48a5 Mon Sep 17 00:00:00 2001
From: Dzmitry Sankouski
Date: Sun, 29 Aug 2021 21:57:33 +0300
Subject: [PATCH 6/6] board: samsung: add Samsung Galaxy S9/S9+(SM-G96x0)
board
Samsung S9 SM-G9600 - Snapdragon SDM845 version of the phone,
for China \ Hong Kong
>From 1deb063fe8d0e527b0fd412505b7614462c7fd19 Mon Sep 17 00:00:00 2001
From: Dzmitry Sankouski
Date: Sun, 29 Aug 2021 21:55:31 +0300
Subject: [PATCH 5/6] SoC: qcom: add support for SDM845
Hi-end qualcomm chip, introduced in late 2017.
Mostly used in flagship phones and tablets of 2018.
On 31/08/2021 10.17, Stefan Roese wrote:
> Hi Rasmus,
>
> I've pulled this patchset now into next [1] and have run it through
> CI via Azure. Here an error occurs:
>
>
>From 647a2cd58fff0e9d7e232dc5970071c5c91bb09f Mon Sep 17 00:00:00 2001
From: Dzmitry Sankouski
Date: Sun, 29 Aug 2021 21:54:57 +0300
Subject: [PATCH 4/6] clocks: qcom: add clocks for SDM845 debug uart
Allows to change clock frequency of debug uart,
thus supporting wide range of baudrates.
From: Ricardo Salveti
Get Unique ID of SoC iMX7ULP, using the logic described in Fusemap
(IMX7ULPRMB2_Rev0_Fusemap) attached in the i.MX 7ULP APRM [1].
[1]
https://www.nxp.com/docs/en/reference-manual/IMX7ULPRMB2.pdf
Signed-off-by: Ricardo Salveti
Co-developed-by: Oleksandr Suvorov
At least on qemu, and likely other platforms, a load address of
0x0200 ends up without our protected range currently. Move this
down to 0x0100.
Cc: Bin Meng
Signed-off-by: Tom Rini
---
Kconfig | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/Kconfig b/Kconfig
On Tue, Aug 31, 2021 at 07:51:29AM +0200, Stefan Roese wrote:
> Hi Tom,
>
> On 21.08.21 19:50, Tom Rini wrote:
> > We have a number of CONFIG symbols to express the fixed size of system
> > memory. For now, rename CONFIG_DDR_FIXED_SIZE to CONFIG_SYS_SDRAM_SIZE
> > and adjust usage to match that
Hi,
On 8/26/21 11:42 PM, Alexandru Gagniuc wrote:
When OP-TEE is booted as the SPL payload, the stage after OP-TEE is
not guaranteed to be u-boot. Thus the FDT patching in u-boot is not
guaranteed to occur. Add this step to SPL.
The patching by stm32_fdt_setup_mac_addr() is done in SPL, and
The following series takes care of two problems:
a) A potential race when R5 (boot processor) is parsing and loading DM
firmware elf sections way slower than A53 executing.
b) We load the FIT image to the same address as the elf sections. See
[1] as example.
NOTE: Though, in theory, the Device
With Device Manager firmware in an elf file form, we cannot load the FIT
image to the exact same address as any of the executable sections of the
elf file itself is located.
However, the device tree descriptions for the ARMV8 bootloader/OS
includes DDR regions only the final sections in DDR where
DM binary is expected to be an elf file. The expected address of
this elf is in the range of 0xa000_ in DDR. In the current
configuration, elf file is loaded to the exact same address and we
invoke load_elf_image_phdr to decode and memcpy sections of the elf to
the same address range, we are
Hi,
I add in CC the ARM STM STM32MP Maintainers...
On 8/26/21 11:42 PM, Alexandru Gagniuc wrote:
The UART can reliably go up to 200 baud when connected to the
on-board st-link. Unfortunately u-boot will fall back to 115200 unless
higher rates are declared via CONFIG_SYS_BAUDRATE_TABLE.
Hi,
Add in CC the MAINTAINERS
On 8/26/21 11:42 PM, Alexandru Gagniuc wrote:
Falcon mode requires a board-specific mechanism to select between
fast and normal boot. This is done via spl_start_uboot()
Use the B2 button as the selection mechanism. This is connected to
GPIO PA13. Incidentally,
Hi all,
I am working on updating our version of u-boot, and came across something
weird - the SPL hangs after "Trying to load NAND" on the first power-on
boot, but after a watchdog reset or power-on reset, the NAND works fine.
U-Boot SPL 2021.01-00010-g8c91cf967b-dirty (Aug 30 2021 -
On 8/31/21 12:10 PM, Patrick DELAUNAY wrote:
Hi,
On 8/26/21 11:42 PM, Alexandru Gagniuc wrote:
When OP-TEE is booted as the SPL payload, the stage after OP-TEE is
not guaranteed to be u-boot. Thus the FDT patching in u-boot is not
guaranteed to occur. Add this step to SPL.
The patching by
Import HS400 support for iMX7ULP B0 from the Linux kernel:
2eaf5a533afd ("mmc: sdhci-esdhc-imx: Add HS400 support for iMX7ULP")
According to IC suggest, need to clear the STROBE_DLL_CTRL_RESET
before any setting of STROBE_DLL_CTRL register.
USDHC has register bits(bit[27~20] of register
From: Jorge Ramirez-Ortiz
Import data for eSDHC driver for SoC iMX7ULP from the Linux kernel.
Set supported by u-boot flags only.
Signed-off-by: Jorge Ramirez-Ortiz
Signed-off-by: Ricardo Salveti
Co-developed-by: Oleksandr Suvorov
Signed-off-by: Oleksandr Suvorov
---
On 8/31/21 4:54 PM, Patrick DELAUNAY wrote:
Hi Alexandru,
Hi,
On 8/26/21 11:47 PM, Alexandru Gagniuc wrote:
Hi Patrick,
I proposing a better fix fir the issues I outlined earlier, I made a
classification of the currently supported boot modes.
1) BL1 -> SPL -> U-Boot
2) BL1 -> SPL
Hi
On 8/26/21 11:42 PM, Alexandru Gagniuc wrote:
stm32mp_bsec_probe() was skipped for TFABOOT and SPL_BUILD. The idea
of skipping probe() is that we can't access BSEC from the normal
world. This is true with TFABOOT. However, in SPL, we are in the
secure world, so skipping probe is incorrect.
On 8/31/21 1:12 PM, Kristian Amlie wrote:
On 31/08/2021 12:46, Heinrich Schuchardt wrote:
*Von:* Ard Biesheuvel
*Gesendet:* 31. August 2021 12:33:56 MESZ
*An:* Heinrich Schuchardt
*CC:* Kristian Amlie
*Betreff:*
Hi,
On 8/26/21 11:42 PM, Alexandru Gagniuc wrote:
OP-TEE does not take a devicetree for its own use. However, it does
pass the devicetree to the normal world OS. In most cases that will
be some other devicetree-bearing platform, such as linux.
As in other cases where there's an OPTEE payload
On Tue, Aug 31, 2021 at 05:40:25PM +0200, Michael Walle wrote:
> The offical ls1028a binding of the driver uses the following as
Same typo as before.
> compatibles:
> compatible = "fsl,ls1028a-dspi", "fsl,ls1021a-v1.0-dspi";
>
> Add the missing compatible to the driver and update the device
Copy the board device tree files from linux v5.14. On top of the v5.14
dtbs the changes of these two patches are included here which are needed
for u-boot:
https://lore.kernel.org/linux-devicetree/20210831134013.1625527-7-mich...@walle.cc/
Move all the CCSR related device nodes into /soc similiar to the linux
device tree.
Signed-off-by: Michael Walle
---
.../dts/fsl-ls1028a-kontron-sl28-u-boot.dtsi | 4 +
.../dts/fsl-ls1028a-qds-1xxx-sch-30842.dtsi | 2 +-
.../dts/fsl-ls1028a-qds-6xxx-sch-30842.dtsi | 2 +-
The offical ls1028a binding of the driver uses the following as
compatibles:
compatible = "fsl,ls1028a-dspi", "fsl,ls1021a-v1.0-dspi";
Add the missing compatible to the driver and update the device tree.
Signed-off-by: Michael Walle
---
arch/arm/dts/fsl-ls1028a.dtsi | 6 +++---
This node is some hodgepodge between the ddr controller node at SoC
offset 0x108 and some static memory size of 2GiB. Remove this bogus
node because it doesn't seem to be used at all.
Signed-off-by: Michael Walle
---
arch/arm/dts/fsl-ls1028a.dtsi | 6 --
1 file changed, 6 deletions(-)
Update the labels of the nodes to match the kernel ones.
Signed-off-by: Michael Walle
---
.../dts/fsl-ls1028a-kontron-sl28-u-boot.dtsi | 10 +++
.../fsl-ls1028a-kontron-sl28-var1-u-boot.dtsi | 2 +-
.../arm/dts/fsl-ls1028a-kontron-sl28-var1.dts | 6 ++---
The offical ls1028a binding of the driver uses the following as
compatibles:
compatible = "fsl,ls1028a-lpuart";
Add the missing compatible to the driver and update the device tree.
Signed-off-by: Michael Walle
---
arch/arm/dts/fsl-ls1028a.dtsi | 12 ++--
Hi
On 8/26/21 11:42 PM, Alexandru Gagniuc wrote:
We want the optee_copy_fdt_nodes symbols in SPL. This is for cases
when booting an OPTEE payload directly.
Signed-off-by: Alexandru Gagniuc
---
lib/Makefile | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/lib/Makefile
Hi,
On 8/26/21 11:42 PM, Alexandru Gagniuc wrote:
This node is required in SPL when booting an OP-TEE payload. Add it to
the SPL devicetree.
Signed-off-by: Alexandru Gagniuc
---
arch/arm/dts/stm32mp157a-dk1-u-boot.dtsi | 1 +
1 file changed, 1 insertion(+)
diff --git
On Tue, Aug 31, 2021 at 1:42 PM Oleksandr Suvorov
wrote:
>
> From: Jorge Ramirez-Ortiz
>
> Import data for eSDHC driver for SoC iMX7ULP from the Linux kernel.
> Set supported by u-boot flags only.
>
> Signed-off-by: Jorge Ramirez-Ortiz
> Signed-off-by: Ricardo Salveti
> Co-developed-by:
Hi Oleksandr,
On Tue, Aug 31, 2021 at 1:42 PM Oleksandr Suvorov
wrote:
>
> Import HS400 support for iMX7ULP B0 from the Linux kernel:
>
> 2eaf5a533afd ("mmc: sdhci-esdhc-imx: Add HS400 support for iMX7ULP")
>
> According to IC suggest, need to clear the STROBE_DLL_CTRL_RESET
> before any setting
On Tue, Aug 31, 2021 at 05:40:19PM +0200, Michael Walle wrote:
> This series sync the device tree of the LS1028A SoC with the linux one.
> To ease future debugging and reviewing, we first clean up the existing one,
> removing bogus nodes, moving all CCSR related nodes in /soc and update the
>
On 13:20-20210831, Nishanth Menon wrote:
> DM binary is expected to be an elf file. The expected address of
> this elf is in the range of 0xa000_ in DDR. In the current
> configuration, elf file is loaded to the exact same address and we
> invoke load_elf_image_phdr to decod
This series sync the device tree of the LS1028A SoC with the linux one.
To ease future debugging and reviewing, we first clean up the existing one,
removing bogus nodes, moving all CCSR related nodes in /soc and update the
drivers to accept the offical compatible strings.
This was tested on a
According to the linux device tree specification the compatible string
is:
compatible = "arm,sp805", "arm,primecell";
Fix all users in u-boot.
Signed-off-by: Michael Walle
---
arch/arm/dts/fsl-ls1028a.dtsi | 2 +-
arch/arm/dts/hi3660.dtsi | 4 ++--
drivers/watchdog/sp805_wdt.c | 2 +-
The fixup is done for the "fsl,ls1028a-gpu" which isn't any official
device tree binding. Don't break it, but instead add a fixup for another
compatible "vivante,gc" which is the offical one for the GPU on the
LS1028A.
Signed-off-by: Michael Walle
---
Hi
Add in CC the MAINTAINERS.
On 8/26/21 11:42 PM, Alexandru Gagniuc wrote:
This function is needed when loading a FIT image from SPL. It selects
the correct configuration node for the current board. Implement it.
Signed-off-by: Alexandru Gagniuc
---
board/st/stm32mp1/spl.c | 10 ++
On Tue, Aug 31, 2021 at 05:40:23PM +0200, Michael Walle wrote:
> Update the labels of the nodes to match the kernel ones.
>
> Signed-off-by: Michael Walle
> ---
-[ cut here ]-
>From 6583bc615f3e6f49d90fabb2033a49e9eab804dc Mon Sep 17
On Tue, Aug 31, 2021 at 05:40:22PM +0200, Michael Walle wrote:
> This node is some hodgepodge between the ddr controller node at SoC
> offset 0x108 and some static memory size of 2GiB. Remove this bogus
> node because it doesn't seem to be used at all.
>
> Signed-off-by: Michael Walle
> ---
Now that everything is prepared, copy the fsl-ls1028a.dtsi from the
linux kernel v5.14.
Signed-off-by: Michael Walle
---
arch/arm/dts/fsl-ls1028a.dtsi | 1212 +
.../dt-bindings/clock/fsl,qoriq-clockgen.h| 15 +
2 files changed, 958 insertions(+), 269
On 8/31/21 1:58 PM, Oleksandr Suvorov wrote:
There are trivial typos in the Kconfig file. Fix them.
Fixes: d56b4b1974 ("configs: Migrate RBTREE, LZO, CMD_MTDPARTS, CMD_UBI and
CMD_UBIFS")
Fixes: 7264f2928b ("spl: fit: Eanble GZIP support for image decompression")
Signed-off-by: Oleksandr
Jaehoon,
readx_poll_timeout expands to read_poll_timeout which accepts the signature:
read_poll_timeout(op, addr, val, cond, sleep_us, timeout_us)
sdhci_readl requires two arguments, host and SHCI_PRESENT_STATE, which
cannot both be provided to that macro in the addr parameter. One potential
Synchronize with the upstream version as of v5.14 kernel tag
Signed-off-by: Nishanth Menon
---
NOTE: checkpatch complains about BIT() macro usage, but I propose that
we are better off staying in sync with the kernel tag itself.
include/dt-bindings/pinctrl/k3.h | 51
On Tue, Aug 31, 2021 at 05:40:26PM +0200, Michael Walle wrote:
> The offical ls1028a binding of the driver uses the following as
> compatibles:
> compatible = "fsl,ls1028a-lpuart";
s/offical/official/
> diff --git a/drivers/serial/serial_lpuart.c b/drivers/serial/serial_lpuart.c
> index
On Tue, Aug 31, 2021 at 9:21 AM Sean Anderson wrote:
>
> On 8/31/21 9:35 AM, Rob Herring wrote:
> > On Wed, Aug 25, 2021 at 10:12 AM Vladimir Oltean wrote:
> >>
> >> On Wed, Aug 25, 2021 at 10:26:10AM -0400, Tom Rini wrote:
> >>> On Wed, Aug 25, 2021 at 05:18:16PM +0300, Vladimir Oltean wrote:
>
On Tue, Aug 31, 2021 at 05:40:19PM +0200, Michael Walle wrote:
> This series sync the device tree of the LS1028A SoC with the linux one.
> To ease future debugging and reviewing, we first clean up the existing one,
> removing bogus nodes, moving all CCSR related nodes in /soc and update the
>
On Tue, Aug 31, 2021 at 8:34 PM Fabio Estevam wrote:
>
> Hi Oleksandr,
>
> On Tue, Aug 31, 2021 at 1:42 PM Oleksandr Suvorov
> wrote:
> >
> > Import HS400 support for iMX7ULP B0 from the Linux kernel:
> >
> > 2eaf5a533afd ("mmc: sdhci-esdhc-imx: Add HS400 support for iMX7ULP")
> >
> > According
From: Jorge Ramirez-Ortiz
Import data for eSDHC driver for SoC iMX7ULP from the Linux kernel.
Set supported by u-boot flags only.
Signed-off-by: Jorge Ramirez-Ortiz
Signed-off-by: Ricardo Salveti
Co-developed-by: Oleksandr Suvorov
Signed-off-by: Oleksandr Suvorov
Reviewed-by: Fabio Estevam
Import HS400 support for iMX7ULP B0 from the Linux kernel:
2eaf5a533afd ("mmc: sdhci-esdhc-imx: Add HS400 support for iMX7ULP")
According to IC suggest, need to clear the STROBE_DLL_CTRL_RESET
before any setting of STROBE_DLL_CTRL register.
USDHC has register bits(bit[27~20] of register
On Tue, Aug 31, 2021 at 05:40:21PM +0200, Michael Walle wrote:
> Move all the CCSR related device nodes into /soc similiar to the linux
> device tree.
>
> Signed-off-by: Michael Walle
> ---
> .../dts/fsl-ls1028a-kontron-sl28-u-boot.dtsi | 4 +
> .../dts/fsl-ls1028a-qds-1xxx-sch-30842.dtsi
> From: Zong Li
> Sent: Tuesday, August 31, 2021 5:21 PM
> To: Rick Jian-Zhi Chen(陳建志) ; Leo Yu-Chi Liang(梁育齊)
> ; bmeng...@gmail.com; sean...@gmail.com;
> green@sifive.com; paul.walms...@sifive.com; s...@chromium.org;
> u-boot@lists.denx.de
> Cc: Zong Li
> Subject: [PATCH v4 2/4] riscv:
Am 2021-08-31 20:32, schrieb Vladimir Oltean:
On Tue, Aug 31, 2021 at 05:40:25PM +0200, Michael Walle wrote:
The offical ls1028a binding of the driver uses the following as
Same typo as before.
compatibles:
compatible = "fsl,ls1028a-dspi", "fsl,ls1021a-v1.0-dspi";
Add the missing
On Tue, Aug 31, 2021 at 11:35:25PM +0200, Michael Walle wrote:
> Am 2021-08-31 20:32, schrieb Vladimir Oltean:
> > On Tue, Aug 31, 2021 at 05:40:25PM +0200, Michael Walle wrote:
> > > The offical ls1028a binding of the driver uses the following as
> >
> > Same typo as before.
> >
> > >
Am 2021-08-31 23:39, schrieb Vladimir Oltean:
On Tue, Aug 31, 2021 at 11:35:25PM +0200, Michael Walle wrote:
Am 2021-08-31 20:32, schrieb Vladimir Oltean:
> On Tue, Aug 31, 2021 at 05:40:25PM +0200, Michael Walle wrote:
> > The offical ls1028a binding of the driver uses the following as
>
>
Am 1. September 2021 00:03:58 MESZ schrieb Vladimir Oltean
:
>On Tue, Aug 31, 2021 at 11:19:20PM +0200, Michael Walle wrote:
>> > So this needs a v2, but in general, who do you expect to pick up your
>> > patches?
>>
>> Mh, I haven't found a rule how patches are picked up in u-boot but most of
Am 2021-08-31 20:46, schrieb Vladimir Oltean:
On Tue, Aug 31, 2021 at 05:40:21PM +0200, Michael Walle wrote:
Move all the CCSR related device nodes into /soc similiar to the linux
device tree.
Signed-off-by: Michael Walle
---
.../dts/fsl-ls1028a-kontron-sl28-u-boot.dtsi | 4 +
Am 2021-08-31 20:28, schrieb Vladimir Oltean:
On Tue, Aug 31, 2021 at 05:40:26PM +0200, Michael Walle wrote:
The offical ls1028a binding of the driver uses the following as
compatibles:
compatible = "fsl,ls1028a-lpuart";
s/offical/official/
diff --git a/drivers/serial/serial_lpuart.c
Am 2021-08-31 20:22, schrieb Vladimir Oltean:
On Tue, Aug 31, 2021 at 05:40:19PM +0200, Michael Walle wrote:
This series sync the device tree of the LS1028A SoC with the linux
one.
To ease future debugging and reviewing, we first clean up the existing
one,
removing bogus nodes, moving all CCSR
On Tue, Aug 31, 2021 at 11:53:22PM +0200, Michael Walle wrote:
> Am 2021-08-31 23:39, schrieb Vladimir Oltean:
> > On Tue, Aug 31, 2021 at 11:35:25PM +0200, Michael Walle wrote:
> > > Am 2021-08-31 20:32, schrieb Vladimir Oltean:
> > > > On Tue, Aug 31, 2021 at 05:40:25PM +0200, Michael Walle
On Tue, Aug 31, 2021 at 11:19:20PM +0200, Michael Walle wrote:
> > So this needs a v2, but in general, who do you expect to pick up your
> > patches?
>
> Mh, I haven't found a rule how patches are picked up in u-boot but most of the
> time they go through the qoriq git tree. Why do you ask?
Just
On Fri, Aug 27, 2021 at 09:18:30PM -0400, Tom Rini wrote:
> This converts the following to Kconfig:
>CONFIG_SKIP_LOWLEVEL_INIT
>CONFIG_SKIP_LOWLEVEL_INIT_ONLY
>
> In order to do this, we need to introduce SPL and TPL variants of these
> options so that we can clearly disable these
On Thu, Aug 26, 2021 at 11:47:59AM -0400, Tom Rini wrote:
> We move the SYS_CACHE_SHIFT_N options from arch/arm/Kconfig to
> arch/Kconfig, and introduce SYS_CACHE_SHIFT_4 to provide a size of 16.
> Introduce select statements for other architectures based on current
> usage. For MIPS, we take
On Sat, Aug 28, 2021 at 09:34:49PM -0400, Tom Rini wrote:
> This converts the following to Kconfig:
>CONFIG_SYS_MALLOC_LEN
>
> Signed-off-by: Tom Rini
> Acked-by: Sean Anderson
Applied to u-boot/next, thanks!
--
Tom
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On Tue, Aug 31, 2021 at 11:19:20PM +0200, Michael Walle wrote:
> Am 2021-08-31 20:51, schrieb Vladimir Oltean:
> > On Tue, Aug 31, 2021 at 05:40:19PM +0200, Michael Walle wrote:
> > > This series sync the device tree of the LS1028A SoC with the linux
> > > one.
> > > To ease future debugging and
On Fri, Aug 27, 2021 at 08:48:10AM +0200, Michal Simek wrote:
> default n/no doesn't need to be specified. It is default option anyway.
>
> Signed-off-by: Michal Simek
Applied to u-boot/next, thanks!
--
Tom
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On Wed, Sep 1, 2021 at 10:06 AM Rick Chen wrote:
>
> > From: Zong Li
> > Sent: Tuesday, August 31, 2021 5:21 PM
> > To: Rick Jian-Zhi Chen(陳建志) ; Leo Yu-Chi Liang(梁育齊)
> > ; bmeng...@gmail.com; sean...@gmail.com;
> > green@sifive.com; paul.walms...@sifive.com; s...@chromium.org;
> >
Am 2021-08-31 20:51, schrieb Vladimir Oltean:
On Tue, Aug 31, 2021 at 05:40:19PM +0200, Michael Walle wrote:
This series sync the device tree of the LS1028A SoC with the linux
one.
To ease future debugging and reviewing, we first clean up the existing
one,
removing bogus nodes, moving all CCSR
On Tue, Aug 31, 2021 at 11:32:22PM +0200, Michael Walle wrote:
> > Does the Kontron SL28 use SPL?
>
> Yep :) No BL1/BL2 for TF-A, BL31 is optionally loaded by the
> u-boot SPL. Mainly because NXP doesn't seem to be interested
> in bringing layerscape (besides one architecture) support in
>
On Mon, Aug 23, 2021 at 10:25:30AM -0400, Tom Rini wrote:
> - In most of the codebase, we reference CONFIG_SYS_LOAD_ADDR and not
> CONFIG_LOADADDR.
> - Generally, CONFIG_SYS_LOADADDR is set to CONFIG_LOADADDR and then as
> noted, we use CONFIG_SYS_LOADADDR.
>
> Signed-off-by: Tom Rini
On Mon, Aug 23, 2021 at 10:25:29AM -0400, Tom Rini wrote:
> All platforms define CONFIG_SYS_LOAD_ADDR, but only some define
> CONFIG_LOADADDR. Very very rarely are these not the same address, and
> qemu-ppce500 is one such case. However, based on reading the history of
> the code, this
On Sat, Aug 21, 2021 at 01:50:11PM -0400, Tom Rini wrote:
> While the Kconfig language seems to accept either form of whitespace, we
> use a space throughout the project, except in these spots.
>
> Signed-off-by: Tom Rini
For the series, applied to u-boot/next, thanks!
--
Tom
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On Mon, Aug 23, 2021 at 04:35:25PM -0400, Tom Rini wrote:
> This converts the following to Kconfig:
>CONFIG_MX7D
>
> Cc: Oleksandr Suvorov
> Signed-off-by: Tom Rini
Applied to u-boot/next, thanks!
--
Tom
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On Tue, Aug 31, 2021 at 12:41:17AM +0200, Marek Vasut wrote:
> The following changes since commit 4865db07169126ca0205f1a6265adf01bd69b3df:
>
> Merge tag 'efi-2021-10-rc3' of
> https://source.denx.de/u-boot/custodians/u-boot-efi (2021-08-23 12:44:12
> -0400)
>
> are available in the Git
> From: Zong Li
> Sent: Tuesday, August 31, 2021 5:21 PM
> To: Rick Jian-Zhi Chen(陳建志) ; Leo Yu-Chi Liang(梁育齊)
> ; bmeng...@gmail.com; sean...@gmail.com;
> green@sifive.com; paul.walms...@sifive.com; s...@chromium.org;
> u-boot@lists.denx.de
> Cc: Zong Li
> Subject: [PATCH v4 1/4] cache:
On Tue, Aug 31, 2021 at 11:37:19PM +0200, Michael Walle wrote:
> Yeah, and it seems that parsing of the little-endian flag was introduced
> just for the ls1028a. If that is true, one could remove that, but I wasn't
> sure, so I just left it there.
Leave NXP something to do too ;)
On Tue, Aug 24, 2021 at 08:40:59PM -0400, Tom Rini wrote:
> Currently, there is no over-arching symbol for access to
> arch/arm/mach-imx nor the CONFIG symbols that are common over all of
> these related platforms. This new CONFIG symbol will allow us to start
> down this path.
>
>
On Tue, Aug 24, 2021 at 11:11:50PM -0400, Tom Rini wrote:
> Based on include/configs/ls1046ardb.h it seems that CONFIG_RAMBOOT_PBL
> should have been enabled, but was not. Enable and migrate the values to
> Kconfig.
>
> Cc: Mingkai Hu
> Cc: Rajesh Bhagat
> Signed-off-by: Tom Rini
Applied to
On Mon, Aug 23, 2021 at 10:25:31AM -0400, Tom Rini wrote:
> Now that we have consistent usage, migrate this symbol to Kconfig.
>
> Signed-off-by: Tom Rini
> Reviewed-by: Rick Chen
> Reviewed-by: Rick Chen
Applied to u-boot/next, thanks!
--
Tom
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