Poul-Henning Kamp wrote: > In message <[EMAIL PROTECTED]>, Bruce Griffiths writes: > >> Poul-Henning Kamp wrote: >> >>> In message <[EMAIL PROTECTED]>, Bruce Griffiths writes: >>> >>> You guys could save a lot of time if you read my paper where all >>> this is described in detail: >>> >>> http://phk.freebsd.dk/pubs/timecounter.pdf >>> >> This paper addresses virtually none of the hardware design issues at all. >> > > That was not the main focus. > > The signals were indeed clocked through 3 D flipflops clocked on the > global clock, to handle metastability, before they latched the count > latches. > > I probably still have the VHDL somewhere... > > The point is that actually using latches in this way is considered poor design practice when crossing clock domains.
Bruce _______________________________________________ time-nuts mailing list -- [email protected] To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
