Poul-Henning Kamp wrote: > In message <[EMAIL PROTECTED]>, Bruce Griffiths writes: > >> Poul-Henning Kamp wrote: >> > > > >> The point is that actually using latches in this way is considered poor >> design practice when crossing clock domains. >> > > The latches do NOT span clock domains, they are in the same domain > as the counter. > > The signals that make captures the counter value in the latch is > synchronized to the global clock using 3 D flip-flops. > > You are missing, the point using latches latched by the output of a synchroniser is considered bad design practice you should use gated D flipflops instead.
Bruce _______________________________________________ time-nuts mailing list -- [email protected] To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
