JackOfAll wrote: > Yes, that's documented in the ref manual too, that spdif0_clk_root is > from PLL3 (the USB PLL). PLL3 PFD3 is where the 454.7MHz (mentioned in > that code comment I already posted) is derived from. As far as I can > see, if we do not wish to use spdif0_clk_root, our other TX clock > choices are..... > > 000 XTAL clk input > 001 CCM spdif0_clk_root input > 010 asrc_clk input > 011 spdif_extclk input, from pads > 100 esai_hckt input > 101 frequency divided ipg_clk input > 110 mlb_clk input > 111 mlb phy clk input
Not looked at the source yet, but P842 suggests SPDIF0_CLK_SEL can be set to use pll4 which is the audio clock? ------------------------------------------------------------------------ Triode's Profile: http://forums.slimdevices.com/member.php?userid=17 View this thread: http://forums.slimdevices.com/showthread.php?t=98544 _______________________________________________ unix mailing list [email protected] http://lists.slimdevices.com/mailman/listinfo/unix
