Triode wrote: > Not looked at the source yet, but P842 suggests SPDIF0_CLK_SEL can be > set to use pll4 which is the audio clock? Yes that is correct, set the SPDIF clock root to come from PLL4 the audio PLL, then you can set PLL4 to the frequencies listed in that table to get an audio frequency at the clock root. Then the dividers in the SPDIF block are normal straight forward things like 8 or 64 etc. This DOES mean the PLL parameters have to be changed when changing sample rate families.
BTW when using my carrier board the audio PLL will be set to bypass mode with CLK1 and 2 (differential clock) being used instead of the PLL. In this mode the dividers after the PLL will all be set to 1. The driver will need to change the value (1 or 0) on a GPIO to tell the board what frequency to select. The only reason I can think of that they might be using the USB PLL is that you can sort of get the right clocks without changing the PLL parameters, just the divide parameters. Using the audio PLL as above will require the PLL to resysnc to a different frequency which takes some finite amount of time. (I don't know what that time is though). This should not be a problem in normal use. Most of the time people are not changing sample rate family in a gapless transition between tracks, but usually only between works or albums where a few mili-seconds will not matter. John S. ------------------------------------------------------------------------ JohnSwenson's Profile: http://forums.slimdevices.com/member.php?userid=5974 View this thread: http://forums.slimdevices.com/showthread.php?t=98544 _______________________________________________ unix mailing list [email protected] http://lists.slimdevices.com/mailman/listinfo/unix
