Re: [Mesa-dev] [PATCH] HUD: Add support for block I/O, network I/O and lmsensor stats

[Karol Herbst]

2016-09-13 0:15 GMT+02:00 Steven Toth :
>> I think you expose Temperature, Voltage and Current. But Nouveau exposes
>> Temperature, Voltage, Fan and Power through hwmon.
>>
>> Read the "power" section here for more info:
>> https://www.kernel.org/doc/Documentation/hwmon/sysfs-interface
>
> Ahh, my nouveau card must be too old then. I only get temperature from
> it. I have a 6yo(?) 8800 GTS. That being said - it services the
> console well enough.
>
> nouveau-pci-0100
> Adapter: PCI adapter
> temp1:+57.0°C  (high = +95.0°C, hyst =  +3.0°C)
>(crit = +110.0°C, hyst =  +2.0°C)
>(emerg = +135.0°C, hyst =  +5.0°C)
>
> In fact, I don't seem to have any dev boxes that expose power. That's a odd.
>
> If you want to recommend a specific nvidia card/model that you know
> for certain exposes these features then I'll see what I can do.

Well a 4.6 kernel is required for that and usually high end Fermi
cards or newer have
power sensors.

Some mid end models also might have them.

Well in the end I could also try to extend your patch and give you my
changes on top of yours.

>
> --
> Steven Toth - Kernel Labs
> http://www.kernellabs.com
> +1.646.355.8490
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Re: [Mesa-dev] Problem with RX 480 on Alien: Isolation and Dota 2

[Edward O'Callaghan]

On 09/13/2016 12:26 PM, Romain Failliot wrote:
> Hi!
> 
> I've just bought myself an RX 480 (because of the open source drivers).
> I have Fedora 24 with GNOME 3.20, linux 4.7.2, mesa 12.0.2, llvm 3.8.0.
> 
> I tested Alien: Isolation (that I couldn't even launch with my old HD
> 6870), but there is a texture bug, see by yourself:
> https://youtu.be/zTZpWU9srL4

If I am not mistaken I believe that was a known bug that was resolved in
llvm 3.9. However that has not been version bumped yet in Fedora :<

If you are familiar you could try to compile llvm 3.9 and mesa, install
it into /usr/local and fix up the runtime linker with,

echo "/usr/local/lib" > /etc/ld.conf.d/test.conf && ldconfig

Perhaps someone else can chime in to confirm and/or you can file a bug
with Fedora for a version bump also.

Kind Regards,
Edward.

> 
> Also I tried Dota 2 (which was working on my old HD 6870) and there the
> textures are perfect, but the top bar is always visible and it creates
> an offset in the input (notice that the bottom of the screen is cropped):
> https://framapic.org/6vMPXK5y1tWu/hRcANfUysTdD.png
> 
> Is there something I could do to help you?
> 
> Thanks,
> Romain
> 
> 
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Re: [Mesa-dev] [PATCH 01/20] gallium/radeon: derive buffer placement and flags only at initialization

[Michel Dänzer]

On 13/09/16 07:46 AM, Marek Olšák wrote:
> This might fix it:
> "[PATCH 1/7] gallium/radeon: set new r600_resource fields correctly in
> other places too"

It does, thanks!

Tested-by: Michel Dänzer 


-- 
Earthling Michel Dänzer   |   http://www.amd.com
Libre software enthusiast | Mesa and X developer

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Re: [Mesa-dev] [PATCH v2 1/4] mesa: introduce MS variants of line width min/max/granularity

[Ilia Mirkin]

On Mon, Sep 12, 2016 at 8:55 PM, Kenneth Graunke  wrote:
> On Tuesday, September 6, 2016 11:49:59 PM PDT Ilia Mirkin wrote:
>> These are exposed in ES 3.2. However this moves all st/mesa to clamping
>> on the MS variants. But for now the MS variants are initialized to the
>> AA values.
>>
>> Signed-off-by: Ilia Mirkin 
>
> So...
>
> - Virtually all implementations have the same line widths and granularity
>   regardless of multisampling or antialiasing settings.
>
> - Imagination is a counter example, and has different ranges/granularity
>   for normal (aliased) and smooth/multisampled lines:
>
>   https://cvs.khronos.org/bugzilla/show_bug.cgi?id=13828#c2
>
>   Hence, the need for two separate ranges.  This would be useful for
>   a theoretical Imagination driver, although none exists today.
>
> - I believe that AA = MS in all cases.  But GLES doesn't have the
>   concept of "smooth lines", so they gave the queries a different name.
>
> - The only Mesa driver that sets these differently today is ILO..all
>   other drivers set MaxLineWidth and MaxLineWidthAA identically.  (I have
>   no idea why ILO does this.  We could probably drop the distinction.)

FWIW I have no idea what the "correct" values are for NVIDIA hw. I
wouldn't be surprised if it were semi-common for actual hw to want to
set these differently (i.e. AA vs non-AA).

>
> Maybe it would make sense to drop the distinction and just have one
> field for both kinds of queries.  If we don't want to go that route,
> then I think I'd rather see only two sets of fields:
>
> - MaxPointWidth
> - MaxPointWidthMS (or AA, either name)
> - LineWidthGranularity
> - LineWidthGranularityMS (or AA, either name)
>
> The MS/AA versions should be used if either MSAA is enabled or
> SmoothFlag is enabled.
>
> Does that seem reasonable?

Fine by me. Happy to drop the bit about the additional variables and
always return the same value for both queries.

The reason I added new values was largely the note in the ES 3.2 spec
which mentions about it being distinct from the AA query, and the
ARB_ES3_2_compatbility spec which adds a separate query and updates
the wording regarding MS rasterization to be about the different
limits.

However I'm perfectly happy to leave this distinction out for now and
let hardware which happens to need these to be different have to split
them out.

I probably won't get to it tonight, but maybe tomorrow night.

Cheers,

  -ilia
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[Mesa-dev] Problem with RX 480 on Alien: Isolation and Dota 2

[Romain Failliot]

Hi!

I've just bought myself an RX 480 (because of the open source drivers).
I have Fedora 24 with GNOME 3.20, linux 4.7.2, mesa 12.0.2, llvm 3.8.0.

I tested Alien: Isolation (that I couldn't even launch with my old HD
6870), but there is a texture bug, see by yourself:
https://youtu.be/zTZpWU9srL4

Also I tried Dota 2 (which was working on my old HD 6870) and there the
textures are perfect, but the top bar is always visible and it creates an
offset in the input (notice that the bottom of the screen is cropped):
https://framapic.org/6vMPXK5y1tWu/hRcANfUysTdD.png

Is there something I could do to help you?

Thanks,
Romain
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Re: [Mesa-dev] [PATCH 3/7] mesa/st: support lowering multi-planar YUV

[Roland Scheidegger]

Am 12.09.2016 um 21:36 schrieb Rob Clark:
> On Sat, Sep 10, 2016 at 10:04 AM, Roland Scheidegger  
> wrote:
>> Am 09.09.2016 um 02:58 schrieb Rob Clark:
>>> On Thu, Sep 8, 2016 at 8:28 PM, Roland Scheidegger  
>>> wrote:
 Am 09.09.2016 um 02:19 schrieb Rob Clark:
> On Thu, Sep 8, 2016 at 7:54 PM, Rob Clark  wrote:
>> On Thu, Sep 8, 2016 at 6:41 PM, Roland Scheidegger  
>> wrote:
>>> Am 08.09.2016 um 23:43 schrieb Rob Clark:
 On Thu, Sep 8, 2016 at 5:11 PM, Roland Scheidegger 
  wrote:
> Am 08.09.2016 um 22:30 schrieb Rob Clark:
>> Support multi-planar YUV for external EGLImage's (currently just in 
>> the
>> dma-buf import path) by lowering to multiple texture fetch's for each
>> plane and CSC in shader.
>>
>> Signed-off-by: Rob Clark 
>> ---
>>  src/gallium/auxiliary/util/u_inlines.h  |   4 +-
>>  src/gallium/include/pipe/p_state.h  |   9 +++
>>  src/gallium/include/state_tracker/st_api.h  |   3 +
>>  src/gallium/state_trackers/dri/dri2.c   | 119 
>> +++-
>>  src/gallium/state_trackers/dri/dri_screen.c |  11 +++
>>  src/mesa/main/mtypes.h  |  16 
>>  src/mesa/program/ir_to_mesa.cpp |   1 +
>>  src/mesa/state_tracker/st_atom_sampler.c|  41 +-
>>  src/mesa/state_tracker/st_atom_shader.c |   3 +
>>  src/mesa/state_tracker/st_atom_texture.c|  58 ++
>>  src/mesa/state_tracker/st_cb_eglimage.c |  18 +
>>  src/mesa/state_tracker/st_context.c |   7 +-
>>  src/mesa/state_tracker/st_glsl_to_nir.cpp   |   1 +
>>  src/mesa/state_tracker/st_glsl_to_tgsi.cpp  |   4 +
>>  src/mesa/state_tracker/st_manager.c |   1 +
>>  src/mesa/state_tracker/st_program.c |  35 
>>  src/mesa/state_tracker/st_program.h |  37 +
>>  src/mesa/state_tracker/st_texture.h |  21 +
>>  18 files changed, 362 insertions(+), 27 deletions(-)
>>
>> diff --git a/src/gallium/auxiliary/util/u_inlines.h 
>> b/src/gallium/auxiliary/util/u_inlines.h
>> index c2a0b08..b7b8313 100644
>> --- a/src/gallium/auxiliary/util/u_inlines.h
>> +++ b/src/gallium/auxiliary/util/u_inlines.h
>> @@ -136,8 +136,10 @@ pipe_resource_reference(struct pipe_resource 
>> **ptr, struct pipe_resource *tex)
>> struct pipe_resource *old_tex = *ptr;
>>
>> if (pipe_reference_described(&(*ptr)->reference, >reference,
>> -
>> (debug_reference_descriptor)debug_describe_resource))
>> +
>> (debug_reference_descriptor)debug_describe_resource)) {
>> +  pipe_resource_reference(_tex->next, NULL);
>>old_tex->screen->resource_destroy(old_tex->screen, old_tex);
>> +   }
>> *ptr = tex;
>>  }
>>
>> diff --git a/src/gallium/include/pipe/p_state.h 
>> b/src/gallium/include/pipe/p_state.h
>> index ebd0337..4a88da6 100644
>> --- a/src/gallium/include/pipe/p_state.h
>> +++ b/src/gallium/include/pipe/p_state.h
>> @@ -498,6 +498,15 @@ struct pipe_resource
>>
>> unsigned bind;/**< bitmask of PIPE_BIND_x */
>> unsigned flags;   /**< bitmask of PIPE_RESOURCE_FLAG_x */
>> +
>> +   /**
>> +* For planar images, ie. YUV EGLImage external, etc, pointer to 
>> the
>> +* next plane.
>> +*
>> +* TODO might be useful for dealing w/ z32s8 too, since at least 
>> a
>> +* couple drivers split these out into separate buffers 
>> internally.
>> +*/
>> +   struct pipe_resource *next;
> Would it be possible to stuff the multiple resources somewhere else
> (__DRIImage ?)? Seems a bit of a hack to have resources referencing
> other resources that way.
> (Also, it's odd since things are mostly lowered really outside of
> gallium so it's odd that some of the yuv state still sneaks in there.)

 I did originally start down the path of making __DRIImage have
 multiple pipe_resource's.. I'm not really sure that would end up
 better, and it certainly would be more invasive.

 Maybe we should just make that something like 'void *stpriv' to let st
 stick whatever it wants in there.  That seems more sane than making
 the st use a hashtable to map the rsc back to something else.
>>>
>>> Can't you just put 3 

[Mesa-dev] [PATCH 1/1] radeon: Don't check DCC on pipe buffers

[Jan Vesely]

Fixes segfaults in EG compute since:
commit 21de3be8e62b2b093569a99550e6356ed2f106b4
radeonsi: fix texture format reinterpretation with DCC

Signed-off-by: Jan Vesely 
---
 src/gallium/drivers/radeon/r600_texture.c | 7 ---
 1 file changed, 4 insertions(+), 3 deletions(-)

diff --git a/src/gallium/drivers/radeon/r600_texture.c 
b/src/gallium/drivers/radeon/r600_texture.c
index 41fd94b..d3a498f 100644
--- a/src/gallium/drivers/radeon/r600_texture.c
+++ b/src/gallium/drivers/radeon/r600_texture.c
@@ -1788,9 +1788,10 @@ struct pipe_surface *r600_create_surface_custom(struct 
pipe_context *pipe,
surface->base.u = templ->u;
surface->level_info = >surface.level[templ->u.tex.level];
 
-   vi_dcc_disable_if_incompatible_format(rctx, texture,
- templ->u.tex.level,
- templ->format);
+   if (texture->target != PIPE_BUFFER)
+   vi_dcc_disable_if_incompatible_format(rctx, texture,
+ templ->u.tex.level,
+ templ->format);
 
return >base;
 }
-- 
2.7.4

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[Mesa-dev] [PATCH v2 2/7] intel/isl: Fix up asserts in calc_phys_level0_extent_sa

[Jason Ekstrand]

The assertion that a format is uncompressed in the multisample layouts
isn't quite right.  What we really want to assert is that the format
supports multisampling which is a bit more complicated query.  We also want
to assert that it has a block size of 1x1 since we do nothing with the
block size in the phys_level0_sa assignment.

Signed-off-by: Jason Ekstrand 
Reviewed-by: Topi Pohjolainen 
Reviewed-by: Chad Versace 
---
 src/intel/isl/isl.c | 6 --
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/src/intel/isl/isl.c b/src/intel/isl/isl.c
index c460ddb..a75fddf 100644
--- a/src/intel/isl/isl.c
+++ b/src/intel/isl/isl.c
@@ -558,7 +558,8 @@ isl_calc_phys_level0_extent_sa(const struct isl_device *dev,
   case ISL_MSAA_LAYOUT_ARRAY:
  assert(info->depth == 1);
  assert(info->levels == 1);
- assert(!isl_format_is_compressed(info->format));
+ assert(isl_format_supports_multisampling(dev->info, info->format));
+ assert(fmtl->bw == 1 && fmtl->bh == 1);
 
  *phys_level0_sa = (struct isl_extent4d) {
 .w = info->width,
@@ -571,7 +572,8 @@ isl_calc_phys_level0_extent_sa(const struct isl_device *dev,
   case ISL_MSAA_LAYOUT_INTERLEAVED:
  assert(info->depth == 1);
  assert(info->levels == 1);
- assert(!isl_format_is_compressed(info->format));
+ assert(isl_format_supports_multisampling(dev->info, info->format));
+ assert(fmtl->bw == 1 && fmtl->bh == 1);
 
  *phys_level0_sa = (struct isl_extent4d) {
 .w = info->width,
-- 
2.5.0.400.gff86faf

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[Mesa-dev] [PATCH v2 4/7] intel/isl: Allow multisampling with ISL_FORMAT_HiZ

[Jason Ekstrand]

HiZ buffers can be multisampled and, on BDW+, simply using interleaved
multisampling with a compression block size of 8x4 samples yields the
correct HiZ surface size calculations.  Unfortunately, choose_msaa_layout
was rejecting multisampled HiZ buffers because of format checks.  Now that
we have a simple helper for determining if a format supports multisampling,
that's an easy enough issue to fix.

Signed-off-by: Jason Ekstrand 
Reviewed-by: Chad Versace 
---
 src/intel/isl/isl.c| 4 +++-
 src/intel/isl/isl_format.c | 9 -
 2 files changed, 11 insertions(+), 2 deletions(-)

diff --git a/src/intel/isl/isl.c b/src/intel/isl/isl.c
index 185984d..33d7079 100644
--- a/src/intel/isl/isl.c
+++ b/src/intel/isl/isl.c
@@ -572,7 +572,6 @@ isl_calc_phys_level0_extent_sa(const struct isl_device *dev,
  assert(info->depth == 1);
  assert(info->levels == 1);
  assert(isl_format_supports_multisampling(dev->info, info->format));
- assert(fmtl->bw == 1 && fmtl->bh == 1);
 
  *phys_level0_sa = (struct isl_extent4d) {
 .w = info->width,
@@ -584,6 +583,9 @@ isl_calc_phys_level0_extent_sa(const struct isl_device *dev,
  isl_msaa_interleaved_scale_px_to_sa(info->samples,
  _level0_sa->w,
  _level0_sa->h);
+
+ phys_level0_sa->w = isl_align(phys_level0_sa->w, fmtl->bw);
+ phys_level0_sa->h = isl_align(phys_level0_sa->h, fmtl->bh);
  break;
   }
   break;
diff --git a/src/intel/isl/isl_format.c b/src/intel/isl/isl_format.c
index f3429be..02df1ce 100644
--- a/src/intel/isl/isl_format.c
+++ b/src/intel/isl/isl_format.c
@@ -444,10 +444,17 @@ isl_format_supports_multisampling(const struct 
brw_device_info *devinfo,
 *   - any compressed texture format (BC*)
 *   - any YCRCB* format
 *
-* The restriction on the format's size is removed on Broadwell.
+* The restriction on the format's size is removed on Broadwell.  Also,
+* there is an exception for HiZ which we treat as a compressed format and
+* is allowed to be multisampled on Broadwell and earlier.
 */
if (devinfo->gen < 8 && isl_format_get_layout(format)->bpb > 64) {
   return false;
+   } else if (format == ISL_FORMAT_HIZ) {
+  /* On SKL+, HiZ is always single-sampled even when the primary surface
+   * is multisampled.  See also isl_surf_get_hiz_surf().
+   */
+  return devinfo->gen <= 8;
} else if (isl_format_is_compressed(format)) {
   return false;
} else if (isl_format_is_yuv(format)) {
-- 
2.5.0.400.gff86faf

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[Mesa-dev] [PATCH v2 0/7] intle/isl: Fixes for multisampled hiz

[Jason Ekstrand]

This series is mostly a re-send of the HiZ patches I had before except that
it fixes some asserts that we weren't hitting in Vulkan but were hitting in
GL.  (I'm not 100% sure how we weren't hitting them before, actually.)
Most of the patches are the same except that patch 2 changed a little,
patch 3 is new and patch 4 is a bit bigger to handle some alignment issues.

Jason Ekstrand (7):
  intel/isl: Add a format_supports_multisampling helper
  intel/isl: Fix up asserts in calc_phys_level0_extent_sa
  intel/isl: Add support for 1-D compressed textures
  intel/isl: Allow multisampling with ISL_FORMAT_HiZ
  intel/isl: Handle HiZ and CCS tiling more directly
  intel/isl: Remove tiling checks from choose_msaa_layout
  intel/isl: Add a detailed comment about multisampling with HiZ

 src/intel/isl/isl.c| 91 +-
 src/intel/isl/isl.h|  2 +
 src/intel/isl/isl_format.c | 35 ++
 src/intel/isl/isl_gen6.c   | 19 +-
 src/intel/isl/isl_gen7.c   | 40 
 src/intel/isl/isl_gen8.c   | 15 +---
 6 files changed, 129 insertions(+), 73 deletions(-)

-- 
2.5.0.400.gff86faf

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[Mesa-dev] [PATCH v2 3/7] intel/isl: Add support for 1-D compressed textures

[Jason Ekstrand]

Compressed 1-D textures are a well-defined thing in both GL and Vulkan.
---
 src/intel/isl/isl.c | 5 ++---
 1 file changed, 2 insertions(+), 3 deletions(-)

diff --git a/src/intel/isl/isl.c b/src/intel/isl/isl.c
index a75fddf..185984d 100644
--- a/src/intel/isl/isl.c
+++ b/src/intel/isl/isl.c
@@ -518,7 +518,6 @@ isl_calc_phys_level0_extent_sa(const struct isl_device *dev,
   assert(info->height == 1);
   assert(info->depth == 1);
   assert(info->samples == 1);
-  assert(!isl_format_is_compressed(info->format));
 
   switch (dim_layout) {
   case ISL_DIM_LAYOUT_GEN4_3D:
@@ -527,8 +526,8 @@ isl_calc_phys_level0_extent_sa(const struct isl_device *dev,
   case ISL_DIM_LAYOUT_GEN9_1D:
   case ISL_DIM_LAYOUT_GEN4_2D:
  *phys_level0_sa = (struct isl_extent4d) {
-.w = info->width,
-.h = 1,
+.w = isl_align_npot(info->width, fmtl->bw),
+.h = fmtl->bh,
 .d = 1,
 .a = info->array_len,
  };
-- 
2.5.0.400.gff86faf

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[Mesa-dev] [PATCH v2 5/7] intel/isl: Handle HiZ and CCS tiling more directly

[Jason Ekstrand]

The HiZ and CCS tiling formats are always used for HiZ and CCS surfaces
respectively.  There's no reason why we should go through filter_tiling and
it's much easier to always get HiZ and CCS right if we just handle them
directly.

Signed-off-by: Jason Ekstrand 
Reviewed-by: Topi Pohjolainen 
Reviewed-by: Chad Versace 
---
 src/intel/isl/isl.c  | 18 --
 src/intel/isl/isl_gen7.c | 14 --
 2 files changed, 16 insertions(+), 16 deletions(-)

diff --git a/src/intel/isl/isl.c b/src/intel/isl/isl.c
index 33d7079..ee5330e 100644
--- a/src/intel/isl/isl.c
+++ b/src/intel/isl/isl.c
@@ -226,6 +226,22 @@ isl_surf_choose_tiling(const struct isl_device *dev,
 {
isl_tiling_flags_t tiling_flags = info->tiling_flags;
 
+   /* HiZ surfaces always use the HiZ tiling */
+   if (info->usage & ISL_SURF_USAGE_HIZ_BIT) {
+  assert(info->format == ISL_FORMAT_HIZ);
+  assert(tiling_flags == ISL_TILING_HIZ_BIT);
+  *tiling = ISL_TILING_HIZ;
+  return true;
+   }
+
+   /* CCS surfaces always use the CCS tiling */
+   if (info->usage & ISL_SURF_USAGE_CCS_BIT) {
+  assert(isl_format_get_layout(info->format)->txc == ISL_TXC_CCS);
+  assert(tiling_flags == ISL_TILING_CCS_BIT);
+  *tiling = ISL_TILING_CCS;
+  return true;
+   }
+
if (ISL_DEV_GEN(dev) >= 7) {
   gen7_filter_tiling(dev, info, _flags);
} else {
@@ -254,8 +270,6 @@ isl_surf_choose_tiling(const struct isl_device *dev,
   CHOOSE(ISL_TILING_LINEAR);
}
 
-   CHOOSE(ISL_TILING_CCS);
-   CHOOSE(ISL_TILING_HIZ);
CHOOSE(ISL_TILING_Ys);
CHOOSE(ISL_TILING_Yf);
CHOOSE(ISL_TILING_Y0);
diff --git a/src/intel/isl/isl_gen7.c b/src/intel/isl/isl_gen7.c
index 7b40291..316b51b 100644
--- a/src/intel/isl/isl_gen7.c
+++ b/src/intel/isl/isl_gen7.c
@@ -217,24 +217,10 @@ gen7_filter_tiling(const struct isl_device *dev,
   *flags &= ~ISL_TILING_W_BIT;
}
 
-   /* The HiZ format and tiling always go together */
-   if (info->format == ISL_FORMAT_HIZ) {
-  *flags &= ISL_TILING_HIZ_BIT;
-   } else {
-  *flags &= ~ISL_TILING_HIZ_BIT;
-   }
-
/* MCS buffers are always Y-tiled */
if (isl_format_get_layout(info->format)->txc == ISL_TXC_MCS)
   *flags &= ISL_TILING_Y0_BIT;
 
-   /* The CCS formats and tiling always go together */
-   if (isl_format_get_layout(info->format)->txc == ISL_TXC_CCS) {
-  *flags &= ISL_TILING_CCS_BIT;
-   } else {
-  *flags &= ~ISL_TILING_CCS_BIT;
-   }
-
if (info->usage & (ISL_SURF_USAGE_DISPLAY_ROTATE_90_BIT |
   ISL_SURF_USAGE_DISPLAY_ROTATE_180_BIT |
   ISL_SURF_USAGE_DISPLAY_ROTATE_270_BIT)) {
-- 
2.5.0.400.gff86faf

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[Mesa-dev] [PATCH v2 1/7] intel/isl: Add a format_supports_multisampling helper

[Jason Ekstrand]

Signed-off-by: Jason Ekstrand 
Reviewed-by: Chad Versace 
---
 src/intel/isl/isl.h|  2 ++
 src/intel/isl/isl_format.c | 28 
 src/intel/isl/isl_gen6.c   | 19 +--
 src/intel/isl/isl_gen7.c   | 16 +---
 src/intel/isl/isl_gen8.c   |  4 +---
 5 files changed, 33 insertions(+), 36 deletions(-)

diff --git a/src/intel/isl/isl.h b/src/intel/isl/isl.h
index ecedc05..cb7c22d 100644
--- a/src/intel/isl/isl.h
+++ b/src/intel/isl/isl.h
@@ -989,6 +989,8 @@ bool isl_format_supports_vertex_fetch(const struct 
brw_device_info *devinfo,
   enum isl_format format);
 bool isl_format_supports_lossless_compression(const struct brw_device_info 
*devinfo,
   enum isl_format format);
+bool isl_format_supports_multisampling(const struct brw_device_info *devinfo,
+   enum isl_format format);
 
 bool isl_format_has_unorm_channel(enum isl_format fmt) ATTRIBUTE_CONST;
 bool isl_format_has_snorm_channel(enum isl_format fmt) ATTRIBUTE_CONST;
diff --git a/src/intel/isl/isl_format.c b/src/intel/isl/isl_format.c
index 8507cc5..f3429be 100644
--- a/src/intel/isl/isl_format.c
+++ b/src/intel/isl/isl_format.c
@@ -429,6 +429,34 @@ isl_format_supports_lossless_compression(const struct 
brw_device_info *devinfo,
return format_gen(devinfo) >= format_info[format].lossless_compression;
 }
 
+bool
+isl_format_supports_multisampling(const struct brw_device_info *devinfo,
+  enum isl_format format)
+{
+   /* From the Sandybridge PRM, Volume 4 Part 1 p72, SURFACE_STATE, Surface
+* Format:
+*
+*If Number of Multisamples is set to a value other than
+*MULTISAMPLECOUNT_1, this field cannot be set to the following
+*formats:
+*
+*   - any format with greater than 64 bits per element
+*   - any compressed texture format (BC*)
+*   - any YCRCB* format
+*
+* The restriction on the format's size is removed on Broadwell.
+*/
+   if (devinfo->gen < 8 && isl_format_get_layout(format)->bpb > 64) {
+  return false;
+   } else if (isl_format_is_compressed(format)) {
+  return false;
+   } else if (isl_format_is_yuv(format)) {
+  return false;
+   } else {
+  return true;
+   }
+}
+
 static inline bool
 isl_format_has_channel_type(enum isl_format fmt, enum isl_base_type type)
 {
diff --git a/src/intel/isl/isl_gen6.c b/src/intel/isl/isl_gen6.c
index 2c52e38..b30998d 100644
--- a/src/intel/isl/isl_gen6.c
+++ b/src/intel/isl/isl_gen6.c
@@ -30,8 +30,6 @@ gen6_choose_msaa_layout(const struct isl_device *dev,
   enum isl_tiling tiling,
   enum isl_msaa_layout *msaa_layout)
 {
-   const struct isl_format_layout *fmtl = isl_format_get_layout(info->format);
-
assert(ISL_DEV_GEN(dev) == 6);
assert(info->samples >= 1);
 
@@ -40,22 +38,7 @@ gen6_choose_msaa_layout(const struct isl_device *dev,
   return false;
}
 
-   /* From the Sandybridge PRM, Volume 4 Part 1 p72, SURFACE_STATE, Surface
-* Format:
-*
-*If Number of Multisamples is set to a value other than
-*MULTISAMPLECOUNT_1, this field cannot be set to the following
-*formats:
-*
-*   - any format with greater than 64 bits per element
-*   - any compressed texture format (BC*)
-*   - any YCRCB* format
-*/
-   if (fmtl->bpb > 64)
-  return false;
-   if (isl_format_is_compressed(info->format))
-  return false;
-   if (isl_format_is_yuv(info->format))
+   if (!isl_format_supports_multisampling(dev->info, info->format))
   return false;
 
/* From the Sandybridge PRM, Volume 4 Part 1 p85, SURFACE_STATE, Number of
diff --git a/src/intel/isl/isl_gen7.c b/src/intel/isl/isl_gen7.c
index 02273f8..7b40291 100644
--- a/src/intel/isl/isl_gen7.c
+++ b/src/intel/isl/isl_gen7.c
@@ -30,8 +30,6 @@ gen7_choose_msaa_layout(const struct isl_device *dev,
 enum isl_tiling tiling,
 enum isl_msaa_layout *msaa_layout)
 {
-   const struct isl_format_layout *fmtl = isl_format_get_layout(info->format);
-
bool require_array = false;
bool require_interleaved = false;
 
@@ -43,19 +41,7 @@ gen7_choose_msaa_layout(const struct isl_device *dev,
   return true;
}
 
-   /* From the Ivybridge PRM, Volume 4 Part 1 p63, SURFACE_STATE, Surface
-* Format:
-*
-*If Number of Multisamples is set to a value other than
-*MULTISAMPLECOUNT_1, this field cannot be set to the following
-*formats: any format with greater than 64 bits per element, any
-*compressed texture format (BC*), and any YCRCB* format.
-*/
-   if (fmtl->bpb > 64)
-  return false;
-   if (isl_format_is_compressed(info->format))
-  return false;
-   if (isl_format_is_yuv(info->format))
+   if 

[Mesa-dev] [PATCH v2 6/7] intel/isl: Remove tiling checks from choose_msaa_layout

[Jason Ekstrand]

We already do those checks in filter_tiling.  There's no good reason to
repeat them in choose_msaa_layout.  If anything they should have been
asserts and not "return false" checks.  Also, this check was causing us to
outright reject multisampled HiZ surfaces which wasn't intended.

Signed-off-by: Jason Ekstrand 
Reviewed-by: Chad Versace 
---
 src/intel/isl/isl_gen7.c | 10 +++---
 src/intel/isl/isl_gen8.c | 11 ---
 2 files changed, 7 insertions(+), 14 deletions(-)

diff --git a/src/intel/isl/isl_gen7.c b/src/intel/isl/isl_gen7.c
index 316b51b..5b4f0d4 100644
--- a/src/intel/isl/isl_gen7.c
+++ b/src/intel/isl/isl_gen7.c
@@ -249,9 +249,13 @@ gen7_filter_tiling(const struct isl_device *dev,
*   For multisample render targets, this field must be 1 (true). MSRTs
*   can only be tiled.
*
-   * Multisample surfaces never require X tiling, and Y tiling generally
-   * performs better than X. So choose Y. (Unless it's stencil, then it
-   * must be W).
+   * From the Broadwell PRM >> Volume2d: Command Structures >>
+   * RENDER_SURFACE_STATE Tile Mode:
+   *
+   *   If Number of Multisamples is not MULTISAMPLECOUNT_1, this field
+   *   must be YMAJOR.
+   *
+   * As usual, though, stencil is special and requires W-tiling.
*/
   *flags &= (ISL_TILING_ANY_Y_MASK | ISL_TILING_W_BIT);
}
diff --git a/src/intel/isl/isl_gen8.c b/src/intel/isl/isl_gen8.c
index 0049614..2d7f41f 100644
--- a/src/intel/isl/isl_gen8.c
+++ b/src/intel/isl/isl_gen8.c
@@ -41,17 +41,6 @@ gen8_choose_msaa_layout(const struct isl_device *dev,
}
 
/* From the Broadwell PRM >> Volume2d: Command Structures >>
-* RENDER_SURFACE_STATE Tile Mode:
-*
-*- If Number of Multisamples is not MULTISAMPLECOUNT_1, this field
-*  must be YMAJOR.
-*
-* As usual, though, stencil is special.
-*/
-   if (!isl_tiling_is_any_y(tiling) && !isl_surf_usage_is_stencil(info->usage))
-  return false;
-
-   /* From the Broadwell PRM >> Volume2d: Command Structures >>
 * RENDER_SURFACE_STATE Multisampled Surface Storage Format:
 *
 *All multisampled render target surfaces must have this field set to
-- 
2.5.0.400.gff86faf

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[Mesa-dev] [PATCH v2 7/7] intel/isl: Add a detailed comment about multisampling with HiZ

[Jason Ekstrand]

Signed-off-by: Jason Ekstrand 
Reviewed-by: Chad Versace 
---
 src/intel/isl/isl.c | 60 +++--
 1 file changed, 58 insertions(+), 2 deletions(-)

diff --git a/src/intel/isl/isl.c b/src/intel/isl/isl.c
index ee5330e..749d228 100644
--- a/src/intel/isl/isl.c
+++ b/src/intel/isl/isl.c
@@ -1288,6 +1288,63 @@ isl_surf_get_hiz_surf(const struct isl_device *dev,
assert(surf->msaa_layout == ISL_MSAA_LAYOUT_NONE ||
   surf->msaa_layout == ISL_MSAA_LAYOUT_INTERLEAVED);
 
+   /* From the Broadwell PRM Vol. 7, "Hierarchical Depth Buffer":
+*
+*"The Surface Type, Height, Width, Depth, Minimum Array Element, Render
+*Target View Extent, and Depth Coordinate Offset X/Y of the
+*hierarchical depth buffer are inherited from the depth buffer. The
+*height and width of the hierarchical depth buffer that must be
+*allocated are computed by the following formulas, where HZ is the
+*hierarchical depth buffer and Z is the depth buffer. The Z_Height,
+*Z_Width, and Z_Depth values given in these formulas are those present
+*in 3DSTATE_DEPTH_BUFFER incremented by one.
+*
+*"The value of Z_Height and Z_Width must each be multiplied by 2 before
+*being applied to the table below if Number of Multisamples is set to
+*NUMSAMPLES_4. The value of Z_Height must be multiplied by 2 and
+*Z_Width must be multiplied by 4 before being applied to the table
+*below if Number of Multisamples is set to NUMSAMPLES_8."
+*
+* In the Sky Lake PRM, the second paragraph is replaced with this:
+*
+*"The Z_Height and Z_Width values must equal those present in
+*3DSTATE_DEPTH_BUFFER incremented by one."
+*
+* In other words, on Sandy Bridge through Broadwell, each 128-bit HiZ
+* block corresponds to a region of 8x4 samples in the primary depth
+* surface.  On Sky Lake, on the other hand, each HiZ block corresponds to
+* a region of 8x4 pixels in the primary depth surface regardless of the
+* number of samples.  The dimensions of a HiZ block in both pixels and
+* samples are given in the table below:
+*
+*| SNB - BDW | SKL+
+*  --+---+-
+*1x  |  8 x 4 sa |   8 x 4 sa
+*   MSAA |  8 x 4 px |   8 x 4 px
+*  --+---+-
+*2x  |  8 x 4 sa |  16 x 4 sa
+*   MSAA |  4 x 4 px |   8 x 4 px
+*  --+---+-
+*4x  |  8 x 4 sa |  16 x 8 sa
+*   MSAA |  4 x 2 px |   8 x 4 px
+*  --+---+-
+*8x  |  8 x 4 sa |  32 x 8 sa
+*   MSAA |  2 x 2 px |   8 x 4 px
+*  --+---+-
+*   16x  |N/A| 32 x 16 sa
+*   MSAA |N/A|  8 x  4 px
+*  --+---+-
+*
+* There are a number of different ways that this discrepency could be
+* handled.  The way we have chosen is to simply make MSAA HiZ have the
+* same number of samples as the parent surface pre-Sky Lake and always be
+* single-sampled on Sky Lake and above.  Since the block sizes of
+* compressed formats are given in samples, this neatly handles everything
+* without the need for additional HiZ formats with different block sizes
+* on SKL+.
+*/
+   const unsigned samples = ISL_DEV_GEN(dev) >= 9 ? 1 : surf->samples;
+
isl_surf_init(dev, hiz_surf,
  .dim = ISL_SURF_DIM_2D,
  .format = ISL_FORMAT_HIZ,
@@ -1296,8 +1353,7 @@ isl_surf_get_hiz_surf(const struct isl_device *dev,
  .depth = 1,
  .levels = surf->levels,
  .array_len = surf->logical_level0_px.array_len,
- /* On SKL+, HiZ is always single-sampled */
- .samples = ISL_DEV_GEN(dev) >= 9 ? 1 : surf->samples,
+ .samples = samples,
  .usage = ISL_SURF_USAGE_HIZ_BIT,
  .tiling_flags = ISL_TILING_HIZ_BIT);
 }
-- 
2.5.0.400.gff86faf

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Re: [Mesa-dev] [PATCH v2 1/4] mesa: introduce MS variants of line width min/max/granularity

[Kenneth Graunke]

On Tuesday, September 6, 2016 11:49:59 PM PDT Ilia Mirkin wrote:
> These are exposed in ES 3.2. However this moves all st/mesa to clamping
> on the MS variants. But for now the MS variants are initialized to the
> AA values.
> 
> Signed-off-by: Ilia Mirkin 

So...

- Virtually all implementations have the same line widths and granularity
  regardless of multisampling or antialiasing settings.

- Imagination is a counter example, and has different ranges/granularity
  for normal (aliased) and smooth/multisampled lines:

  https://cvs.khronos.org/bugzilla/show_bug.cgi?id=13828#c2

  Hence, the need for two separate ranges.  This would be useful for
  a theoretical Imagination driver, although none exists today.

- I believe that AA = MS in all cases.  But GLES doesn't have the
  concept of "smooth lines", so they gave the queries a different name.

- The only Mesa driver that sets these differently today is ILO..all
  other drivers set MaxLineWidth and MaxLineWidthAA identically.  (I have
  no idea why ILO does this.  We could probably drop the distinction.)

Maybe it would make sense to drop the distinction and just have one
field for both kinds of queries.  If we don't want to go that route,
then I think I'd rather see only two sets of fields:

- MaxPointWidth
- MaxPointWidthMS (or AA, either name)
- LineWidthGranularity
- LineWidthGranularityMS (or AA, either name)

The MS/AA versions should be used if either MSAA is enabled or
SmoothFlag is enabled.

Does that seem reasonable?

--Ken


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Re: [Mesa-dev] Check about recent changes in amdgpu

[Dave Airlie]

On 13 September 2016 at 09:41, Mauro Rossi  wrote:
>
>
> 2016-09-12 3:22 GMT+02:00 Dave Airlie :
>>
>> Does android have an endian.h? does the attached patch work?
>
>
> Yes, bionic libc has endian.h and the patch you provided works
> Thanks a lot
>
> I'm sending in the attachment the cumulative patch to fix android building
> errors due to following commits:
>
> f1f1ba3 "radeonsi: move sid.h/r600d_common.h to a common place."
> 69fca64 "amd/addrlib: move addrlib from amdgpu winsys to common code"
>
> Tested by building nougat-x86 branch and applicable to mesa-dev git, after
> your/Emil review

Looks good to me, I've pushed both patches.

Dave.
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Re: [Mesa-dev] [PATCH 3/3] Revert "i965: Drop the maximum 3D texture size to 512 on Sandy Bridge"

[Chad Versace]

On Mon 12 Sep 2016, Kenneth Graunke wrote:
> On Monday, September 12, 2016 3:16:31 PM PDT Jason Ekstrand wrote:
> > This reverts commit 6ba88bce64b343761aabe3a6c7ee285c6020a959.  The commit
> > was erroneous because GL already provides a separate guard on the number of
> > layers you are allowed to render into.  On Sandy Bridge, we set this guard
> > correctly so creating a 3D texture bigger than 512 is fine, you just can't
> > render into all of the slices at once.
> > 
> > Signed-off-by: Jason Ekstrand 
> > ---
> >  src/mesa/drivers/dri/i965/brw_context.c | 11 +--
> >  1 file changed, 1 insertion(+), 10 deletions(-)
> > 
> > diff --git a/src/mesa/drivers/dri/i965/brw_context.c 
> > b/src/mesa/drivers/dri/i965/brw_context.c
> > index c28401a..3af4555 100644
> > --- a/src/mesa/drivers/dri/i965/brw_context.c
> > +++ b/src/mesa/drivers/dri/i965/brw_context.c
> > @@ -524,16 +524,7 @@ brw_initialize_context_constants(struct brw_context 
> > *brw)
> > ctx->Const.MaxImageUnits = MAX_IMAGE_UNITS;
> > ctx->Const.MaxRenderbufferSize = 8192;
> > ctx->Const.MaxTextureLevels = MIN2(14 /* 8192 */, MAX_TEXTURE_LEVELS);
> > -
> > -   /* On Sandy Bridge and prior, the "Render Target View Extent" field of
> > -* RENDER_SURFACE_STATE is only 9 bits so the largest 3-D texture we 
> > can do
> > -* a layered render into has a depth of 512.  On Iron Lake and earlier, 
> > we
> > -* don't support layered rendering and we use manual offsetting to 
> > render
> > -* into the different layers so this doesn't matter.  On Sandy Bridge,
> > -* however, we do support layered rendering so this is a problem.
> > -*/
> > -   ctx->Const.Max3DTextureLevels = brw->gen == 6 ? 10 /* 512 */ : 12; /* 
> > 2048 */
> > -
> > +   ctx->Const.Max3DTextureLevels = 12; /* 2048 */
> > ctx->Const.MaxCubeTextureLevels = 14; /* 8192 */
> > ctx->Const.MaxArrayTextureLayers = brw->gen >= 7 ? 2048 : 512;
> > ctx->Const.MaxTextureMbytes = 1536;
> > 
> 
> To clarify...that limit is GL_MAX_FRAMEBUFFER_LAYERS.

Good. If the limit is GL_MAX_FRAMEBUFFER_LAYERS, then I agree with this
patch.

Reviewed-by: Chad Versace 
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Re: [Mesa-dev] [PATCH 3/3] Revert "i965: Drop the maximum 3D texture size to 512 on Sandy Bridge"

[Kenneth Graunke]

On Monday, September 12, 2016 3:16:31 PM PDT Jason Ekstrand wrote:
> This reverts commit 6ba88bce64b343761aabe3a6c7ee285c6020a959.  The commit
> was erroneous because GL already provides a separate guard on the number of
> layers you are allowed to render into.  On Sandy Bridge, we set this guard
> correctly so creating a 3D texture bigger than 512 is fine, you just can't
> render into all of the slices at once.
> 
> Signed-off-by: Jason Ekstrand 
> ---
>  src/mesa/drivers/dri/i965/brw_context.c | 11 +--
>  1 file changed, 1 insertion(+), 10 deletions(-)
> 
> diff --git a/src/mesa/drivers/dri/i965/brw_context.c 
> b/src/mesa/drivers/dri/i965/brw_context.c
> index c28401a..3af4555 100644
> --- a/src/mesa/drivers/dri/i965/brw_context.c
> +++ b/src/mesa/drivers/dri/i965/brw_context.c
> @@ -524,16 +524,7 @@ brw_initialize_context_constants(struct brw_context *brw)
> ctx->Const.MaxImageUnits = MAX_IMAGE_UNITS;
> ctx->Const.MaxRenderbufferSize = 8192;
> ctx->Const.MaxTextureLevels = MIN2(14 /* 8192 */, MAX_TEXTURE_LEVELS);
> -
> -   /* On Sandy Bridge and prior, the "Render Target View Extent" field of
> -* RENDER_SURFACE_STATE is only 9 bits so the largest 3-D texture we can 
> do
> -* a layered render into has a depth of 512.  On Iron Lake and earlier, we
> -* don't support layered rendering and we use manual offsetting to render
> -* into the different layers so this doesn't matter.  On Sandy Bridge,
> -* however, we do support layered rendering so this is a problem.
> -*/
> -   ctx->Const.Max3DTextureLevels = brw->gen == 6 ? 10 /* 512 */ : 12; /* 
> 2048 */
> -
> +   ctx->Const.Max3DTextureLevels = 12; /* 2048 */
> ctx->Const.MaxCubeTextureLevels = 14; /* 8192 */
> ctx->Const.MaxArrayTextureLayers = brw->gen >= 7 ? 2048 : 512;
> ctx->Const.MaxTextureMbytes = 1536;
> 

To clarify...that limit is GL_MAX_FRAMEBUFFER_LAYERS.

The GL 4.5 spec says:

"The framebuffer attachment point attachment is said to be framebuffer
 attachment complete if [...] all of the following conditions are true:

 [...]

 If image is a three-dimensional, one- or two-dimensional array, or cube map
 array texture and the attachment is layered, the depth or layer count of the
 texture is less than or equal to the value of the implementation-dependent
 limit MAX_FRAMEBUFFER_LAYERS."

and goes on to say that "framebuffer complete" requires all attachments
to be "framebuffer attachment complete".


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Re: [Mesa-dev] Check about recent changes in amdgpu

[Mauro Rossi]

2016-09-12 3:22 GMT+02:00 Dave Airlie :

> Does android have an endian.h? does the attached patch work?
>

Yes, bionic libc has endian.h and the patch you provided works
Thanks a lot

I'm sending in the attachment the cumulative patch to fix android building
errors due to following commits:

f1f1ba3 "radeonsi: move sid.h/r600d_common.h to a common place."
69fca64 "amd/addrlib: move addrlib from amdgpu winsys to common code"

Tested by building nougat-x86 branch and applicable to mesa-dev git, after
your/Emil review
KR

Mauro
From 63fc17feef58effe19b95785f85dbccfa9b18a3f Mon Sep 17 00:00:00 2001
From: Mauro Rossi 
Date: Tue, 13 Sep 2016 01:15:16 +0200
Subject: [PATCH] android: add support for libmesa_amdgpu_addrlib

Android porting of the following commits:

f1f1ba3 "radeonsi: move sid.h/r600d_common.h to a common place."
69fca64 "amd/addrlib: move addrlib from amdgpu winsys to common code"

This patch fixes android building errors
---
 Android.mk   |  1 +
 src/amd/Android.addrlib.mk   | 44 
 src/amd/Android.mk   | 28 
 src/gallium/drivers/r600/Android.mk  |  2 ++
 src/gallium/drivers/radeonsi/Android.mk  |  4 ++-
 src/gallium/targets/dri/Android.mk   |  2 +-
 src/gallium/winsys/amdgpu/drm/Android.mk |  9 ---
 7 files changed, 84 insertions(+), 6 deletions(-)
 create mode 100644 src/amd/Android.addrlib.mk
 create mode 100644 src/amd/Android.mk

diff --git a/Android.mk b/Android.mk
index 5ab0ef9..e97307d 100644
--- a/Android.mk
+++ b/Android.mk
@@ -90,6 +90,7 @@ SUBDIRS := \
 	src/mesa \
 	src/util \
 	src/egl \
+	src/amd \
 	src/intel \
 	src/mesa/drivers/dri
 
diff --git a/src/amd/Android.addrlib.mk b/src/amd/Android.addrlib.mk
new file mode 100644
index 000..d296ce0
--- /dev/null
+++ b/src/amd/Android.addrlib.mk
@@ -0,0 +1,44 @@
+# Copyright © 2016 Red Hat.
+# Copyright © 2016 Mauro Rossi 
+#
+# Permission is hereby granted, free of charge, to any person obtaining a
+# copy of this software and associated documentation files (the "Software"),
+# to deal in the Software without restriction, including without limitation
+# the rights to use, copy, modify, merge, publish, distribute, sublicense,
+# and/or sell copies of the Software, and to permit persons to whom the
+# Software is furnished to do so, subject to the following conditions:
+#
+# The above copyright notice and this permission notice (including the next
+# paragraph) shall be included in all copies or substantial portions of the
+# Software.
+#
+# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+# THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+# FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+# IN THE SOFTWARE.
+
+# ---
+# Build libmesa_amdgpu_addrlib
+# ---
+
+include $(CLEAR_VARS)
+
+LOCAL_MODULE := libmesa_amdgpu_addrlib
+
+LOCAL_SRC_FILES := $(ADDRLIB_FILES)
+
+LOCAL_CFLAGS := -DBRAHMA_BUILD=1
+
+LOCAL_C_INCLUDES := \
+	$(MESA_TOP)/src \
+	$(MESA_TOP)/src/amd/common \
+	$(MESA_TOP)/src/amd/addrlib \
+	$(MESA_TOP)/src/amd/addrlib/core \
+	$(MESA_TOP)/src/amd/addrlib/inc/chip/r800 \
+	$(MESA_TOP)/src/amd/addrlib/r800/chip
+
+include $(MESA_COMMON_MK)
+include $(BUILD_STATIC_LIBRARY)
diff --git a/src/amd/Android.mk b/src/amd/Android.mk
new file mode 100644
index 000..7b745fe
--- /dev/null
+++ b/src/amd/Android.mk
@@ -0,0 +1,28 @@
+# Copyright © 2016 Red Hat.
+# Copyright © 2016 Mauro Rossi 
+#
+# Permission is hereby granted, free of charge, to any person obtaining a
+# copy of this software and associated documentation files (the "Software"),
+# to deal in the Software without restriction, including without limitation
+# the rights to use, copy, modify, merge, publish, distribute, sublicense,
+# and/or sell copies of the Software, and to permit persons to whom the
+# Software is furnished to do so, subject to the following conditions:
+#
+# The above copyright notice and this permission notice (including the next
+# paragraph) shall be included in all copies or substantial portions of the
+# Software.
+#
+# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+# THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+# FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 

Re: [Mesa-dev] [PATCH 3/3] Revert "i965: Drop the maximum 3D texture size to 512 on Sandy Bridge"

[Chad Versace]

On Mon 12 Sep 2016, Jason Ekstrand wrote:
> This reverts commit 6ba88bce64b343761aabe3a6c7ee285c6020a959.  The commit
> was erroneous because GL already provides a separate guard on the number of
> layers you are allowed to render into.  On Sandy Bridge, we set this guard
> correctly so creating a 3D texture bigger than 512 is fine, you just can't
> render into all of the slices at once.
> 
> Signed-off-by: Jason Ekstrand 
> ---
>  src/mesa/drivers/dri/i965/brw_context.c | 11 +--
>  1 file changed, 1 insertion(+), 10 deletions(-)

What is that separate guard? Is it GL_MAX_FRAMEBUFFER_LAYERS (which we
set to the same value as GL_MaxArrayTextureLayers)?
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Re: [Mesa-dev] [PATCH 0/5] *** Aubinator code simplification ***

[Kenneth Graunke]

On Thursday, September 8, 2016 6:56:59 PM PDT Kenneth Graunke wrote:
> On Thursday, September 8, 2016 4:15:17 PM PDT Sirisha Gandikota wrote:
> > From: Sirisha Gandikota 
> > 
> > This patch set simplifies parts of code in the aubinator tool
> > as per review comments from Ken (Wed Aug 24 04:51:47 UTC 2016)
> > 
> > Sirisha Gandikota (5):
> >   aubinator: Fix compiler warning
> >   aubinator: Simplify gen_disasm_create()'s devinfo handling
> >   aubinator: Simplify print_dword_val() method
> >   aubinator: Make gen_disasm_disassemble handle split sends
> >   aubinator: Remove bogus "end" parameter in gen_disasm_disassemble()
> > 
> >  src/intel/tools/aubinator.c  | 20 
> >  src/intel/tools/decoder.h|  2 +-
> >  src/intel/tools/disasm.c | 38 ++
> >  src/intel/tools/gen_disasm.h |  2 +-
> >  4 files changed, 32 insertions(+), 30 deletions(-)
> > 
> > 
> 
> Patches 1, 2, and 5 are:
> Reviewed-by: Kenneth Graunke 

I pushed patches 1-2.  I'll plan to push 3-5 once I receive a v2.

--Ken


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Re: [Mesa-dev] [PATCH 00/33] anv: Use blorp for most blits and clears

[Nanley Chery]

On Tue, Sep 06, 2016 at 10:20:02AM -0700, Nanley Chery wrote:
> On Mon, Sep 05, 2016 at 09:38:59AM -0700, Jason Ekstrand wrote:
> > Everything is now reviewed.  I've also sent two additional patches blorp
> > which, when placed prior to the anv patches, make the series
> > regression-free and they've been reviewed by Topi.
> > 
> > Nanley, if you don't mind, I would still like your review on the "use blorp
> > to implement vkFoo" patches.  They're a complete replacement of the old
> > blit2d or direct meta entrypoints and it's entirely possible that I've
> > missed things.  You know the dirty little details of those APIs better than
> > about anyone else (including myself) so I'll feel much more comfortable if
> > you've looked over it.
> > 
> 
> Sure, I'll take a look at them today.

I've looked over all the patches that touch the API entry points I'm
most familiar with (all the users of blorp_copy()), so feel free to
push.

- Nanley

> 
> - Nanley
> 
> > --Jason
> > 
> > On Wed, Aug 31, 2016 at 2:22 PM, Jason Ekstrand 
> > wrote:
> > 
> > > This little (hah!) series does a bit more blorp reworking and then 
> > > converts
> > > most of the Vulkan driver to using blorp for its blit and copy operations.
> > >
> > > As it currently stands, it adds a few cts "regresssions" which are really
> > > because the CTS makes assumptions about rounding in scaled blit operations
> > > that aren't quite valid.
> > >
> > > This series also doesn't 100% remove vulkan meta.  As it stands, blorp
> > > can't do depth/stencil clears so those are left in meta.  Support could be
> > > added to blorp (and we could use it from GL) but that's a bit more work 
> > > and
> > > I wanted to get this sent out earlier rather than later.
> > >
> > > For review, I would recommend that Topi review the first 19 or so and
> > > Nanley review patch 26+.  For 20-25, I'm not sure.  Kristian may be the
> > > best one to review since he understands it all but Jordan or Nanley could
> > > take a crack at it too.
> > >
> > > Cc: Topi Pohjolainen 
> > > Cc: Jordan Justen 
> > > Cc: Nanley Chery 
> > > Cc: Chad Versace 
> > > Cc: Kristian Høgsberg 
> > >
> > > Jason Ekstrand (33):
> > >   intel/isl: Add an isl_swizzle structure and use it for isl_view
> > > swizzles
> > >   intel/blorp: Take an isl_swizzle instead of a SWIZZLE
> > >   intel/blorp: Take a destination swizzle in blorp_blit
> > >   intel/blorp: Don't assume R8_UINT in convert_to_single_slice
> > >   intel/blorp: Use the surface format for computing offsets
> > >   intel/blorp: Fix the early return condition in convert_to_single_slice
> > >   intel/isl: Fix an assert in get_intratile_offset_sa
> > >   intel/blorp: Handle 3D surfaces in convert_to_single_slice
> > >   intel/isl: Add a helper for getting the size of an interleaved pixel
> > >   intel/blorp: Use isl_get_interleaved_msaa_px_size_sa
> > >   intel/blorp: Use fake_interleaved_msaa in retile_w_to_y
> > >   intel/blorp: Stop using the X/YOffset field of RENDER_SURFACE_STATE
> > >   intel/blorp: Pull the guts of blorp_blit into a helper
> > >   intel/blorp: Add an entrypoint for doing bit-for-bit copies
> > >   intel/blorp: Add support for RGB destinations in copies
> > >   intel/blorp: Add support for clearing R9G9B9E5 surfaces
> > >   intel/blorp: Make color_write_disable const and optional
> > >   intel/blorp: Add a swizzle parameter to blorp_clear
> > >   intel/blorp: Rework alloc_binding_table
> > >   intel/blorp: Use #defines for all __gen_ helpers
> > >   anv/pipeline: Roll compute_urb_partition into emit_urb_setup
> > >   anv: Generalize emit_urb_setup
> > >   intel/anv: Use #defines for all __gen_ helpers
> > >   anv: Add initial blorp support
> > >   anv: Make image_get_surface_for_aspect_mask const
> > >   anv: Use blorp to implement VkBlitImage
> > >   anv: Use blorp for CopyImageToBuffer
> > >   anv: Use blorp for CopyBufferToImage
> > >   anv: Use blorp for CopyImage
> > >   anv: Use blorp for CopyBuffer and UpdateBuffer
> > >   anv: Delete meta_blit2d
> > >   anv: Use blorp for ClearColorImage
> > >   anv: Use blorp for doing MSAA resolves
> > >
> > >  src/intel/blorp/blorp.c  |7 +-
> > >  src/intel/blorp/blorp.h  |   19 +-
> > >  src/intel/blorp/blorp_blit.c |  570 +---
> > >  src/intel/blorp/blorp_clear.c|   24 +-
> > >  src/intel/blorp/blorp_genX_exec.h|   25 +-
> > >  src/intel/blorp/blorp_priv.h |   26 +-
> > >  src/intel/isl/isl.c  |   22 +-
> > >  src/intel/isl/isl.h  |   23 +-
> > >  src/intel/isl/isl_surface_state.c|8 +-
> > >  src/intel/vulkan/Makefile.am |1 +
> > >  src/intel/vulkan/Makefile.sources|9 +-
> > >  

Re: [Mesa-dev] [PATCH 2/3] blorp: Handle the 512 layers restriction on Sandy Bridge

[Chad Versace]

On Mon 12 Sep 2016, Jason Ekstrand wrote:
> ---
>  src/intel/blorp/blorp.c   |  6 ++
>  src/intel/blorp/blorp_clear.c | 17 +
>  2 files changed, 19 insertions(+), 4 deletions(-)


> @@ -246,7 +246,6 @@ blorp_clear(struct blorp_batch *batch,

Why didn't you also update blorp_fast_clear()? Oh right, Sandybridge
can't do fast clears.

Reviewed-by: Chad Versace 
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Re: [Mesa-dev] [PATCH 1/3] intel/isl: Treat 3-D textures as 2-D arrays for rendering

[Chad Versace]

On Mon 12 Sep 2016, Jason Ekstrand wrote:
> In particular, this means that isl_view::base_array_layer and
> isl_view::array_len get applied to 3-D textures but only when rendering.
> We were already applying isl_view::base_array_layer for rendering into 3-D
> textures so this isn't a huge deviation.
> 
> Signed-off-by: Jason Ekstrand 
> Cc: Chad Versace 
> ---
>  src/intel/isl/isl.h   |  6 ++
>  src/intel/isl/isl_surface_state.c | 11 +++
>  2 files changed, 13 insertions(+), 4 deletions(-)

Reviewed-by: Chad Versace 

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[Mesa-dev] [PATCH 2/3] intel/blorp: Emit 3DSTATE_MULTISAMPLE directly

[Jason Ekstrand]

Previously, we relied on a driver hook for 3DSTATE_MULTISAMPLE.  However,
now that Vulkan and GL use the same sample positions, we can set up
3DSTATE_MULTISAMPLE directly in blorp and delete the driver hook.

Signed-off-by: Jason Ekstrand 
---
 src/intel/blorp/blorp_genX_exec.h   | 48 +++--
 src/intel/vulkan/genX_blorp_exec.c  | 37 --
 src/mesa/drivers/dri/i965/genX_blorp_exec.c | 13 
 3 files changed, 45 insertions(+), 53 deletions(-)

diff --git a/src/intel/blorp/blorp_genX_exec.h 
b/src/intel/blorp/blorp_genX_exec.h
index 5972cc4..aff59e1 100644
--- a/src/intel/blorp/blorp_genX_exec.h
+++ b/src/intel/blorp/blorp_genX_exec.h
@@ -23,6 +23,7 @@
 
 #include "blorp_priv.h"
 #include "common/gen_device_info.h"
+#include "common/gen_sample_positions.h"
 #include "intel_aub.h"
 
 /**
@@ -68,8 +69,6 @@ blorp_surface_reloc(struct blorp_batch *batch, uint32_t 
ss_offset,
 
 static void
 blorp_emit_urb_config(struct blorp_batch *batch, unsigned vs_entry_size);
-static void
-blorp_emit_3dstate_multisample(struct blorp_batch *batch, unsigned samples);
 
 /* BEGIN blorp_exec implementation **/
 
@@ -1021,6 +1020,49 @@ blorp_emit_sampler_state(struct blorp_batch *batch,
 #endif
 }
 
+static void
+blorp_emit_3dstate_multisample(struct blorp_batch *batch,
+   const struct blorp_params *params)
+{
+   const unsigned samples = params->dst.surf.samples;
+
+   blorp_emit(batch, GENX(3DSTATE_MULTISAMPLE), ms) {
+  ms.NumberofMultisamples   = __builtin_ffs(samples) - 1;
+
+#if GEN_GEN >= 8
+  /* The PRM says that this bit is valid only for DX9:
+   *
+   *SW can choose to set this bit only for DX9 API. DX10/OGL API's
+   *should not have any effect by setting or not setting this bit.
+   */
+  ms.PixelPositionOffsetEnable  = false;
+  ms.PixelLocation  = CENTER;
+#elif GEN_GEN >= 7
+  ms.PixelLocation  = PIXLOC_CENTER;
+
+  switch (samples) {
+  case 1:
+ GEN_SAMPLE_POS_1X(ms.Sample);
+ break;
+  case 2:
+ GEN_SAMPLE_POS_2X(ms.Sample);
+ break;
+  case 4:
+ GEN_SAMPLE_POS_4X(ms.Sample);
+ break;
+  case 8:
+ GEN_SAMPLE_POS_8X(ms.Sample);
+ break;
+  default:
+ break;
+  }
+#else
+  ms.PixelLocation  = PIXLOC_CENTER;
+  GEN_SAMPLE_POS_4X(ms.Sample);
+#endif
+   }
+}
+
 /* 3DSTATE_VIEWPORT_STATE_POINTERS */
 static void
 blorp_emit_viewport_state(struct blorp_batch *batch,
@@ -1118,7 +1160,7 @@ blorp_exec(struct blorp_batch *batch, const struct 
blorp_params *params)
if (params->src.addr.buffer)
   blorp_emit_sampler_state(batch, params);
 
-   blorp_emit_3dstate_multisample(batch, params->dst.surf.samples);
+   blorp_emit_3dstate_multisample(batch, params);
 
blorp_emit(batch, GENX(3DSTATE_SAMPLE_MASK), mask) {
   mask.SampleMask = (1 << params->dst.surf.samples) - 1;
diff --git a/src/intel/vulkan/genX_blorp_exec.c 
b/src/intel/vulkan/genX_blorp_exec.c
index 5a08ed3..a3ad97a 100644
--- a/src/intel/vulkan/genX_blorp_exec.c
+++ b/src/intel/vulkan/genX_blorp_exec.c
@@ -145,43 +145,6 @@ blorp_emit_urb_config(struct blorp_batch *batch, unsigned 
vs_entry_size)
 cmd_buffer->state.current_l3_config);
 }
 
-static void
-blorp_emit_3dstate_multisample(struct blorp_batch *batch, unsigned samples)
-{
-   blorp_emit(batch, GENX(3DSTATE_MULTISAMPLE), ms) {
-  ms.NumberofMultisamples   = __builtin_ffs(samples) - 1;
-
-#if GEN_GEN >= 8
-  /* The PRM says that this bit is valid only for DX9:
-   *
-   *SW can choose to set this bit only for DX9 API. DX10/OGL API's
-   *should not have any effect by setting or not setting this bit.
-   */
-  ms.PixelPositionOffsetEnable  = false;
-  ms.PixelLocation  = CENTER;
-#else
-  ms.PixelLocation  = PIXLOC_CENTER;
-
-  switch (samples) {
-  case 1:
- GEN_SAMPLE_POS_1X(ms.Sample);
- break;
-  case 2:
- GEN_SAMPLE_POS_2X(ms.Sample);
- break;
-  case 4:
- GEN_SAMPLE_POS_4X(ms.Sample);
- break;
-  case 8:
- GEN_SAMPLE_POS_8X(ms.Sample);
- break;
-  default:
- break;
-  }
-#endif
-   }
-}
-
 void genX(blorp_exec)(struct blorp_batch *batch,
   const struct blorp_params *params);
 
diff --git a/src/mesa/drivers/dri/i965/genX_blorp_exec.c 
b/src/mesa/drivers/dri/i965/genX_blorp_exec.c
index 47d509d..8cd5a62 100644
--- a/src/mesa/drivers/dri/i965/genX_blorp_exec.c
+++ b/src/mesa/drivers/dri/i965/genX_blorp_exec.c
@@ -162,19 +162,6 @@ blorp_emit_urb_config(struct blorp_batch *batch, unsigned 
vs_entry_size)
 #endif
 }
 
-static void
-blorp_emit_3dstate_multisample(struct blorp_batch *batch, unsigned samples)
-{
-   assert(batch->blorp->driver_ctx == batch->driver_batch);
-  

[Mesa-dev] [PATCH 1/3] intel: Move Vulkan sample positions to common code

[Jason Ekstrand]

Signed-off-by: Jason Ekstrand 
---
 .../genX_multisample.h => common/gen_sample_positions.h} | 10 +-
 src/intel/vulkan/genX_blorp_exec.c   | 10 +-
 src/intel/vulkan/genX_pipeline_util.h| 10 +-
 src/intel/vulkan/genX_state.c| 12 ++--
 4 files changed, 21 insertions(+), 21 deletions(-)
 rename src/intel/{vulkan/genX_multisample.h => common/gen_sample_positions.h} 
(94%)

diff --git a/src/intel/vulkan/genX_multisample.h 
b/src/intel/common/gen_sample_positions.h
similarity index 94%
rename from src/intel/vulkan/genX_multisample.h
rename to src/intel/common/gen_sample_positions.h
index 0deb48f..0411bf0 100644
--- a/src/intel/vulkan/genX_multisample.h
+++ b/src/intel/common/gen_sample_positions.h
@@ -22,17 +22,17 @@
  */
 #pragma once
 
-#define SAMPLE_POS_1X(prefix) \
+#define GEN_SAMPLE_POS_1X(prefix) \
 prefix##0XOffset   = 0.5; \
 prefix##0YOffset   = 0.5;
 
-#define SAMPLE_POS_2X(prefix) \
+#define GEN_SAMPLE_POS_2X(prefix) \
 prefix##0XOffset   = 0.25; \
 prefix##0YOffset   = 0.25; \
 prefix##1XOffset   = 0.75; \
 prefix##1YOffset   = 0.75;
 
-#define SAMPLE_POS_4X(prefix) \
+#define GEN_SAMPLE_POS_4X(prefix) \
 prefix##0XOffset   = 0.375; \
 prefix##0YOffset   = 0.125; \
 prefix##1XOffset   = 0.875; \
@@ -42,7 +42,7 @@ prefix##2YOffset   = 0.625; \
 prefix##3XOffset   = 0.625; \
 prefix##3YOffset   = 0.875;
 
-#define SAMPLE_POS_8X(prefix) \
+#define GEN_SAMPLE_POS_8X(prefix) \
 prefix##0XOffset   = 0.5625; \
 prefix##0YOffset   = 0.3125; \
 prefix##1XOffset   = 0.4375; \
@@ -60,7 +60,7 @@ prefix##6YOffset   = 0.9375; \
 prefix##7XOffset   = 0.9375; \
 prefix##7YOffset   = 0.0625;
 
-#define SAMPLE_POS_16X(prefix) \
+#define GEN_SAMPLE_POS_16X(prefix) \
 prefix##0XOffset   = 0.5625; \
 prefix##0YOffset   = 0.5625; \
 prefix##1XOffset   = 0.4375; \
diff --git a/src/intel/vulkan/genX_blorp_exec.c 
b/src/intel/vulkan/genX_blorp_exec.c
index 889c423..5a08ed3 100644
--- a/src/intel/vulkan/genX_blorp_exec.c
+++ b/src/intel/vulkan/genX_blorp_exec.c
@@ -24,7 +24,6 @@
 #include 
 
 #include "anv_private.h"
-#include "genX_multisample.h"
 
 /* These are defined in anv_private.h and blorp_genX_exec.h */
 #undef __gen_address_type
@@ -32,6 +31,7 @@
 #undef __gen_combine_address
 
 #include "common/gen_l3_config.h"
+#include "common/gen_sample_positions.h"
 #include "blorp/blorp_genX_exec.h"
 
 static void *
@@ -164,16 +164,16 @@ blorp_emit_3dstate_multisample(struct blorp_batch *batch, 
unsigned samples)
 
   switch (samples) {
   case 1:
- SAMPLE_POS_1X(ms.Sample);
+ GEN_SAMPLE_POS_1X(ms.Sample);
  break;
   case 2:
- SAMPLE_POS_2X(ms.Sample);
+ GEN_SAMPLE_POS_2X(ms.Sample);
  break;
   case 4:
- SAMPLE_POS_4X(ms.Sample);
+ GEN_SAMPLE_POS_4X(ms.Sample);
  break;
   case 8:
- SAMPLE_POS_8X(ms.Sample);
+ GEN_SAMPLE_POS_8X(ms.Sample);
  break;
   default:
  break;
diff --git a/src/intel/vulkan/genX_pipeline_util.h 
b/src/intel/vulkan/genX_pipeline_util.h
index 2c0bf3f..0ff92f1 100644
--- a/src/intel/vulkan/genX_pipeline_util.h
+++ b/src/intel/vulkan/genX_pipeline_util.h
@@ -22,8 +22,8 @@
  */
 
 #include "common/gen_l3_config.h"
+#include "common/gen_sample_positions.h"
 #include "vk_format_info.h"
-#include "genX_multisample.h"
 
 static uint32_t
 vertex_element_comp_control(enum isl_format format, unsigned comp)
@@ -610,16 +610,16 @@ emit_ms_state(struct anv_pipeline *pipeline,
 
   switch (samples) {
   case 1:
- SAMPLE_POS_1X(ms.Sample);
+ GEN_SAMPLE_POS_1X(ms.Sample);
  break;
   case 2:
- SAMPLE_POS_2X(ms.Sample);
+ GEN_SAMPLE_POS_2X(ms.Sample);
  break;
   case 4:
- SAMPLE_POS_4X(ms.Sample);
+ GEN_SAMPLE_POS_4X(ms.Sample);
  break;
   case 8:
- SAMPLE_POS_8X(ms.Sample);
+ GEN_SAMPLE_POS_8X(ms.Sample);
  break;
   default:
  break;
diff --git a/src/intel/vulkan/genX_state.c b/src/intel/vulkan/genX_state.c
index 2849b50..a6d405d 100644
--- a/src/intel/vulkan/genX_state.c
+++ b/src/intel/vulkan/genX_state.c
@@ -28,8 +28,8 @@
 #include 
 
 #include "anv_private.h"
-#include "genX_multisample.h"
 
+#include "common/gen_sample_positions.h"
 #include "genxml/gen_macros.h"
 #include "genxml/genX_pack.h"
 
@@ -77,12 +77,12 @@ genX(init_device_state)(struct anv_device *device)
 * VkPhysicalDeviceFeatures::standardSampleLocations.
 */
anv_batch_emit(, GENX(3DSTATE_SAMPLE_PATTERN), sp) {
-  SAMPLE_POS_1X(sp._1xSample);
-  SAMPLE_POS_2X(sp._2xSample);
-  SAMPLE_POS_4X(sp._4xSample);
-  SAMPLE_POS_8X(sp._8xSample);
+  GEN_SAMPLE_POS_1X(sp._1xSample);
+  GEN_SAMPLE_POS_2X(sp._2xSample);
+  GEN_SAMPLE_POS_4X(sp._4xSample);
+  GEN_SAMPLE_POS_8X(sp._8xSample);
 #if GEN_GEN >= 9
-  

[Mesa-dev] [PATCH 3/3] intel/blorp: Stop setting 3DSTATE_DRAWING_RECTANGLE

[Jason Ekstrand]

The Vulkan driver sets 3DSTATE_DRAWING_RECTANGLE once to MAX_INT x MAX_INT
at the GPU initialization time and never sets it again.  The GL driver sets
it every time the framebuffer changes.  Originally, blorp set it to the
size of the drawing area but meant we had to set it back in the Vulkan
driver.  Instead, we can easily just do that in the GL driver's blorp_exec
implementation and not set it in blorp core.

Signed-off-by: Jason Ekstrand 
---
 src/intel/blorp/blorp_genX_exec.h   |  5 -
 src/intel/vulkan/genX_blorp_exec.c  | 15 ---
 src/mesa/drivers/dri/i965/genX_blorp_exec.c |  5 +
 3 files changed, 5 insertions(+), 20 deletions(-)

diff --git a/src/intel/blorp/blorp_genX_exec.h 
b/src/intel/blorp/blorp_genX_exec.h
index aff59e1..eb4a5b9 100644
--- a/src/intel/blorp/blorp_genX_exec.h
+++ b/src/intel/blorp/blorp_genX_exec.h
@@ -1216,11 +1216,6 @@ blorp_exec(struct blorp_batch *batch, const struct 
blorp_params *params)
   clear.DepthClearValue = params->depth.clear_color.u32[0];
}
 
-   blorp_emit(batch, GENX(3DSTATE_DRAWING_RECTANGLE), rect) {
-  rect.ClippedDrawingRectangleXMax = MAX2(params->x1, params->x0) - 1;
-  rect.ClippedDrawingRectangleYMax = MAX2(params->y1, params->y0) - 1;
-   }
-
blorp_emit(batch, GENX(3DPRIMITIVE), prim) {
   prim.VertexAccessType = SEQUENTIAL;
   prim.PrimitiveTopologyType = _3DPRIM_RECTLIST;
diff --git a/src/intel/vulkan/genX_blorp_exec.c 
b/src/intel/vulkan/genX_blorp_exec.c
index a3ad97a..5ddbb7d 100644
--- a/src/intel/vulkan/genX_blorp_exec.c
+++ b/src/intel/vulkan/genX_blorp_exec.c
@@ -203,21 +203,6 @@ genX(blorp_exec)(struct blorp_batch *batch,
 
blorp_exec(batch, params);
 
-   /* BLORP sets DRAWING_RECTANGLE but we always want it set to the maximum.
-* Since we set it once at driver init and never again, we have to set it
-* back after invoking blorp.
-*
-* TODO: BLORP should assume a max drawing rectangle
-*/
-   blorp_emit(batch, GENX(3DSTATE_DRAWING_RECTANGLE), rect) {
-  rect.ClippedDrawingRectangleYMin = 0;
-  rect.ClippedDrawingRectangleXMin = 0;
-  rect.ClippedDrawingRectangleYMax = UINT16_MAX;
-  rect.ClippedDrawingRectangleXMax = UINT16_MAX;
-  rect.DrawingRectangleOriginY = 0;
-  rect.DrawingRectangleOriginX = 0;
-   }
-
cmd_buffer->state.vb_dirty = ~0;
cmd_buffer->state.dirty = ~0;
cmd_buffer->state.push_constants_dirty = ~0;
diff --git a/src/mesa/drivers/dri/i965/genX_blorp_exec.c 
b/src/mesa/drivers/dri/i965/genX_blorp_exec.c
index 8cd5a62..edcd896 100644
--- a/src/mesa/drivers/dri/i965/genX_blorp_exec.c
+++ b/src/mesa/drivers/dri/i965/genX_blorp_exec.c
@@ -206,6 +206,11 @@ retry:
 
brw_emit_depth_stall_flushes(brw);
 
+   blorp_emit(batch, GENX(3DSTATE_DRAWING_RECTANGLE), rect) {
+  rect.ClippedDrawingRectangleXMax = MAX2(params->x1, params->x0) - 1;
+  rect.ClippedDrawingRectangleYMax = MAX2(params->y1, params->y0) - 1;
+   }
+
blorp_exec(batch, params);
 
/* Make sure we didn't wrap the batch unintentionally, and make sure we
-- 
2.5.0.400.gff86faf

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Re: [Mesa-dev] [PATCH 01/20] gallium/radeon: derive buffer placement and flags only at initialization

[Marek Olšák]

This might fix it:
"[PATCH 1/7] gallium/radeon: set new r600_resource fields correctly in
other places too"

It should be on mesa-dev by now.

Marek

On Mon, Sep 12, 2016 at 5:30 AM, Michel Dänzer  wrote:
> On 12/09/16 10:15 AM, Michel Dänzer wrote:
>> On 30/08/16 12:28 AM, Marek Olšák wrote:
>>> From: Marek Olšák 
>>>
>>> Invalidated buffers don't have to go through it.
>>>
>>> Split r600_init_resource into r600_init_resource_fields and
>>> r600_alloc_resource.
>>
>> This change caused Portal 2 to crash for me (with Kaveri using the
>> radeon kernel driver),
>
> On another machine using the amdgpu kernel driver (also with Kaveri), it
> doesn't crash, but the intro videos and main menu background are
> severely corrupted.
>
>
>> see below. Let me know if you need more information.
>>
>>
>> Thread 1 "portal2_linux" received signal SIGSEGV, Segmentation fault.
>> 0xf4c3f500 in util_copy_rect (dst=0xe57fa000 > address 0xe57fa000>, format=, dst_stride=, 
>> dst_x=, dst_y=, width=640, height=> out>,
>> src=0xe0fc000 '\200' ..., src_stride=, 
>> src_x=, src_y=) at 
>> ../../../../src/gallium/auxiliary/util/u_surface.c:105
>> 105memcpy(dst, src, width);
>> (gdb) bt
>> #0  0xf4c3f500 in util_copy_rect (dst=0xe57fa000 > memory at address 0xe57fa000>, format=, dst_stride=> out>, dst_x=, dst_y=, width=640, 
>> height=,
>> src=0xe0fc000 '\200' ..., src_stride=, 
>> src_x=, src_y=) at 
>> ../../../../src/gallium/auxiliary/util/u_surface.c:105
>> #1  0xf4c3f616 in util_copy_box (dst=0xe57be000 > at address 0xe57be000>, format=PIPE_FORMAT_L8_SRGB, dst_stride=768, 
>> dst_slice_stride=276480, dst_x=0, dst_y=0, dst_z=0, width=640, height=360, 
>> depth=1,
>> src=0xe0ca000 '\200' ..., src_stride=640, 
>> src_slice_stride=230400, src_x=0, src_y=0, src_z=0) at 
>> ../../../../src/gallium/auxiliary/util/u_surface.c:131
>> #2  0xf4c4400e in u_default_texture_subdata (pipe=0xa18a000, 
>> resource=0xd6d0800, level=0, usage=258, box=0xff826b38, data=0xe0ca000, 
>> stride=640, layer_stride=230400) at 
>> ../../../../src/gallium/auxiliary/util/u_transfer.c:67
>> #3  0xf4a62123 in st_TexSubImage (ctx=0xa344000, dims=2, texImage=0xd666900, 
>> xoffset=0, yoffset=0, zoffset=0, width=640, height=360, depth=1, 
>> format=6409, type=5121, pixels=0xe0ca000, unpack=0xa35be3c) at 
>> ../../../src/mesa/state_tracker/st_cb_texture.c:1400
>> #4  0xf49ed48d in _mesa_texture_sub_image (ctx=0xa344000, dims=2, 
>> texObj=0xd167b80, texImage=0xd666900, target=3553, level=0, xoffset=0, 
>> yoffset=0, zoffset=0, width=640, height=360, depth=1, format=6409, 
>> type=5121, pixels=0xe0ca000, dsa=false)
>> at ../../../src/mesa/main/teximage.c:3239
>> #5  0xf49ed696 in texsubimage (ctx=0xa344000, dims=2, target=3553, level=0, 
>> xoffset=0, yoffset=0, zoffset=0, width=640, height=360, depth=1, 
>> format=6409, type=5121, pixels=0xe0ca000, callerName=0xf4d9380a 
>> "glTexSubImage2D")
>> at ../../../src/mesa/main/teximage.c:3297
>> #6  0xf49ed98a in _mesa_TexSubImage2D (target=3553, level=0, xoffset=0, 
>> yoffset=0, width=640, height=360, format=6409, type=5121, pixels=0xe0ca000) 
>> at ../../../src/mesa/main/teximage.c:3438
>> #7  0xf5792b98 in ?? () from 
>> /home/daenzer/.steam/steam/steamapps/common/Portal 2/bin/libtogl.so
>> #8  0xf5792db5 in ?? () from 
>> /home/daenzer/.steam/steam/steamapps/common/Portal 2/bin/libtogl.so
>> #9  0xf579f84b in IDirect3DSurface9::UnlockRect() () from 
>> /home/daenzer/.steam/steam/steamapps/common/Portal 2/bin/libtogl.so
>> #10 0xed478ddb in ?? () from 
>> /home/daenzer/.steam/steam/steamapps/common/Portal 2/bin/shaderapidx9.so
>> #11 0xed466cb3 in ?? () from 
>> /home/daenzer/.steam/steam/steamapps/common/Portal 2/bin/shaderapidx9.so
>> #12 0xedfdce2b in ?? () from 
>> /home/daenzer/.steam/steam/steamapps/common/Portal 2/bin/materialsystem.so
>> #13 0xedfdda41 in ?? () from 
>> /home/daenzer/.steam/steam/steamapps/common/Portal 2/bin/materialsystem.so
>> #14 0xedfddbf8 in ?? () from 
>> /home/daenzer/.steam/steam/steamapps/common/Portal 2/bin/materialsystem.so
>> #15 0xedfddc62 in ?? () from 
>> /home/daenzer/.steam/steam/steamapps/common/Portal 2/bin/materialsystem.so
>> #16 0xed88050f in ?? () from 
>> /home/daenzer/.steam/steam/steamapps/common/Portal 2/bin/valve_avi.so
>> #17 0xed8806c8 in ?? () from 
>> /home/daenzer/.steam/steam/steamapps/common/Portal 2/bin/valve_avi.so
>> #18 0xee87fd62 in ?? () from 
>> /home/daenzer/.steam/steam/steamapps/common/Portal 2/bin/engine.so
>> #19 0xee87f316 in ?? () from 
>> /home/daenzer/.steam/steam/steamapps/common/Portal 2/bin/engine.so
>> #20 0xee87ec53 in ?? () from 
>> /home/daenzer/.steam/steam/steamapps/common/Portal 2/bin/engine.so
>> #21 0xee87ccf5 in ?? () from 
>> /home/daenzer/.steam/steam/steamapps/common/Portal 2/bin/engine.so
>> #22 0xee87d5ff in ?? () from 
>> /home/daenzer/.steam/steam/steamapps/common/Portal 2/bin/engine.so
>> #23 0xee877536 in ?? () from 
>> 

[Mesa-dev] [PATCH 4/7] radeonsi: print the IB and buffer list in VM fault reports

[Marek Olšák]

From: Marek Olšák 

This is a fallout from reworking the debug flags.
---
 src/gallium/drivers/radeonsi/si_debug.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/src/gallium/drivers/radeonsi/si_debug.c 
b/src/gallium/drivers/radeonsi/si_debug.c
index 8ce9caf..75ab0e7 100644
--- a/src/gallium/drivers/radeonsi/si_debug.c
+++ b/src/gallium/drivers/radeonsi/si_debug.c
@@ -822,21 +822,22 @@ void si_check_vm_faults(struct r600_common_context *ctx,
fprintf(f, "Failing VM page: 0x%08x\n\n", addr);
 
if (sctx->apitrace_call_number)
fprintf(f, "Last apitrace call: %u\n\n",
sctx->apitrace_call_number);
 
switch (ring) {
case RING_GFX:
si_dump_debug_state(>b.b, f,
PIPE_DUMP_CURRENT_STATES |
-   PIPE_DUMP_CURRENT_SHADERS);
+   PIPE_DUMP_CURRENT_SHADERS |
+   PIPE_DUMP_LAST_COMMAND_BUFFER);
break;
 
case RING_DMA:
si_dump_dma(sctx, saved, f);
break;
 
default:
break;
}
 
-- 
2.7.4

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[Mesa-dev] [PATCH 7/7] radeonsi: fix FP64 UBO loads with indirect uniform block indexing

[Marek Olšák]

From: Marek Olšák 

No known tests.

Cc: mesa-sta...@lists.freedesktop.org
---
 src/gallium/drivers/radeonsi/si_shader.c | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/src/gallium/drivers/radeonsi/si_shader.c 
b/src/gallium/drivers/radeonsi/si_shader.c
index 6d30d1c..be6fae7 100644
--- a/src/gallium/drivers/radeonsi/si_shader.c
+++ b/src/gallium/drivers/radeonsi/si_shader.c
@@ -1917,22 +1917,21 @@ static LLVMValueRef fetch_constant(
if (!tgsi_type_is_64bit(type))
result = bitcast(bld_base, type, result);
else {
LLVMValueRef addr2, result2;
addr2 = ctx->radeon_bld.soa.addr[ireg->Index][ireg->Swizzle + 
1];
addr2 = LLVMBuildLoad(base->gallivm->builder, addr2, "load addr 
reg2");
addr2 = lp_build_mul_imm(_base->uint_bld, addr2, 16);
addr2 = lp_build_add(_base->uint_bld, addr2,
 lp_build_const_int32(base->gallivm, idx * 
4));
 
-   result2 = buffer_load_const(ctx, ctx->const_buffers[buf],
-   addr2);
+   result2 = buffer_load_const(ctx, bufp, addr2);
 
result = radeon_llvm_emit_fetch_64bit(bld_base, type,
  result, result2);
}
return result;
 }
 
 /* Upper 16 bits must be zero. */
 static LLVMValueRef si_llvm_pack_two_int16(struct gallivm_state *gallivm,
   LLVMValueRef val[2])
-- 
2.7.4

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[Mesa-dev] [PATCH 5/7] radeonsi: clean up CP DMA emit code

[Marek Olšák]

From: Marek Olšák 

Unify the clear and copy paths, clean up the definitions.
It looks more like a rework. It's a preparation for GDS support,
which might or might not come.
---
 src/gallium/drivers/radeonsi/si_cp_dma.c | 144 +--
 1 file changed, 60 insertions(+), 84 deletions(-)

diff --git a/src/gallium/drivers/radeonsi/si_cp_dma.c 
b/src/gallium/drivers/radeonsi/si_cp_dma.c
index 08d3dfe..0e8d1e8 100644
--- a/src/gallium/drivers/radeonsi/si_cp_dma.c
+++ b/src/gallium/drivers/radeonsi/si_cp_dma.c
@@ -21,111 +21,93 @@
  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  *
  * Authors:
  *  Marek Olšák 
  */
 
 #include "si_pipe.h"
 #include "sid.h"
 #include "radeon/r600_cs.h"
 
+/* Alignment for optimal performance. */
+#define CP_DMA_ALIGNMENT   32
+/* The max number of bytes to copy per packet. */
+#define CP_DMA_MAX_BYTE_COUNT  ((1 << 21) - CP_DMA_ALIGNMENT)
 
-/* Set this if you want the 3D engine to wait until CP DMA is done.
+/* Set this if you want the ME to wait until CP DMA is done.
  * It should be set on the last CP DMA packet. */
-#define R600_CP_DMA_SYNC   (1 << 0) /* R600+ */
+#define CP_DMA_SYNC(1 << 0)
 
 /* Set this if the source data was used as a destination in a previous CP DMA
  * packet. It's for preventing a read-after-write (RAW) hazard between two
  * CP DMA packets. */
-#define SI_CP_DMA_RAW_WAIT (1 << 1) /* SI+ */
-#define CIK_CP_DMA_USE_L2  (1 << 2)
+#define CP_DMA_RAW_WAIT(1 << 1)
+#define CP_DMA_USE_L2  (1 << 2) /* CIK+ */
+#define CP_DMA_CLEAR   (1 << 3)
 
-/* Emit a CP DMA packet to do a copy from one buffer to another.
- * The size must fit in bits [20:0].
+/* Emit a CP DMA packet to do a copy from one buffer to another, or to clear
+ * a buffer. The size must fit in bits [20:0]. If CP_DMA_CLEAR is set, src_va 
is a 32-bit
+ * clear value.
  */
-static void si_emit_cp_dma_copy_buffer(struct si_context *sctx,
-  uint64_t dst_va, uint64_t src_va,
-  unsigned size, unsigned flags)
+static void si_emit_cp_dma(struct si_context *sctx, uint64_t dst_va,
+  uint64_t src_va, unsigned size, unsigned flags,
+  enum r600_coherency coher)
 {
struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
-   uint32_t sync_flag = flags & R600_CP_DMA_SYNC ? S_411_CP_SYNC(1) : 0;
-   uint32_t wr_confirm = !(flags & R600_CP_DMA_SYNC) ? 
S_414_DISABLE_WR_CONFIRM(1) : 0;
-   uint32_t raw_wait = flags & SI_CP_DMA_RAW_WAIT ? S_414_RAW_WAIT(1) : 0;
-   uint32_t sel = flags & CIK_CP_DMA_USE_L2 ?
-  S_411_SRC_SEL(V_411_SRC_ADDR_TC_L2) |
-  S_411_DSL_SEL(V_411_DST_ADDR_TC_L2) : 0;
+   uint32_t header = 0, command = S_414_BYTE_COUNT(size);
 
assert(size);
-   assert((size & ((1<<21)-1)) == size);
+   assert(size <= CP_DMA_MAX_BYTE_COUNT);
+
+   /* Sync flags. */
+   if (flags & CP_DMA_SYNC)
+   header |= S_411_CP_SYNC(1);
+   else
+   command |= S_414_DISABLE_WR_CONFIRM(1);
+
+   if (flags & CP_DMA_RAW_WAIT)
+   command |= S_414_RAW_WAIT(1);
+
+   /* Src and dst flags. */
+   if (flags & CP_DMA_USE_L2)
+   header |= S_411_DSL_SEL(V_411_DST_ADDR_TC_L2);
+
+   if (flags & CP_DMA_CLEAR)
+   header |= S_411_SRC_SEL(V_411_DATA);
+   else if (flags & CP_DMA_USE_L2)
+   header |= S_411_SRC_SEL(V_411_SRC_ADDR_TC_L2);
 
if (sctx->b.chip_class >= CIK) {
radeon_emit(cs, PKT3(PKT3_DMA_DATA, 5, 0));
-   radeon_emit(cs, sync_flag | sel);   /* CP_SYNC [31] */
-   radeon_emit(cs, src_va);/* SRC_ADDR_LO [31:0] */
-   radeon_emit(cs, src_va >> 32);  /* SRC_ADDR_HI [31:0] */
-   radeon_emit(cs, dst_va);/* DST_ADDR_LO [31:0] */
-   radeon_emit(cs, dst_va >> 32);  /* DST_ADDR_HI [31:0] */
-   radeon_emit(cs, size | wr_confirm | raw_wait);  /* COMMAND 
[29:22] | BYTE_COUNT [20:0] */
+   radeon_emit(cs, header);
+   radeon_emit(cs, src_va);/* SRC_ADDR_LO [31:0] */
+   radeon_emit(cs, src_va >> 32);  /* SRC_ADDR_HI [31:0] */
+   radeon_emit(cs, dst_va);/* DST_ADDR_LO [31:0] */
+   radeon_emit(cs, dst_va >> 32);  /* DST_ADDR_HI [31:0] */
+   radeon_emit(cs, command);
} else {
+   header |= S_411_SRC_ADDR_HI(src_va >> 32);
+
radeon_emit(cs, PKT3(PKT3_CP_DMA, 4, 0));
-   radeon_emit(cs, src_va);/* SRC_ADDR_LO 
[31:0] */
-   radeon_emit(cs, sync_flag | ((src_va >> 32) & 0x)); /* 
CP_SYNC [31] | SRC_ADDR_HI [15:0] */
-   radeon_emit(cs, dst_va);/* DST_ADDR_LO 

[Mesa-dev] [PATCH 3/7] radeonsi: add sampler view BOs to the BO list last

[Marek Olšák]

From: Marek Olšák 

This might not be stricly needed, but better safe than sorry.
---
 src/gallium/drivers/radeonsi/si_descriptors.c | 17 ++---
 1 file changed, 10 insertions(+), 7 deletions(-)

diff --git a/src/gallium/drivers/radeonsi/si_descriptors.c 
b/src/gallium/drivers/radeonsi/si_descriptors.c
index b9fae79..b1a8594 100644
--- a/src/gallium/drivers/radeonsi/si_descriptors.c
+++ b/src/gallium/drivers/radeonsi/si_descriptors.c
@@ -403,24 +403,20 @@ static void si_set_sampler_view(struct si_context *sctx,
struct si_sampler_view *rview = (struct si_sampler_view*)view;
struct si_descriptors *descs = si_sampler_descriptors(sctx, shader);
 
if (views->views[slot] == view && !disallow_early_out)
return;
 
if (view) {
struct r600_texture *rtex = (struct r600_texture 
*)view->texture;
uint32_t *desc = descs->list + slot * 16;
 
-   si_sampler_view_add_buffer(sctx, view->texture,
-  RADEON_USAGE_READ,
-  rview->is_stencil_sampler, true);
-
pipe_sampler_view_reference(>views[slot], view);
memcpy(desc, rview->state, 8*4);
 
if (view->texture && view->texture->target != PIPE_BUFFER) {
bool is_separate_stencil =
rtex->db_compatible &&
rview->is_stencil_sampler;
 
si_set_mutable_tex_desc_fields(rtex,
   rview->base_level_info,
@@ -439,20 +435,26 @@ static void si_set_sampler_view(struct si_context *sctx,
/* Disable FMASK and bind sampler state in [12:15]. */
memcpy(desc + 8,
   null_texture_descriptor, 4*4);
 
if (views->sampler_states[slot])
memcpy(desc + 12,
   views->sampler_states[slot], 4*4);
}
 
views->enabled_mask |= 1u << slot;
+
+   /* Since this can flush, it must be done after enabled_mask is
+* updated. */
+   si_sampler_view_add_buffer(sctx, view->texture,
+  RADEON_USAGE_READ,
+  rview->is_stencil_sampler, true);
} else {
pipe_sampler_view_reference(>views[slot], NULL);
memcpy(descs->list + slot*16, null_texture_descriptor, 8*4);
/* Only clear the lower dwords of FMASK. */
memcpy(descs->list + slot*16 + 8, null_texture_descriptor, 4*4);
views->enabled_mask &= ~(1u << slot);
}
 
descs->dirty_mask |= 1u << slot;
sctx->descriptors_dirty |= 1u << si_sampler_descriptors_idx(shader);
@@ -620,23 +622,20 @@ static void si_set_shader_image(struct si_context *ctx,
if (!view || !view->resource) {
si_disable_shader_image(ctx, shader, slot);
return;
}
 
res = (struct r600_resource *)view->resource;
 
if (>views[slot] != view)
util_copy_image_view(>views[slot], view);
 
-   si_sampler_view_add_buffer(ctx, >b.b,
-  RADEON_USAGE_READWRITE, false, true);
-
if (res->b.b.target == PIPE_BUFFER) {
if (view->access & PIPE_IMAGE_ACCESS_WRITE)
si_mark_image_range_valid(view);
 
si_make_buffer_descriptor(screen, res,
  view->format,
  view->u.buf.offset,
  view->u.buf.size,
  descs->list + slot * 8);
images->compressed_colortex_mask &= ~(1 << slot);
@@ -695,20 +694,24 @@ static void si_set_shader_image(struct si_context *ctx,
   desc, NULL);
si_set_mutable_tex_desc_fields(tex, >surface.level[level],
   level, level,
   
util_format_get_blockwidth(view->format),
   false, desc);
}
 
images->enabled_mask |= 1u << slot;
descs->dirty_mask |= 1u << slot;
ctx->descriptors_dirty |= 1u << si_image_descriptors_idx(shader);
+
+   /* Since this can flush, it must be done after enabled_mask is updated. 
*/
+   si_sampler_view_add_buffer(ctx, >b.b,
+  RADEON_USAGE_READWRITE, false, true);
 }
 
 static void
 si_set_shader_images(struct pipe_context *pipe,
 enum pipe_shader_type shader,
 unsigned start_slot, unsigned count,
 const struct 

[Mesa-dev] [PATCH 2/7] radeonsi: export SampleMask from pixel shaders at full rate

[Marek Olšák]

From: Marek Olšák 

Heaven and Valley write gl_SampleMask and not Z.
Use 16_ABGR instead of 32_ABGR if Z isn't written.
---
 src/gallium/drivers/radeonsi/si_shader.c| 63 -
 src/gallium/drivers/radeonsi/si_shader.h|  2 +
 src/gallium/drivers/radeonsi/si_state_shaders.c |  7 ++-
 3 files changed, 56 insertions(+), 16 deletions(-)

diff --git a/src/gallium/drivers/radeonsi/si_shader.c 
b/src/gallium/drivers/radeonsi/si_shader.c
index 6801722..6d30d1c 100644
--- a/src/gallium/drivers/radeonsi/si_shader.c
+++ b/src/gallium/drivers/radeonsi/si_shader.c
@@ -2921,57 +2921,96 @@ static void si_llvm_emit_vs_epilogue(struct 
lp_build_tgsi_context *bld_base)
 
si_llvm_export_vs(bld_base, outputs, i);
FREE(outputs);
 }
 
 struct si_ps_exports {
unsigned num;
LLVMValueRef args[10][9];
 };
 
+unsigned si_get_spi_shader_z_format(bool writes_z, bool writes_stencil,
+   bool writes_samplemask)
+{
+   if (writes_z) {
+   /* Z needs 32 bits. */
+   if (writes_samplemask)
+   return V_028710_SPI_SHADER_32_ABGR;
+   else if (writes_stencil)
+   return V_028710_SPI_SHADER_32_GR;
+   else
+   return V_028710_SPI_SHADER_32_R;
+   } else if (writes_stencil || writes_samplemask) {
+   /* Both stencil and sample mask need only 16 bits. */
+   return V_028710_SPI_SHADER_UINT16_ABGR;
+   } else {
+   return V_028710_SPI_SHADER_ZERO;
+   }
+}
+
 static void si_export_mrt_z(struct lp_build_tgsi_context *bld_base,
LLVMValueRef depth, LLVMValueRef stencil,
LLVMValueRef samplemask, struct si_ps_exports *exp)
 {
struct si_shader_context *ctx = si_shader_context(bld_base);
struct lp_build_context *base = _base->base;
struct lp_build_context *uint = _base->uint_bld;
LLVMValueRef args[9];
unsigned mask = 0;
+   unsigned format = si_get_spi_shader_z_format(depth != NULL,
+stencil != NULL,
+samplemask != NULL);
 
assert(depth || stencil || samplemask);
 
args[1] = uint->one; /* whether the EXEC mask is valid */
args[2] = uint->one; /* DONE bit */
 
/* Specify the target we are exporting */
args[3] = lp_build_const_int32(base->gallivm, V_008DFC_SQ_EXP_MRTZ);
 
args[4] = uint->zero; /* COMP flag */
args[5] = base->undef; /* R, depth */
args[6] = base->undef; /* G, stencil test value[0:7], stencil op 
value[8:15] */
args[7] = base->undef; /* B, sample mask */
args[8] = base->undef; /* A, alpha to mask */
 
-   if (depth) {
-   args[5] = depth;
-   mask |= 0x1;
-   }
-
-   if (stencil) {
-   args[6] = stencil;
-   mask |= 0x2;
-   }
+   if (format == V_028710_SPI_SHADER_UINT16_ABGR) {
+   assert(!depth);
+   args[4] = uint->one; /* COMPR flag */
 
-   if (samplemask) {
-   args[7] = samplemask;
-   mask |= 0x4;
+   if (stencil) {
+   /* Stencil should be in X[23:16]. */
+   stencil = bitcast(bld_base, TGSI_TYPE_UNSIGNED, 
stencil);
+   stencil = LLVMBuildShl(base->gallivm->builder, stencil,
+  LLVMConstInt(ctx->i32, 16, 0), 
"");
+   args[5] = bitcast(bld_base, TGSI_TYPE_FLOAT, stencil);
+   mask |= 0x3;
+   }
+   if (samplemask) {
+   /* SampleMask should be in Y[15:0]. */
+   args[6] = samplemask;
+   mask |= 0xc;
+   }
+   } else {
+   if (depth) {
+   args[5] = depth;
+   mask |= 0x1;
+   }
+   if (stencil) {
+   args[6] = stencil;
+   mask |= 0x2;
+   }
+   if (samplemask) {
+   args[7] = samplemask;
+   mask |= 0x4;
+   }
}
 
/* SI (except OLAND) has a bug that it only looks
 * at the X writemask component. */
if (ctx->screen->b.chip_class == SI &&
ctx->screen->b.family != CHIP_OLAND)
mask |= 0x1;
 
/* Specify which components to enable */
args[0] = lp_build_const_int32(base->gallivm, mask);
diff --git a/src/gallium/drivers/radeonsi/si_shader.h 
b/src/gallium/drivers/radeonsi/si_shader.h
index fc1b22d..de4705d 100644
--- a/src/gallium/drivers/radeonsi/si_shader.h
+++ b/src/gallium/drivers/radeonsi/si_shader.h
@@ -511,12 +511,14 @@ int 

[Mesa-dev] [PATCH 1/7] gallium/radeon: set new r600_resource fields correctly in other places too

[Marek Olšák]

From: Marek Olšák 

This was missed in:

commit 0d2e43fcb1198a6e67c85feadb1ca8c360ddc284
Author: Marek Olšák 
Date:   Thu Aug 18 16:30:00 2016 +0200

gallium/radeon: derive buffer placement and flags only at initialization
---
 src/gallium/drivers/radeon/r600_texture.c | 11 +++
 1 file changed, 11 insertions(+)

diff --git a/src/gallium/drivers/radeon/r600_texture.c 
b/src/gallium/drivers/radeon/r600_texture.c
index 41fd94b..1dbaff7 100644
--- a/src/gallium/drivers/radeon/r600_texture.c
+++ b/src/gallium/drivers/radeon/r600_texture.c
@@ -490,21 +490,26 @@ static void r600_degrade_tile_mode_to_linear(struct 
r600_common_context *rctx,
}
}
 
r600_texture_discard_cmask(rctx->screen, rtex);
r600_texture_discard_dcc(rctx->screen, rtex);
 
/* Replace the structure fields of rtex. */
rtex->resource.b.b.bind = templ.bind;
pb_reference(>resource.buf, new_tex->resource.buf);
rtex->resource.gpu_address = new_tex->resource.gpu_address;
+   rtex->resource.vram_usage = new_tex->resource.vram_usage;
+   rtex->resource.gart_usage = new_tex->resource.gart_usage;
+   rtex->resource.bo_size = new_tex->resource.bo_size;
+   rtex->resource.bo_alignment = new_tex->resource.bo_alignment;
rtex->resource.domains = new_tex->resource.domains;
+   rtex->resource.flags = new_tex->resource.flags;
rtex->size = new_tex->size;
rtex->surface = new_tex->surface;
rtex->non_disp_tiling = new_tex->non_disp_tiling;
rtex->cb_color_info = new_tex->cb_color_info;
rtex->cmask = new_tex->cmask; /* needed even without CMASK */
 
assert(!rtex->htile_buffer);
assert(!rtex->cmask.size);
assert(!rtex->fmask.size);
assert(!rtex->dcc_offset);
@@ -1112,21 +1117,27 @@ r600_texture_create_object(struct pipe_screen *screen,
r600_init_resource_fields(rscreen, resource, rtex->size,
  rtex->surface.bo_alignment);
 
if (!r600_alloc_resource(rscreen, resource)) {
FREE(rtex);
return NULL;
}
} else {
resource->buf = buf;
resource->gpu_address = 
rscreen->ws->buffer_get_virtual_address(resource->buf);
+   resource->bo_size = buf->size;
+   resource->bo_alignment = buf->alignment;
resource->domains = 
rscreen->ws->buffer_get_initial_domain(resource->buf);
+   if (resource->domains & RADEON_DOMAIN_VRAM)
+   resource->vram_usage = buf->size;
+   else if (resource->domains & RADEON_DOMAIN_GTT)
+   resource->gart_usage = buf->size;
}
 
if (rtex->cmask.size) {
/* Initialize the cmask to 0xCC (= compressed state). */
r600_screen_clear_buffer(rscreen, >cmask_buffer->b.b,
 rtex->cmask.offset, rtex->cmask.size,
 0x, R600_COHERENCY_NONE);
}
 
/* Initialize DCC only if the texture is not being imported. */
-- 
2.7.4

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[Mesa-dev] [PATCH 6/7] winsys/amdgpu: don't assume GTT if the VRAM flag isn't set

[Marek Olšák]

From: Marek Olšák 

---
 src/gallium/winsys/amdgpu/drm/amdgpu_bo.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/src/gallium/winsys/amdgpu/drm/amdgpu_bo.c 
b/src/gallium/winsys/amdgpu/drm/amdgpu_bo.c
index a6d4aa4..5b099b0 100644
--- a/src/gallium/winsys/amdgpu/drm/amdgpu_bo.c
+++ b/src/gallium/winsys/amdgpu/drm/amdgpu_bo.c
@@ -138,21 +138,21 @@ void amdgpu_bo_destroy(struct pb_buffer *_buf)
amdgpu_fence_reference(>fence, NULL);
 
if (bo->initial_domain & RADEON_DOMAIN_VRAM)
   bo->ws->allocated_vram -= align64(bo->base.size, 
bo->ws->info.gart_page_size);
else if (bo->initial_domain & RADEON_DOMAIN_GTT)
   bo->ws->allocated_gtt -= align64(bo->base.size, 
bo->ws->info.gart_page_size);
 
if (bo->map_count >= 1) {
   if (bo->initial_domain & RADEON_DOMAIN_VRAM)
  bo->ws->mapped_vram -= bo->base.size;
-  else
+  else if (bo->initial_domain & RADEON_DOMAIN_GTT)
  bo->ws->mapped_gtt -= bo->base.size;
}
 
FREE(bo);
 }
 
 static void amdgpu_bo_destroy_or_cache(struct pb_buffer *_buf)
 {
struct amdgpu_winsys_bo *bo = amdgpu_winsys_bo(_buf);
 
@@ -254,37 +254,37 @@ static void *amdgpu_bo_map(struct pb_buffer *buf,
   /* Clear the cache and try again. */
   pb_cache_release_all_buffers(>ws->bo_cache);
   r = amdgpu_bo_cpu_map(bo->bo, );
   if (r)
  return NULL;
}
 
if (p_atomic_inc_return(>map_count) == 1) {
   if (bo->initial_domain & RADEON_DOMAIN_VRAM)
  bo->ws->mapped_vram += bo->base.size;
-  else
+  else if (bo->initial_domain & RADEON_DOMAIN_GTT)
  bo->ws->mapped_gtt += bo->base.size;
}
return cpu;
 }
 
 static void amdgpu_bo_unmap(struct pb_buffer *buf)
 {
struct amdgpu_winsys_bo *bo = (struct amdgpu_winsys_bo*)buf;
 
if (bo->user_ptr)
   return;
 
if (p_atomic_dec_zero(>map_count)) {
   if (bo->initial_domain & RADEON_DOMAIN_VRAM)
  bo->ws->mapped_vram -= bo->base.size;
-  else
+  else if (bo->initial_domain & RADEON_DOMAIN_GTT)
  bo->ws->mapped_gtt -= bo->base.size;
}
 
amdgpu_bo_cpu_unmap(bo->bo);
 }
 
 static const struct pb_vtbl amdgpu_winsys_bo_vtbl = {
amdgpu_bo_destroy_or_cache
/* other functions are never called */
 };
-- 
2.7.4

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Re: [Mesa-dev] [PATCH 1/3] intel/isl: Treat 3-D textures as 2-D arrays for rendering

[Kenneth Graunke]

On Monday, September 12, 2016 3:16:29 PM PDT Jason Ekstrand wrote:
> In particular, this means that isl_view::base_array_layer and
> isl_view::array_len get applied to 3-D textures but only when rendering.
> We were already applying isl_view::base_array_layer for rendering into 3-D
> textures so this isn't a huge deviation.
> 
> Signed-off-by: Jason Ekstrand 
> Cc: Chad Versace 

These three are:
Reviewed-by: Kenneth Graunke 

but you might want Chad or someone more familiar to comment.


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[Mesa-dev] [PATCH 06/14] egl: Use _eglCreatePixmapSurfaceCommon consistently

[Adam Jackson]

From: Kyle Brenneman 

This moves the native pixmap fixup to a helper function so we don't
repeat ourselves.
---
 src/egl/main/eglapi.c | 36 +---
 1 file changed, 21 insertions(+), 15 deletions(-)

diff --git a/src/egl/main/eglapi.c b/src/egl/main/eglapi.c
index dd2b4cc..fac2d18 100644
--- a/src/egl/main/eglapi.c
+++ b/src/egl/main/eglapi.c
@@ -813,6 +813,22 @@ eglCreatePlatformWindowSurface(EGLDisplay dpy, EGLConfig 
config,
return surface;
 }
 
+static void *
+fixupNativePixmap(_EGLDisplay *disp, void *native_pixmap)
+{
+#ifdef HAVE_X11_PLATFORM
+  /* The `native_pixmap` parameter for the X11 platform differs between
+   * eglCreatePixmapSurface() and eglCreatePlatformPixmapSurfaceEXT(). In
+   * eglCreatePixmapSurface(), the type of `native_pixmap` is an Xlib
+   * `Pixmap`. In eglCreatePlatformPixmapSurfaceEXT(), the type is
+   * `Pixmap*`.  Convert `Pixmap*` to `Pixmap` because that's what
+   * dri2_x11_create_pixmap_surface() expects.
+   */
+   if (disp->Platform == _EGL_PLATFORM_X11 && native_pixmap != NULL)
+  return (void *)(* (Pixmap*) native_pixmap);
+#endif
+   return native_pixmap;
+}
 
 static EGLSurface
 _eglCreatePixmapSurfaceCommon(_EGLDisplay *disp, EGLConfig config,
@@ -849,19 +865,7 @@ eglCreatePlatformPixmapSurfaceEXT(EGLDisplay dpy, 
EGLConfig config,
 {
_EGLDisplay *disp = _eglLockDisplay(dpy);
 
-#ifdef HAVE_X11_PLATFORM
-  /* The `native_pixmap` parameter for the X11 platform differs between
-   * eglCreatePixmapSurface() and eglCreatePlatformPixmapSurfaceEXT(). In
-   * eglCreatePixmapSurface(), the type of `native_pixmap` is an Xlib
-   * `Pixmap`. In eglCreatePlatformPixmapSurfaceEXT(), the type is
-   * `Pixmap*`.  Convert `Pixmap*` to `Pixmap` because that's what
-   * dri2_x11_create_pixmap_surface() expects.
-   */
-   if (disp->Platform == _EGL_PLATFORM_X11 && native_pixmap != NULL) {
-  native_pixmap = (void*) (* (Pixmap*) native_pixmap);
-   }
-#endif
-
+   native_pixmap = fixupNativePixmap(disp, native_pixmap);
return _eglCreatePixmapSurfaceCommon(disp, config, native_pixmap,
 attrib_list);
 }
@@ -872,14 +876,16 @@ eglCreatePlatformPixmapSurface(EGLDisplay dpy, EGLConfig 
config,
void *native_pixmap,
const EGLAttrib *attrib_list)
 {
+   _EGLDisplay *disp = _eglLockDisplay(dpy);
EGLSurface surface;
EGLint *int_attribs = _eglConvertAttribsToInt(attrib_list);
 
if (attrib_list && !int_attribs)
   RETURN_EGL_ERROR(NULL, EGL_BAD_ALLOC, EGL_NO_SURFACE);
 
-   surface = eglCreatePlatformPixmapSurfaceEXT(dpy, config, native_pixmap,
-   int_attribs);
+   native_pixmap = fixupNativePixmap(disp, native_pixmap);
+   surface = _eglCreatePixmapSurfaceCommon(disp, config, native_pixmap,
+   int_attribs);
free(int_attribs);
return surface;
 }
-- 
2.9.3

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[Mesa-dev] [PATCH 01/14] egl: Update eglext.h (v2)

[Adam Jackson]

From: Kyle Brenneman 

Updated eglext.h to revision 33111 from the Khronos repository.

v2:
- Don't (re)move extension includes from eglext.h (Emil Velikov)
- Bump to revision 33111 (Adam Jackson)

Reviewed-by: Adam Jackson 
---
 include/EGL/eglext.h | 121 +--
 1 file changed, 118 insertions(+), 3 deletions(-)

diff --git a/include/EGL/eglext.h b/include/EGL/eglext.h
index 6043b37..4ccbab8 100644
--- a/include/EGL/eglext.h
+++ b/include/EGL/eglext.h
@@ -6,7 +6,7 @@ extern "C" {
 #endif
 
 /*
-** Copyright (c) 2013-2014 The Khronos Group Inc.
+** Copyright (c) 2013-2016 The Khronos Group Inc.
 **
 ** Permission is hereby granted, free of charge, to any person obtaining a
 ** copy of this software and/or associated documentation files (the
@@ -38,7 +38,7 @@ extern "C" {
 
 #include 
 
-#define EGL_EGLEXT_VERSION 20150508
+#define EGL_EGLEXT_VERSION 20160809
 
 /* Generated C header for:
  * API: egl
@@ -99,6 +99,33 @@ EGLAPI EGLSyncKHR EGLAPIENTRY eglCreateSync64KHR (EGLDisplay 
dpy, EGLenum type,
 #define EGL_CONTEXT_OPENGL_NO_ERROR_KHR   0x31B3
 #endif /* EGL_KHR_create_context_no_error */
 
+#ifndef EGL_KHR_debug
+#define EGL_KHR_debug 1
+typedef void *EGLLabelKHR;
+typedef void *EGLObjectKHR;
+typedef void (EGLAPIENTRY  *EGLDEBUGPROCKHR)(EGLenum error,const char 
*command,EGLint messageType,EGLLabelKHR threadLabel,EGLLabelKHR 
objectLabel,const char* message);
+#define EGL_OBJECT_THREAD_KHR 0x33B0
+#define EGL_OBJECT_DISPLAY_KHR0x33B1
+#define EGL_OBJECT_CONTEXT_KHR0x33B2
+#define EGL_OBJECT_SURFACE_KHR0x33B3
+#define EGL_OBJECT_IMAGE_KHR  0x33B4
+#define EGL_OBJECT_SYNC_KHR   0x33B5
+#define EGL_OBJECT_STREAM_KHR 0x33B6
+#define EGL_DEBUG_MSG_CRITICAL_KHR0x33B9
+#define EGL_DEBUG_MSG_ERROR_KHR   0x33BA
+#define EGL_DEBUG_MSG_WARN_KHR0x33BB
+#define EGL_DEBUG_MSG_INFO_KHR0x33BC
+#define EGL_DEBUG_CALLBACK_KHR0x33B8
+typedef EGLint (EGLAPIENTRYP PFNEGLDEBUGMESSAGECONTROLKHRPROC) 
(EGLDEBUGPROCKHR callback, const EGLAttrib *attrib_list);
+typedef EGLBoolean (EGLAPIENTRYP PFNEGLQUERYDEBUGKHRPROC) (EGLint attribute, 
EGLAttrib *value);
+typedef EGLint (EGLAPIENTRYP PFNEGLLABELOBJECTKHRPROC) (EGLDisplay display, 
EGLenum objectType, EGLObjectKHR object, EGLLabelKHR label);
+#ifdef EGL_EGLEXT_PROTOTYPES
+EGLAPI EGLint EGLAPIENTRY eglDebugMessageControlKHR (EGLDEBUGPROCKHR callback, 
const EGLAttrib *attrib_list);
+EGLAPI EGLBoolean EGLAPIENTRY eglQueryDebugKHR (EGLint attribute, EGLAttrib 
*value);
+EGLAPI EGLint EGLAPIENTRY eglLabelObjectKHR (EGLDisplay display, EGLenum 
objectType, EGLObjectKHR object, EGLLabelKHR label);
+#endif
+#endif /* EGL_KHR_debug */
+
 #ifndef EGL_KHR_fence_sync
 #define EGL_KHR_fence_sync 1
 typedef khronos_utime_nanoseconds_t EGLTimeKHR;
@@ -223,6 +250,16 @@ EGLAPI EGLBoolean EGLAPIENTRY eglQuerySurface64KHR 
(EGLDisplay dpy, EGLSurface s
 #endif
 #endif /* EGL_KHR_lock_surface3 */
 
+#ifndef EGL_KHR_mutable_render_buffer
+#define EGL_KHR_mutable_render_buffer 1
+#define EGL_MUTABLE_RENDER_BUFFER_BIT_KHR 0x1000
+#endif /* EGL_KHR_mutable_render_buffer */
+
+#ifndef EGL_KHR_no_config_context
+#define EGL_KHR_no_config_context 1
+#define EGL_NO_CONFIG_KHR ((EGLConfig)0)
+#endif /* EGL_KHR_no_config_context */
+
 #ifndef EGL_KHR_partial_update
 #define EGL_KHR_partial_update 1
 #define EGL_BUFFER_AGE_KHR0x313D
@@ -402,11 +439,28 @@ EGLAPI void EGLAPIENTRY eglSetBlobCacheFuncsANDROID 
(EGLDisplay dpy, EGLSetBlobF
 #endif
 #endif /* EGL_ANDROID_blob_cache */
 
+#ifndef EGL_ANDROID_create_native_client_buffer
+#define EGL_ANDROID_create_native_client_buffer 1
+#define EGL_NATIVE_BUFFER_USAGE_ANDROID   0x3143
+#define EGL_NATIVE_BUFFER_USAGE_PROTECTED_BIT_ANDROID 0x0001
+#define EGL_NATIVE_BUFFER_USAGE_RENDERBUFFER_BIT_ANDROID 0x0002
+#define EGL_NATIVE_BUFFER_USAGE_TEXTURE_BIT_ANDROID 0x0004
+typedef EGLClientBuffer (EGLAPIENTRYP 
PFNEGLCREATENATIVECLIENTBUFFERANDROIDPROC) (const EGLint *attrib_list);
+#ifdef EGL_EGLEXT_PROTOTYPES
+EGLAPI EGLClientBuffer EGLAPIENTRY eglCreateNativeClientBufferANDROID (const 
EGLint *attrib_list);
+#endif
+#endif /* EGL_ANDROID_create_native_client_buffer */
+
 #ifndef EGL_ANDROID_framebuffer_target
 #define EGL_ANDROID_framebuffer_target 1
 #define EGL_FRAMEBUFFER_TARGET_ANDROID0x3147
 #endif /* EGL_ANDROID_framebuffer_target */
 
+#ifndef EGL_ANDROID_front_buffer_auto_refresh
+#define EGL_ANDROID_front_buffer_auto_refresh 1
+#define EGL_FRONT_BUFFER_AUTO_REFRESH_ANDROID 0x314C
+#endif /* EGL_ANDROID_front_buffer_auto_refresh */
+
 #ifndef EGL_ANDROID_image_native_buffer
 #define EGL_ANDROID_image_native_buffer 1
 #define EGL_NATIVE_BUFFER_ANDROID 0x3140
@@ -424,6 +478,15 @@ EGLAPI EGLint EGLAPIENTRY eglDupNativeFenceFDANDROID 
(EGLDisplay dpy, EGLSyncKHR
 #endif
 #endif /* 

[Mesa-dev] [PATCH 14/14] egl: Implement EGL_KHR_debug

[Adam Jackson]

From: Kyle Brenneman 

Wire up the debug entrypoints to EGL dispatch, and add the extension
string to the client extension list.
---
 src/egl/main/eglapi.c | 140 ++
 src/egl/main/eglglobals.c |   3 +-
 2 files changed, 142 insertions(+), 1 deletion(-)

diff --git a/src/egl/main/eglapi.c b/src/egl/main/eglapi.c
index 0a6ebe7..6b0fd2e 100644
--- a/src/egl/main/eglapi.c
+++ b/src/egl/main/eglapi.c
@@ -1987,6 +1987,143 @@ eglExportDMABUFImageMESA(EGLDisplay dpy, EGLImage image,
RETURN_EGL_EVAL(disp, ret);
 }
 
+static EGLint EGLAPIENTRY
+eglLabelObjectKHR(EGLDisplay dpy, EGLenum objectType, EGLObjectKHR object,
+ EGLLabelKHR label)
+{
+   _EGL_FUNC_START(NULL, EGL_NONE, NULL, EGL_BAD_ALLOC);
+
+   if (objectType == EGL_OBJECT_THREAD_KHR) {
+  _EGLThreadInfo *t = _eglGetCurrentThread();
+
+  if (!_eglIsCurrentThreadDummy()) {
+ t->Label = label;
+ return EGL_SUCCESS;
+  } else {
+ _eglDebugReportFull(EGL_BAD_ALLOC, __func__, __func__,
+   EGL_DEBUG_MSG_CRITICAL_KHR, NULL, NULL);
+ return EGL_BAD_ALLOC;
+  }
+   } else {
+  _EGLDisplay *disp = _eglLookupDisplay(dpy);
+
+  if (disp == NULL) {
+ _eglError(EGL_BAD_DISPLAY, "eglLabelObjectKHR");
+ return EGL_BAD_DISPLAY;
+  }
+
+  if (objectType == EGL_OBJECT_DISPLAY_KHR) {
+ if (dpy != (EGLDisplay) object) {
+_eglError(EGL_BAD_PARAMETER, "eglLabelObjectKHR");
+return EGL_BAD_PARAMETER;
+ }
+ disp->Label = label;
+ return EGL_SUCCESS;
+  } else {
+ _EGLResourceType type;
+
+ switch (objectType)
+ {
+case EGL_OBJECT_CONTEXT_KHR:
+   type = _EGL_RESOURCE_CONTEXT;
+   break;
+case EGL_OBJECT_SURFACE_KHR:
+   type = _EGL_RESOURCE_SURFACE;
+   break;
+case EGL_OBJECT_IMAGE_KHR:
+   type = _EGL_RESOURCE_IMAGE;
+   break;
+case EGL_OBJECT_SYNC_KHR:
+   type = _EGL_RESOURCE_SYNC;
+   break;
+case EGL_OBJECT_STREAM_KHR:
+default:
+_eglError(EGL_BAD_PARAMETER, "eglLabelObjectKHR");
+   return EGL_BAD_PARAMETER;
+ }
+
+ if (_eglCheckResource(object, type, disp)) {
+_EGLResource *res = (_EGLResource *) object;
+res->Label = label;
+return EGL_SUCCESS;
+ } else {
+_eglError(EGL_BAD_PARAMETER, "eglLabelObjectKHR");
+return EGL_BAD_PARAMETER;
+ }
+  }
+   }
+}
+
+static EGLint
+eglDebugMessageControlKHR(EGLDEBUGPROCKHR callback,
+ const EGLAttrib *attrib_list)
+{
+   unsigned int newEnabled;
+
+   _EGL_FUNC_START(NULL, EGL_NONE, NULL, EGL_BAD_ALLOC);
+
+   mtx_lock(_eglGlobal.Mutex);
+
+   newEnabled = _eglGlobal.debugTypesEnabled;
+   if (attrib_list != NULL) {
+  int i;
+
+  for (i = 0; attrib_list[i] != EGL_NONE; i += 2) {
+ if (attrib_list[i] >= EGL_DEBUG_MSG_CRITICAL_KHR &&
+   attrib_list[i] <= EGL_DEBUG_MSG_INFO_KHR) {
+if (attrib_list[i + 1]) {
+   newEnabled |= DebugBitFromType(attrib_list[i]);
+} else {
+   newEnabled &= ~DebugBitFromType(attrib_list[i]);
+}
+ } else {
+// On error, set the last error code, call the current
+// debug callback, and return the error code.
+mtx_unlock(_eglGlobal.Mutex);
+_eglReportError(EGL_BAD_ATTRIBUTE, NULL,
+  "Invalid attribute 0x%04lx", (unsigned long) attrib_list[i]);
+return EGL_BAD_ATTRIBUTE;
+ }
+  }
+   }
+
+   if (callback != NULL) {
+  _eglGlobal.debugCallback = callback;
+  _eglGlobal.debugTypesEnabled = newEnabled;
+   } else {
+  _eglGlobal.debugCallback = NULL;
+  _eglGlobal.debugTypesEnabled = _EGL_DEBUG_BIT_CRITICAL | 
_EGL_DEBUG_BIT_ERROR;
+   }
+
+   mtx_unlock(_eglGlobal.Mutex);
+   return EGL_SUCCESS;
+}
+
+static EGLBoolean
+eglQueryDebugKHR(EGLint attribute, EGLAttrib *value)
+{
+   _EGL_FUNC_START(NULL, EGL_NONE, NULL, EGL_BAD_ALLOC);
+
+   mtx_lock(_eglGlobal.Mutex);
+   if (attribute >= EGL_DEBUG_MSG_CRITICAL_KHR &&
+ attribute <= EGL_DEBUG_MSG_INFO_KHR) {
+  if (_eglGlobal.debugTypesEnabled & DebugBitFromType(attribute)) {
+ *value = EGL_TRUE;
+  } else {
+ *value = EGL_FALSE;
+  }
+   } else if (attribute == EGL_DEBUG_CALLBACK_KHR) {
+  *value = (EGLAttrib) _eglGlobal.debugCallback;
+   } else {
+  mtx_unlock(_eglGlobal.Mutex);
+  _eglReportError(EGL_BAD_ATTRIBUTE, NULL,
+  "Invalid attribute 0x%04lx", (unsigned long) attribute);
+  return EGL_FALSE;
+   }
+   mtx_unlock(_eglGlobal.Mutex);
+   return EGL_TRUE;
+}
+
 __eglMustCastToProperFunctionPointerType EGLAPIENTRY
 

[Mesa-dev] [PATCH 08/14] egl: Factor out _eglCreateImageCommon

[Adam Jackson]

From: Kyle Brenneman 

---
 src/egl/main/eglapi.c | 16 
 1 file changed, 12 insertions(+), 4 deletions(-)

diff --git a/src/egl/main/eglapi.c b/src/egl/main/eglapi.c
index a74e5e4..658d0d7 100644
--- a/src/egl/main/eglapi.c
+++ b/src/egl/main/eglapi.c
@@ -1309,11 +1309,10 @@ eglReleaseThread(void)
 }
 
 
-static EGLImage EGLAPIENTRY
-eglCreateImageKHR(EGLDisplay dpy, EGLContext ctx, EGLenum target,
+static EGLImage
+_eglCreateImageCommon(_EGLDisplay *disp, EGLContext ctx, EGLenum target,
   EGLClientBuffer buffer, const EGLint *attr_list)
 {
-   _EGLDisplay *disp = _eglLockDisplay(dpy);
_EGLContext *context = _eglLookupContext(ctx, disp);
_EGLDriver *drv;
_EGLImage *img;
@@ -1337,18 +1336,27 @@ eglCreateImageKHR(EGLDisplay dpy, EGLContext ctx, 
EGLenum target,
RETURN_EGL_EVAL(disp, ret);
 }
 
+static EGLImage EGLAPIENTRY
+eglCreateImageKHR(EGLDisplay dpy, EGLContext ctx, EGLenum target,
+  EGLClientBuffer buffer, const EGLint *attr_list)
+{
+   _EGLDisplay *disp = _eglLockDisplay(dpy);
+   return _eglCreateImageCommon(disp, ctx, target, buffer, attr_list);
+}
+
 
 EGLImage EGLAPIENTRY
 eglCreateImage(EGLDisplay dpy, EGLContext ctx, EGLenum target,
EGLClientBuffer buffer, const EGLAttrib *attr_list)
 {
+   _EGLDisplay *disp = _eglLockDisplay(dpy);
EGLImage image;
EGLint *int_attribs = _eglConvertAttribsToInt(attr_list);
 
if (attr_list && !int_attribs)
   RETURN_EGL_ERROR(NULL, EGL_BAD_ALLOC, EGL_NO_IMAGE);
 
-   image = eglCreateImageKHR(dpy, ctx, target, buffer, int_attribs);
+   image = _eglCreateImageCommon(disp, ctx, target, buffer, int_attribs);
free(int_attribs);
return image;
 }
-- 
2.9.3

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[Mesa-dev] [PATCH 09/14] egl: Lock the display in _eglCreateSync's callers

[Adam Jackson]

From: Kyle Brenneman 

---
 src/egl/main/eglapi.c | 14 --
 1 file changed, 8 insertions(+), 6 deletions(-)

diff --git a/src/egl/main/eglapi.c b/src/egl/main/eglapi.c
index 658d0d7..dc61d5f 100644
--- a/src/egl/main/eglapi.c
+++ b/src/egl/main/eglapi.c
@@ -1384,11 +1384,10 @@ eglDestroyImage(EGLDisplay dpy, EGLImage image)
 
 
 static EGLSync
-_eglCreateSync(EGLDisplay dpy, EGLenum type, const EGLint *attrib_list,
+_eglCreateSync(_EGLDisplay *disp, EGLenum type, const EGLint *attrib_list,
const EGLAttrib *attrib_list64, EGLBoolean is64,
EGLenum invalid_type_error)
 {
-   _EGLDisplay *disp = _eglLockDisplay(dpy);
_EGLContext *ctx = _eglGetCurrentContext();
_EGLDriver *drv;
_EGLSync *sync;
@@ -1400,7 +1399,7 @@ _eglCreateSync(EGLDisplay dpy, EGLenum type, const EGLint 
*attrib_list,
   RETURN_EGL_EVAL(disp, EGL_NO_SYNC_KHR);
 
/* return an error if the client API doesn't support GL_OES_EGL_sync */
-   if (!ctx || ctx->Resource.Display != dpy ||
+   if (!ctx || ctx->Resource.Display != disp ||
ctx->ClientAPI != EGL_OPENGL_ES_API)
   RETURN_EGL_ERROR(disp, EGL_BAD_MATCH, EGL_NO_SYNC_KHR);
 
@@ -1431,7 +1430,8 @@ _eglCreateSync(EGLDisplay dpy, EGLenum type, const EGLint 
*attrib_list,
 static EGLSync EGLAPIENTRY
 eglCreateSyncKHR(EGLDisplay dpy, EGLenum type, const EGLint *attrib_list)
 {
-   return _eglCreateSync(dpy, type, attrib_list, NULL, EGL_FALSE,
+   _EGLDisplay *disp = _eglLockDisplay(dpy);
+   return _eglCreateSync(disp, type, attrib_list, NULL, EGL_FALSE,
  EGL_BAD_ATTRIBUTE);
 }
 
@@ -1439,7 +1439,8 @@ eglCreateSyncKHR(EGLDisplay dpy, EGLenum type, const 
EGLint *attrib_list)
 static EGLSync EGLAPIENTRY
 eglCreateSync64KHR(EGLDisplay dpy, EGLenum type, const EGLAttrib *attrib_list)
 {
-   return _eglCreateSync(dpy, type, NULL, attrib_list, EGL_TRUE,
+   _EGLDisplay *disp = _eglLockDisplay(dpy);
+   return _eglCreateSync(disp, type, NULL, attrib_list, EGL_TRUE,
  EGL_BAD_ATTRIBUTE);
 }
 
@@ -1447,7 +1448,8 @@ eglCreateSync64KHR(EGLDisplay dpy, EGLenum type, const 
EGLAttrib *attrib_list)
 EGLSync EGLAPIENTRY
 eglCreateSync(EGLDisplay dpy, EGLenum type, const EGLAttrib *attrib_list)
 {
-   return _eglCreateSync(dpy, type, NULL, attrib_list, EGL_TRUE,
+   _EGLDisplay *disp = _eglLockDisplay(dpy);
+   return _eglCreateSync(disp, type, NULL, attrib_list, EGL_TRUE,
  EGL_BAD_PARAMETER);
 }
 
-- 
2.9.3

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[Mesa-dev] [PATCH 03/14] egl: Fix typo

[Adam Jackson]

From: Kyle Brenneman 

---
 src/egl/main/eglglobals.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/egl/main/eglglobals.c b/src/egl/main/eglglobals.c
index 938d953..04bb5ba 100644
--- a/src/egl/main/eglglobals.c
+++ b/src/egl/main/eglglobals.c
@@ -50,7 +50,7 @@ struct _egl_global _eglGlobal =
   _eglFiniDisplay
},
 
-   /* ClientExtensionsString */
+   /* ClientExtensionString */
"EGL_EXT_client_extensions"
" EGL_EXT_platform_base"
" EGL_EXT_platform_wayland"
-- 
2.9.3

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[Mesa-dev] [PATCH 05/14] egl: Use _eglCreateWindowSurfaceCommon consistently

[Adam Jackson]

From: Kyle Brenneman 

This moves the native window fixup to a helper function so we don't
repeat ourselves.
---
 src/egl/main/eglapi.c | 28 ++--
 1 file changed, 18 insertions(+), 10 deletions(-)

diff --git a/src/egl/main/eglapi.c b/src/egl/main/eglapi.c
index df355a5..dd2b4cc 100644
--- a/src/egl/main/eglapi.c
+++ b/src/egl/main/eglapi.c
@@ -762,14 +762,9 @@ eglCreateWindowSurface(EGLDisplay dpy, EGLConfig config,
 attrib_list);
 }
 
-
-static EGLSurface EGLAPIENTRY
-eglCreatePlatformWindowSurfaceEXT(EGLDisplay dpy, EGLConfig config,
-  void *native_window,
-  const EGLint *attrib_list)
+static void *
+fixupNativeWindow(_EGLDisplay *disp, void *native_window)
 {
-   _EGLDisplay *disp = _eglLockDisplay(dpy);
-
 #ifdef HAVE_X11_PLATFORM
if (disp->Platform == _EGL_PLATFORM_X11 && native_window != NULL) {
   /* The `native_window` parameter for the X11 platform differs between
@@ -779,9 +774,20 @@ eglCreatePlatformWindowSurfaceEXT(EGLDisplay dpy, 
EGLConfig config,
* `Window*`.  Convert `Window*` to `Window` because that's what
* dri2_x11_create_window_surface() expects.
*/
-  native_window = (void*) (* (Window*) native_window);
+  return (void *)(* (Window*) native_window);
}
 #endif
+   return native_window;
+}
+
+static EGLSurface EGLAPIENTRY
+eglCreatePlatformWindowSurfaceEXT(EGLDisplay dpy, EGLConfig config,
+  void *native_window,
+  const EGLint *attrib_list)
+{
+   _EGLDisplay *disp = _eglLockDisplay(dpy);
+
+   native_window = fixupNativeWindow(disp, native_window);
 
return _eglCreateWindowSurfaceCommon(disp, config, native_window,
 attrib_list);
@@ -793,14 +799,16 @@ eglCreatePlatformWindowSurface(EGLDisplay dpy, EGLConfig 
config,
void *native_window,
const EGLAttrib *attrib_list)
 {
+   _EGLDisplay *disp = _eglLockDisplay(dpy);
EGLSurface surface;
EGLint *int_attribs = _eglConvertAttribsToInt(attrib_list);
 
if (attrib_list && !int_attribs)
   RETURN_EGL_ERROR(NULL, EGL_BAD_ALLOC, EGL_NO_SURFACE);
 
-   surface = eglCreatePlatformWindowSurfaceEXT(dpy, config, native_window,
-   int_attribs);
+   native_window = fixupNativeWindow(disp, native_window);
+   surface = _eglCreateWindowSurfaceCommon(disp, config, native_window,
+   int_attribs);
free(int_attribs);
return surface;
 }
-- 
2.9.3

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[Mesa-dev] [PATCH 10/14] egl: Factor out _eglWaitSyncCommon

[Adam Jackson]

From: Kyle Brenneman 

---
 src/egl/main/eglapi.c | 18 +-
 1 file changed, 13 insertions(+), 5 deletions(-)

diff --git a/src/egl/main/eglapi.c b/src/egl/main/eglapi.c
index dc61d5f..c285c20 100644
--- a/src/egl/main/eglapi.c
+++ b/src/egl/main/eglapi.c
@@ -1509,11 +1509,9 @@ eglClientWaitSync(EGLDisplay dpy, EGLSync sync, EGLint 
flags, EGLTime timeout)
 }
 
 
-static EGLint EGLAPIENTRY
-eglWaitSyncKHR(EGLDisplay dpy, EGLSync sync, EGLint flags)
+static EGLint
+_eglWaitSyncCommon(_EGLDisplay *disp, _EGLSync *s, EGLint flags)
 {
-   _EGLDisplay *disp = _eglLockDisplay(dpy);
-   _EGLSync *s = _eglLookupSync(sync, disp);
_EGLContext *ctx = _eglGetCurrentContext();
_EGLDriver *drv;
EGLint ret;
@@ -1534,6 +1532,14 @@ eglWaitSyncKHR(EGLDisplay dpy, EGLSync sync, EGLint 
flags)
RETURN_EGL_EVAL(disp, ret);
 }
 
+static EGLint EGLAPIENTRY
+eglWaitSyncKHR(EGLDisplay dpy, EGLSync sync, EGLint flags)
+{
+   _EGLDisplay *disp = _eglLockDisplay(dpy);
+   _EGLSync *s = _eglLookupSync(sync, disp);
+   return _eglWaitSyncCommon(disp, s, flags);
+}
+
 
 EGLBoolean EGLAPIENTRY
 eglWaitSync(EGLDisplay dpy, EGLSync sync, EGLint flags)
@@ -1542,7 +1548,9 @@ eglWaitSync(EGLDisplay dpy, EGLSync sync, EGLint flags)
 * EGLBoolean. In both cases, the return values can only be EGL_FALSE and
 * EGL_TRUE.
 */
-   return eglWaitSyncKHR(dpy, sync, flags);
+   _EGLDisplay *disp = _eglLockDisplay(dpy);
+   _EGLSync *s = _eglLookupSync(sync, disp);
+   return _eglWaitSyncCommon(disp, s, flags);
 }
 
 
-- 
2.9.3

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[Mesa-dev] [PATCH 02/14] egl: Tear down images and syncs at eglTerminate

[Adam Jackson]

Signed-off-by: Adam Jackson 
---
 src/egl/main/egldisplay.c | 22 ++
 1 file changed, 22 insertions(+)

diff --git a/src/egl/main/egldisplay.c b/src/egl/main/egldisplay.c
index bbc3063..3d4eb81 100644
--- a/src/egl/main/egldisplay.c
+++ b/src/egl/main/egldisplay.c
@@ -44,6 +44,8 @@
 #include "egldriver.h"
 #include "eglglobals.h"
 #include "egllog.h"
+#include "eglimage.h"
+#include "eglsync.h"
 
 /* Includes for _eglNativePlatformDetectNativeDisplay */
 #ifdef HAVE_MINCORE
@@ -300,6 +302,26 @@ _eglReleaseDisplayResources(_EGLDriver *drv, _EGLDisplay 
*display)
   drv->API.DestroySurface(drv, display, surf);
}
assert(!display->ResourceLists[_EGL_RESOURCE_SURFACE]);
+
+   list = display->ResourceLists[_EGL_RESOURCE_IMAGE];
+   while (list) {
+  _EGLImage *image = (_EGLImage *) list;
+  list = list->Next;
+
+  _eglUnlinkImage(image);
+  drv->API.DestroyImageKHR(drv, display, image);
+   }
+   assert(!display->ResourceLists[_EGL_RESOURCE_IMAGE]);
+
+   list = display->ResourceLists[_EGL_RESOURCE_SYNC];
+   while (list) {
+  _EGLSync *sync = (_EGLSync *) list;
+  list = list->Next;
+
+  _eglUnlinkSync(sync);
+  drv->API.DestroySyncKHR(drv, display, sync);
+   }
+   assert(!display->ResourceLists[_EGL_RESOURCE_SYNC]);
 }
 
 
-- 
2.9.3

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[Mesa-dev] [PATCH 11/14] egl: Factor out _eglGetSyncAttribCommon

[Adam Jackson]

From: Kyle Brenneman 

---
 src/egl/main/eglapi.c | 18 +-
 1 file changed, 13 insertions(+), 5 deletions(-)

diff --git a/src/egl/main/eglapi.c b/src/egl/main/eglapi.c
index c285c20..0477ad9 100644
--- a/src/egl/main/eglapi.c
+++ b/src/egl/main/eglapi.c
@@ -1570,11 +1570,9 @@ eglSignalSyncKHR(EGLDisplay dpy, EGLSync sync, EGLenum 
mode)
 }
 
 
-EGLBoolean EGLAPIENTRY
-eglGetSyncAttrib(EGLDisplay dpy, EGLSync sync, EGLint attribute, EGLAttrib 
*value)
+static EGLBoolean
+_eglGetSyncAttribCommon(_EGLDisplay *disp, _EGLSync *s, EGLint attribute, 
EGLAttrib *value)
 {
-   _EGLDisplay *disp = _eglLockDisplay(dpy);
-   _EGLSync *s = _eglLookupSync(sync, disp);
_EGLDriver *drv;
EGLBoolean ret;
 
@@ -1586,10 +1584,20 @@ eglGetSyncAttrib(EGLDisplay dpy, EGLSync sync, EGLint 
attribute, EGLAttrib *valu
RETURN_EGL_EVAL(disp, ret);
 }
 
+EGLBoolean EGLAPIENTRY
+eglGetSyncAttrib(EGLDisplay dpy, EGLSync sync, EGLint attribute, EGLAttrib 
*value)
+{
+   _EGLDisplay *disp = _eglLockDisplay(dpy);
+   _EGLSync *s = _eglLookupSync(sync, disp);
+   return _eglGetSyncAttribCommon(disp, s, attribute, value);
+}
+
 
 static EGLBoolean EGLAPIENTRY
 eglGetSyncAttribKHR(EGLDisplay dpy, EGLSync sync, EGLint attribute, EGLint 
*value)
 {
+   _EGLDisplay *disp = _eglLockDisplay(dpy);
+   _EGLSync *s = _eglLookupSync(sync, disp);
EGLAttrib attrib;
EGLBoolean result;
 
@@ -1597,7 +1605,7 @@ eglGetSyncAttribKHR(EGLDisplay dpy, EGLSync sync, EGLint 
attribute, EGLint *valu
   RETURN_EGL_ERROR(NULL, EGL_BAD_PARAMETER, EGL_FALSE);
 
attrib = *value;
-   result = eglGetSyncAttrib(dpy, sync, attribute, );
+   result = _eglGetSyncAttribCommon(disp, s, attribute, );
 
/* The EGL_KHR_fence_sync spec says this about eglGetSyncAttribKHR:
 *
-- 
2.9.3

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[Mesa-dev] [PATCH 12/14] egl: Add storage for EGL_KHR_debug's state to EGL objects

[Adam Jackson]

From: Kyle Brenneman 

---
 src/egl/main/eglcurrent.c |  3 +--
 src/egl/main/eglcurrent.h |  8 
 src/egl/main/egldisplay.h |  4 
 src/egl/main/eglglobals.c |  5 -
 src/egl/main/eglglobals.h | 10 ++
 5 files changed, 27 insertions(+), 3 deletions(-)

diff --git a/src/egl/main/eglcurrent.c b/src/egl/main/eglcurrent.c
index 2a225bc..f093bec 100644
--- a/src/egl/main/eglcurrent.c
+++ b/src/egl/main/eglcurrent.c
@@ -35,10 +35,9 @@
 #include "eglcurrent.h"
 #include "eglglobals.h"
 
-
 /* This should be kept in sync with _eglInitThreadInfo() */
 #define _EGL_THREAD_INFO_INITIALIZER \
-   { EGL_SUCCESS, NULL, 0 }
+   { EGL_SUCCESS, NULL, 0, NULL, NULL, NULL }
 
 /* a fallback thread info to guarantee that every thread always has one */
 static _EGLThreadInfo dummy_thread = _EGL_THREAD_INFO_INITIALIZER;
diff --git a/src/egl/main/eglcurrent.h b/src/egl/main/eglcurrent.h
index b922435..b2638fd 100644
--- a/src/egl/main/eglcurrent.h
+++ b/src/egl/main/eglcurrent.h
@@ -54,6 +54,14 @@ struct _egl_thread_info
EGLint LastError;
_EGLContext *CurrentContext;
EGLenum CurrentAPI;
+   EGLLabelKHR Label;
+
+   /**
+* The name of the EGL function that's being called at the moment. This is
+* used to report the function name to the EGL_KHR_debug callback.
+*/
+   const char *CurrentFuncName;
+   EGLLabelKHR CurrentObjectLabel;
 };
 
 
diff --git a/src/egl/main/egldisplay.h b/src/egl/main/egldisplay.h
index 6f3340e..22fb5c8 100644
--- a/src/egl/main/egldisplay.h
+++ b/src/egl/main/egldisplay.h
@@ -79,6 +79,8 @@ struct _egl_resource
EGLBoolean IsLinked;
EGLint RefCount;
 
+   EGLLabelKHR Label;
+
/* used to link resources of the same type */
_EGLResource *Next;
 };
@@ -165,6 +167,8 @@ struct _egl_display
 
/* lists of resources */
_EGLResource *ResourceLists[_EGL_NUM_RESOURCES];
+
+   EGLLabelKHR Label;
 };
 
 
diff --git a/src/egl/main/eglglobals.c b/src/egl/main/eglglobals.c
index 04bb5ba..dca5c21 100644
--- a/src/egl/main/eglglobals.c
+++ b/src/egl/main/eglglobals.c
@@ -56,7 +56,10 @@ struct _egl_global _eglGlobal =
" EGL_EXT_platform_wayland"
" EGL_EXT_platform_x11"
" EGL_KHR_client_get_all_proc_addresses"
-   " EGL_MESA_platform_gbm"
+   " EGL_MESA_platform_gbm",
+
+   NULL, /* debugCallback */
+   _EGL_DEBUG_BIT_CRITICAL | _EGL_DEBUG_BIT_ERROR, /* debugTypesEnabled */
 };
 
 
diff --git a/src/egl/main/eglglobals.h b/src/egl/main/eglglobals.h
index ae1b75b..dfa3577 100644
--- a/src/egl/main/eglglobals.h
+++ b/src/egl/main/eglglobals.h
@@ -36,6 +36,13 @@
 
 #include "egltypedefs.h"
 
+enum
+{
+_EGL_DEBUG_BIT_CRITICAL = 0x1,
+_EGL_DEBUG_BIT_ERROR = 0x2,
+_EGL_DEBUG_BIT_WARN = 0x4,
+_EGL_DEBUG_BIT_INFO = 0x8,
+};
 
 /**
  * Global library data
@@ -51,6 +58,9 @@ struct _egl_global
void (*AtExitCalls[10])(void);
 
const char *ClientExtensionString;
+
+   EGLDEBUGPROCKHR debugCallback;
+   unsigned int debugTypesEnabled;
 };
 
 
-- 
2.9.3

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[Mesa-dev] [PATCH 13/14] egl: Track EGL_KHR_debug state when going through EGL API calls

[Adam Jackson]

From: Kyle Brenneman 

This decorates every EGL entrypoint with _EGL_FUNC_START, which records
the function name and primary dispatch object label in the current
thread state. It also adds debug report functions and calls them when
appropriate.

This would be useful enough for debugging on its own, if the user set a
breakpoint when the report function was called. We will also need this
state tracked in order to expose EGL_KHR_debug.
---
 src/egl/main/eglapi.c | 161 +++---
 src/egl/main/eglcurrent.c |  89 -
 src/egl/main/eglcurrent.h |  22 +++
 src/egl/main/eglglobals.h |   5 ++
 4 files changed, 266 insertions(+), 11 deletions(-)

diff --git a/src/egl/main/eglapi.c b/src/egl/main/eglapi.c
index 0477ad9..0a6ebe7 100644
--- a/src/egl/main/eglapi.c
+++ b/src/egl/main/eglapi.c
@@ -250,6 +250,46 @@ _eglUnlockDisplay(_EGLDisplay *dpy)
mtx_unlock(>Mutex);
 }
 
+static EGLBoolean
+_eglSetFuncName(const char *funcName, _EGLDisplay *disp, EGLenum objectType, 
_EGLResource *object)
+{
+   _EGLThreadInfo *thr = _eglGetCurrentThread();
+   if (!_eglIsCurrentThreadDummy()) {
+  thr->CurrentFuncName = funcName;
+  thr->CurrentObjectLabel = NULL;
+
+  if (objectType == EGL_OBJECT_THREAD_KHR) {
+ thr->CurrentObjectLabel = thr->Label;
+  } else if (objectType == EGL_OBJECT_DISPLAY_KHR) {
+ if (disp != NULL) {
+thr->CurrentObjectLabel = disp->Label;
+ }
+  } else {
+ /*
+  * Everything else will either be NULL or a valid _EGLResource
+  * pointer.
+  */
+ if (object != NULL) {
+thr->CurrentObjectLabel = object->Label;
+ }
+  }
+
+  return EGL_TRUE;
+   }
+
+   _eglDebugReportFull(EGL_BAD_ALLOC, funcName, funcName,
+  EGL_DEBUG_MSG_CRITICAL_KHR, NULL, NULL);
+   return EGL_FALSE;
+}
+
+#define _EGL_FUNC_START(disp, objectType, object, ret) \
+   do { \
+  if (!_eglSetFuncName(__func__, disp, objectType, (_EGLResource *) 
object)) { \
+ if (disp) \
+_eglUnlockDisplay(disp);   \
+ return ret; \
+  } \
+   } while(0)
 
 static EGLint *
 _eglConvertAttribsToInt(const EGLAttrib *attr_list)
@@ -287,6 +327,8 @@ eglGetDisplay(EGLNativeDisplayType nativeDisplay)
_EGLDisplay *dpy;
void *native_display_ptr;
 
+   _EGL_FUNC_START(NULL, EGL_OBJECT_THREAD_KHR, NULL, EGL_NO_DISPLAY);
+
STATIC_ASSERT(sizeof(void*) == sizeof(nativeDisplay));
native_display_ptr = (void*) nativeDisplay;
 
@@ -330,6 +372,7 @@ static EGLDisplay EGLAPIENTRY
 eglGetPlatformDisplayEXT(EGLenum platform, void *native_display,
  const EGLint *attrib_list)
 {
+   _EGL_FUNC_START(NULL, EGL_OBJECT_THREAD_KHR, NULL, EGL_NO_DISPLAY);
return _eglGetPlatformDisplayCommon(platform, native_display, attrib_list);
 }
 
@@ -340,6 +383,8 @@ eglGetPlatformDisplay(EGLenum platform, void 
*native_display,
EGLDisplay display;
EGLint *int_attribs;
 
+   _EGL_FUNC_START(NULL, EGL_OBJECT_THREAD_KHR, NULL, EGL_NO_DISPLAY);
+
int_attribs = _eglConvertAttribsToInt(attrib_list);
if (attrib_list && !int_attribs)
   RETURN_EGL_ERROR(NULL, EGL_BAD_ALLOC, NULL);
@@ -483,6 +528,8 @@ eglInitialize(EGLDisplay dpy, EGLint *major, EGLint *minor)
 {
_EGLDisplay *disp = _eglLockDisplay(dpy);
 
+   _EGL_FUNC_START(disp, EGL_OBJECT_DISPLAY_KHR, NULL, EGL_FALSE);
+
if (!disp)
   RETURN_EGL_ERROR(NULL, EGL_BAD_DISPLAY, EGL_FALSE);
 
@@ -533,6 +580,8 @@ eglTerminate(EGLDisplay dpy)
 {
_EGLDisplay *disp = _eglLockDisplay(dpy);
 
+   _EGL_FUNC_START(disp, EGL_OBJECT_DISPLAY_KHR, NULL, EGL_FALSE);
+
if (!disp)
   RETURN_EGL_ERROR(NULL, EGL_BAD_DISPLAY, EGL_FALSE);
 
@@ -560,6 +609,7 @@ eglQueryString(EGLDisplay dpy, EGLint name)
}
 
disp = _eglLockDisplay(dpy);
+   _EGL_FUNC_START(disp, EGL_OBJECT_DISPLAY_KHR, NULL, NULL);
_EGL_CHECK_DISPLAY(disp, NULL, drv);
 
switch (name) {
@@ -585,6 +635,8 @@ eglGetConfigs(EGLDisplay dpy, EGLConfig *configs,
_EGLDriver *drv;
EGLBoolean ret;
 
+   _EGL_FUNC_START(disp, EGL_OBJECT_DISPLAY_KHR, NULL, EGL_FALSE);
+
_EGL_CHECK_DISPLAY(disp, EGL_FALSE, drv);
ret = drv->API.GetConfigs(drv, disp, configs, config_size, num_config);
 
@@ -600,6 +652,8 @@ eglChooseConfig(EGLDisplay dpy, const EGLint *attrib_list, 
EGLConfig *configs,
_EGLDriver *drv;
EGLBoolean ret;
 
+   _EGL_FUNC_START(disp, EGL_OBJECT_DISPLAY_KHR, NULL, EGL_FALSE);
+
_EGL_CHECK_DISPLAY(disp, EGL_FALSE, drv);
ret = drv->API.ChooseConfig(drv, disp, attrib_list, configs,
 config_size, num_config);
@@ -617,6 +671,8 @@ eglGetConfigAttrib(EGLDisplay dpy, EGLConfig config,
_EGLDriver *drv;
EGLBoolean ret;
 
+   _EGL_FUNC_START(disp, EGL_OBJECT_DISPLAY_KHR, NULL, EGL_FALSE);
+
_EGL_CHECK_CONFIG(disp, conf, EGL_FALSE, drv);

[Mesa-dev] [PATCH 07/14] egl: Factor out _eglWaitClientCommon

[Adam Jackson]

From: Kyle Brenneman 

---
 src/egl/main/eglapi.c | 11 ---
 1 file changed, 8 insertions(+), 3 deletions(-)

diff --git a/src/egl/main/eglapi.c b/src/egl/main/eglapi.c
index fac2d18..a74e5e4 100644
--- a/src/egl/main/eglapi.c
+++ b/src/egl/main/eglapi.c
@@ -1081,8 +1081,8 @@ eglCopyBuffers(EGLDisplay dpy, EGLSurface surface, 
EGLNativePixmapType target)
 }
 
 
-EGLBoolean EGLAPIENTRY
-eglWaitClient(void)
+static EGLBoolean
+_eglWaitClientCommon(void)
 {
_EGLContext *ctx = _eglGetCurrentContext();
_EGLDisplay *disp;
@@ -1108,12 +1108,17 @@ eglWaitClient(void)
RETURN_EGL_EVAL(disp, ret);
 }
 
+EGLBoolean EGLAPIENTRY
+eglWaitClient(void)
+{
+   return _eglWaitClientCommon();
+}
 
 EGLBoolean EGLAPIENTRY
 eglWaitGL(void)
 {
/* Since we only support OpenGL and GLES, eglWaitGL is equivalent to 
eglWaitClient. */
-   return eglWaitClient();
+   return _eglWaitClientCommon();
 }
 
 
-- 
2.9.3

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[Mesa-dev] [PATCH 04/14] egl: Factor out _eglGetPlatformDisplayCommon

[Adam Jackson]

From: Kyle Brenneman 

---
 src/egl/main/eglapi.c | 18 +-
 1 file changed, 13 insertions(+), 5 deletions(-)

diff --git a/src/egl/main/eglapi.c b/src/egl/main/eglapi.c
index ba8305e..df355a5 100644
--- a/src/egl/main/eglapi.c
+++ b/src/egl/main/eglapi.c
@@ -295,9 +295,9 @@ eglGetDisplay(EGLNativeDisplayType nativeDisplay)
return _eglGetDisplayHandle(dpy);
 }
 
-static EGLDisplay EGLAPIENTRY
-eglGetPlatformDisplayEXT(EGLenum platform, void *native_display,
- const EGLint *attrib_list)
+static EGLDisplay
+_eglGetPlatformDisplayCommon(EGLenum platform, void *native_display,
+const EGLint *attrib_list)
 {
_EGLDisplay *dpy;
 
@@ -326,17 +326,25 @@ eglGetPlatformDisplayEXT(EGLenum platform, void 
*native_display,
return _eglGetDisplayHandle(dpy);
 }
 
+static EGLDisplay EGLAPIENTRY
+eglGetPlatformDisplayEXT(EGLenum platform, void *native_display,
+ const EGLint *attrib_list)
+{
+   return _eglGetPlatformDisplayCommon(platform, native_display, attrib_list);
+}
+
 EGLDisplay EGLAPIENTRY
 eglGetPlatformDisplay(EGLenum platform, void *native_display,
   const EGLAttrib *attrib_list)
 {
EGLDisplay display;
-   EGLint *int_attribs = _eglConvertAttribsToInt(attrib_list);
+   EGLint *int_attribs;
 
+   int_attribs = _eglConvertAttribsToInt(attrib_list);
if (attrib_list && !int_attribs)
   RETURN_EGL_ERROR(NULL, EGL_BAD_ALLOC, NULL);
 
-   display = eglGetPlatformDisplayEXT(platform, native_display, int_attribs);
+   display = _eglGetPlatformDisplayCommon(platform, native_display, 
int_attribs);
free(int_attribs);
return display;
 }
-- 
2.9.3

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[Mesa-dev] [PATCH 00/14] EGL_KHR_debug v3

[Adam Jackson]

This gets us to basically the same end state as before, but I've
rearranged the sequence of changes to be a little easier to review and
not introduce broken intermediate states.

01 updates eglext.h to the very latest. 02 is a bugfix for leaking images
and syncs at eglTerminate, pointed out in review; technically it's an
independent change. 04 through 11 factor out common code paths so that
the eventual _EGL_FUNC_START macro can set the current function string
correctly. 13 wires up the internals of debug state tracking, and 14
adds the user-facing API.

- ajax

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[Mesa-dev] [PATCH 3/3] Revert "i965: Drop the maximum 3D texture size to 512 on Sandy Bridge"

[Jason Ekstrand]

This reverts commit 6ba88bce64b343761aabe3a6c7ee285c6020a959.  The commit
was erroneous because GL already provides a separate guard on the number of
layers you are allowed to render into.  On Sandy Bridge, we set this guard
correctly so creating a 3D texture bigger than 512 is fine, you just can't
render into all of the slices at once.

Signed-off-by: Jason Ekstrand 
---
 src/mesa/drivers/dri/i965/brw_context.c | 11 +--
 1 file changed, 1 insertion(+), 10 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_context.c 
b/src/mesa/drivers/dri/i965/brw_context.c
index c28401a..3af4555 100644
--- a/src/mesa/drivers/dri/i965/brw_context.c
+++ b/src/mesa/drivers/dri/i965/brw_context.c
@@ -524,16 +524,7 @@ brw_initialize_context_constants(struct brw_context *brw)
ctx->Const.MaxImageUnits = MAX_IMAGE_UNITS;
ctx->Const.MaxRenderbufferSize = 8192;
ctx->Const.MaxTextureLevels = MIN2(14 /* 8192 */, MAX_TEXTURE_LEVELS);
-
-   /* On Sandy Bridge and prior, the "Render Target View Extent" field of
-* RENDER_SURFACE_STATE is only 9 bits so the largest 3-D texture we can do
-* a layered render into has a depth of 512.  On Iron Lake and earlier, we
-* don't support layered rendering and we use manual offsetting to render
-* into the different layers so this doesn't matter.  On Sandy Bridge,
-* however, we do support layered rendering so this is a problem.
-*/
-   ctx->Const.Max3DTextureLevels = brw->gen == 6 ? 10 /* 512 */ : 12; /* 2048 
*/
-
+   ctx->Const.Max3DTextureLevels = 12; /* 2048 */
ctx->Const.MaxCubeTextureLevels = 14; /* 8192 */
ctx->Const.MaxArrayTextureLayers = brw->gen >= 7 ? 2048 : 512;
ctx->Const.MaxTextureMbytes = 1536;
-- 
2.5.0.400.gff86faf

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[Mesa-dev] [PATCH 1/3] intel/isl: Treat 3-D textures as 2-D arrays for rendering

[Jason Ekstrand]

In particular, this means that isl_view::base_array_layer and
isl_view::array_len get applied to 3-D textures but only when rendering.
We were already applying isl_view::base_array_layer for rendering into 3-D
textures so this isn't a huge deviation.

Signed-off-by: Jason Ekstrand 
Cc: Chad Versace 
---
 src/intel/isl/isl.h   |  6 ++
 src/intel/isl/isl_surface_state.c | 11 +++
 2 files changed, 13 insertions(+), 4 deletions(-)

diff --git a/src/intel/isl/isl.h b/src/intel/isl/isl.h
index bb20d17..e01624b 100644
--- a/src/intel/isl/isl.h
+++ b/src/intel/isl/isl.h
@@ -879,6 +879,12 @@ struct isl_view {
 *
 * For cube maps, both base_array_layer and array_len should be
 * specified in terms of 2-D layers and must be a multiple of 6.
+*
+* 3-D textures are effectively treated as 2-D arrays when used as a
+* storage image or render target.  If `usage` contains
+* ISL_SURF_USAGE_RENDER_TARGET_BIT or ISL_SURF_USAGE_STORAGE_BIT then
+* base_array_layer and array_len are applied.  If the surface is only used
+* for texturing, they are ignored.
 */
uint32_t base_array_layer;
uint32_t array_len;
diff --git a/src/intel/isl/isl_surface_state.c 
b/src/intel/isl/isl_surface_state.c
index 979e140..5c5386e 100644
--- a/src/intel/isl/isl_surface_state.c
+++ b/src/intel/isl/isl_surface_state.c
@@ -288,8 +288,6 @@ isl_genX(surf_fill_state_s)(const struct isl_device *dev, 
void *state,
  s.RenderTargetViewExtent = s.Depth;
   break;
case SURFTYPE_3D:
-  s.MinimumArrayElement = info->view->base_array_layer;
-
   /* From the Broadwell PRM >> RENDER_SURFACE_STATE::Depth:
*
*If the volume texture is MIP-mapped, this field specifies the
@@ -309,11 +307,16 @@ isl_genX(surf_fill_state_s)(const struct isl_device *dev, 
void *state,
* textures with more levels than we can render to.  In order to prevent
* assert-failures in the packing function below, we only set the field
* when it's actually going to be used by the hardware.
+   *
+   * Similaraly, the MinimumArrayElement field is ignored by all hardware
+   * prior to Sky Lake when texturing and we want it set to 0 anyway.
+   * Since it's already initialized to 0, we can just leave it alone for
+   * texture surfaces.
*/
   if (info->view->usage & (ISL_SURF_USAGE_RENDER_TARGET_BIT |
ISL_SURF_USAGE_STORAGE_BIT)) {
- s.RenderTargetViewExtent = 
isl_minify(info->surf->logical_level0_px.depth,
-   info->view->base_level) - 1;
+ s.MinimumArrayElement = info->view->base_array_layer;
+ s.RenderTargetViewExtent = info->view->array_len - 1;
   }
   break;
default:
-- 
2.5.0.400.gff86faf

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[Mesa-dev] [PATCH 2/3] blorp: Handle the 512 layers restriction on Sandy Bridge

[Jason Ekstrand]

---
 src/intel/blorp/blorp.c   |  6 ++
 src/intel/blorp/blorp_clear.c | 17 +
 2 files changed, 19 insertions(+), 4 deletions(-)

diff --git a/src/intel/blorp/blorp.c b/src/intel/blorp/blorp.c
index 17c1ff4..8dfebbc 100644
--- a/src/intel/blorp/blorp.c
+++ b/src/intel/blorp/blorp.c
@@ -139,6 +139,12 @@ brw_blorp_surface_info_init(struct blorp_context *blorp,
   info->view.array_len -= info->view.base_array_layer;
   info->z_offset = 0;
}
+
+   /* Sandy Bridge has a limit of a maximum of 512 layers for layered
+* rendering.
+*/
+   if (is_render_target && blorp->isl_dev->info->gen == 6)
+  info->view.array_len = MIN2(info->view.array_len, 512);
 }
 
 
diff --git a/src/intel/blorp/blorp_clear.c b/src/intel/blorp/blorp_clear.c
index cba4823..2213ada 100644
--- a/src/intel/blorp/blorp_clear.c
+++ b/src/intel/blorp/blorp_clear.c
@@ -246,7 +246,6 @@ blorp_clear(struct blorp_batch *batch,
 {
struct blorp_params params;
blorp_params_init();
-   params.num_layers = num_layers;
 
params.x0 = x0;
params.y0 = y0;
@@ -278,10 +277,20 @@ blorp_clear(struct blorp_batch *batch,
blorp_params_get_clear_kernel(batch->blorp, ,
  use_simd16_replicated_data);
 
-   brw_blorp_surface_info_init(batch->blorp, , surf, level,
-   start_layer, format, true);
+   while (num_layers > 0) {
+  brw_blorp_surface_info_init(batch->blorp, , surf, level,
+  start_layer, format, true);
 
-   batch->blorp->exec(batch, );
+  /* We may be restricted on the number of layers we can bind at any one
+   * time.  In particular, Sandy Bridge has a maximum number of layers of
+   * 512 but a maximum 3D texture size is much larger.
+   */
+  params.num_layers = MIN2(params.dst.view.array_len, num_layers);
+  batch->blorp->exec(batch, );
+
+  start_layer += params.num_layers;
+  num_layers -= params.num_layers;
+   }
 }
 
 void
-- 
2.5.0.400.gff86faf

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Re: [Mesa-dev] [PATCH] HUD: Add support for block I/O, network I/O and lmsensor stats

[Steven Toth]

> I think you expose Temperature, Voltage and Current. But Nouveau exposes
> Temperature, Voltage, Fan and Power through hwmon.
>
> Read the "power" section here for more info:
> https://www.kernel.org/doc/Documentation/hwmon/sysfs-interface

Ahh, my nouveau card must be too old then. I only get temperature from
it. I have a 6yo(?) 8800 GTS. That being said - it services the
console well enough.

nouveau-pci-0100
Adapter: PCI adapter
temp1:+57.0°C  (high = +95.0°C, hyst =  +3.0°C)
   (crit = +110.0°C, hyst =  +2.0°C)
   (emerg = +135.0°C, hyst =  +5.0°C)

In fact, I don't seem to have any dev boxes that expose power. That's a odd.

If you want to recommend a specific nvidia card/model that you know
for certain exposes these features then I'll see what I can do.

-- 
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http://www.kernellabs.com
+1.646.355.8490
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Re: [Mesa-dev] [PATCH] HUD: Add support for block I/O, network I/O and lmsensor stats

[Karol Herbst]

2016-09-12 23:20 GMT+02:00 Steven Toth :
>> nice work regarding the lmsensor bits. But I think it makes sense to
>> also wire the power things in, cause we actually expose them within
>> nouveau. Others might want or actually do the same as well.
>
> Karol, thank you for your feedback.
>
> I'm happy and willing to adapt to any changes recommended. That being
> said, I'm not sure I fully understand what you mean. Can you please be
> more specific?
>
> If the nouveau driver is exposing a specific set of sensors that you'd
> like me to test, I'd be happy to do this and report back  or adapt
> the patchset accordingly.
>

I think you expose Temperature, Voltage and Current. But Nouveau exposes
Temperature, Voltage, Fan and Power through hwmon.

Read the "power" section here for more info:
https://www.kernel.org/doc/Documentation/hwmon/sysfs-interface


Thanks

Karol

> Thanks.
>
> --
> Steven Toth - Kernel Labs
> http://www.kernellabs.com
> +1.646.355.8490
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Re: [Mesa-dev] [PATCH] anv/cmd_buffer: Set the L3 atomic disable mask bit in CHICKEN3 on HSW

[Francisco Jerez]

Jason Ekstrand  writes:

> Without this bit set, the value in "L3 Atomic Disable" won't get applied by
> the hardware so we won't properly get L3 atomic caching.
>
> Fixes dEQP-VK.spirv_assembly.instruction.compute.opatomic.compex on HSW
>
> Signed-off-by: Jason Ekstrand 
> Cc: Lionel Landwerlin 
> Cc: Francisco Jerez 

Reviewed-by: Francisco Jerez 

> ---
>  src/intel/genxml/gen75.xml | 1 +
>  src/intel/vulkan/genX_cmd_buffer.c | 1 +
>  2 files changed, 2 insertions(+)
>
> diff --git a/src/intel/genxml/gen75.xml b/src/intel/genxml/gen75.xml
> index 27112b6..1debc3a 100644
> --- a/src/intel/genxml/gen75.xml
> +++ b/src/intel/genxml/gen75.xml
> @@ -2951,6 +2951,7 @@
>  
>
>  
> +
>
>  
>  
> diff --git a/src/intel/vulkan/genX_cmd_buffer.c 
> b/src/intel/vulkan/genX_cmd_buffer.c
> index b6f93e7..6a84383 100644
> --- a/src/intel/vulkan/genX_cmd_buffer.c
> +++ b/src/intel/vulkan/genX_cmd_buffer.c
> @@ -296,6 +296,7 @@ genX(cmd_buffer_config_l3)(struct anv_cmd_buffer 
> *cmd_buffer,
>anv_pack_struct(, GENX(SCRATCH1),
>.L3AtomicDisable = !has_dc);
>anv_pack_struct(, GENX(CHICKEN3),
> +  .L3AtomicDisableMask = true,
>.L3AtomicDisable = !has_dc);
>emit_lri(_buffer->batch, GENX(SCRATCH1_num), scratch1);
>emit_lri(_buffer->batch, GENX(CHICKEN3_num), chicken3);
> -- 
> 2.5.0.400.gff86faf


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[Mesa-dev] [PATCH] anv/cmd_buffer: Set the L3 atomic disable mask bit in CHICKEN3 on HSW

[Jason Ekstrand]

Without this bit set, the value in "L3 Atomic Disable" won't get applied by
the hardware so we won't properly get L3 atomic caching.

Fixes dEQP-VK.spirv_assembly.instruction.compute.opatomic.compex on HSW

Signed-off-by: Jason Ekstrand 
Cc: Lionel Landwerlin 
Cc: Francisco Jerez 
---
 src/intel/genxml/gen75.xml | 1 +
 src/intel/vulkan/genX_cmd_buffer.c | 1 +
 2 files changed, 2 insertions(+)

diff --git a/src/intel/genxml/gen75.xml b/src/intel/genxml/gen75.xml
index 27112b6..1debc3a 100644
--- a/src/intel/genxml/gen75.xml
+++ b/src/intel/genxml/gen75.xml
@@ -2951,6 +2951,7 @@
 
   
 
+
   
 
 
diff --git a/src/intel/vulkan/genX_cmd_buffer.c 
b/src/intel/vulkan/genX_cmd_buffer.c
index b6f93e7..6a84383 100644
--- a/src/intel/vulkan/genX_cmd_buffer.c
+++ b/src/intel/vulkan/genX_cmd_buffer.c
@@ -296,6 +296,7 @@ genX(cmd_buffer_config_l3)(struct anv_cmd_buffer 
*cmd_buffer,
   anv_pack_struct(, GENX(SCRATCH1),
   .L3AtomicDisable = !has_dc);
   anv_pack_struct(, GENX(CHICKEN3),
+  .L3AtomicDisableMask = true,
   .L3AtomicDisable = !has_dc);
   emit_lri(_buffer->batch, GENX(SCRATCH1_num), scratch1);
   emit_lri(_buffer->batch, GENX(CHICKEN3_num), chicken3);
-- 
2.5.0.400.gff86faf

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[Mesa-dev] [PATCH shader-db] add a new option for selecting the render node ID

[Samuel Pitoiset]

When multiple GPUs are plugged in the same box, we might want to
use /dev/dri/renderD129 without updating/compiling the code. This
doesn't change the existing behaviour.
---
 run.c | 23 +++
 1 file changed, 19 insertions(+), 4 deletions(-)

diff --git a/run.c b/run.c
index c7f0be6..408049f 100644
--- a/run.c
+++ b/run.c
@@ -301,7 +301,7 @@ const struct platform platforms[] = {
 void print_usage(const char *prog_name)
 {
 fprintf(stderr,
-"Usage: %s [-p ] \n"
+"Usage: %s [-d ] [-p ] \n"
 "Other options: \n"
 " -1Disable multi-threading\n",
 prog_name);
@@ -323,12 +323,24 @@ static void addenv(const char *name, const char *value)
 int
 main(int argc, char **argv)
 {
+char device_path[64];
+int device_id = 0;
 int opt;
 
 max_threads = omp_get_max_threads();
 
-while((opt = getopt(argc, argv, "1p:")) != -1) {
+while((opt = getopt(argc, argv, "1d:p:")) != -1) {
 switch(opt) {
+case 'd': {
+char *endptr;
+
+device_id = strtol(optarg, , 10);
+if (endptr == optarg) {
+fprintf(stderr, "Invalid device ID.\n");
+return -1;
+}
+break;
+}
 case 'p': {
 const struct platform *platform = NULL;
 for (unsigned i = 0; i < ARRAY_SIZE(platforms); i++) {
@@ -386,9 +398,12 @@ main(int argc, char **argv)
 
 int ret = 0;
 
-int fd = open("/dev/dri/renderD128", O_RDWR);
+snprintf(device_path, sizeof(device_path),
+ "/dev/dri/renderD%d", device_id + 128);
+
+int fd = open(device_path, O_RDWR);
 if (unlikely(fd < 0)) {
-fprintf(stderr, "ERROR: Couldn't open /dev/dri/renderD128\n");
+fprintf(stderr, "ERROR: Couldn't open %s\n", device_path);
 return -1;
 }
 
-- 
2.8.0

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Re: [Mesa-dev] [PATCH] HUD: Add support for block I/O, network I/O and lmsensor stats

[Steven Toth]

> Can you enclose all the unix-specific parts in #ifdef PIPE_OS_UNIX to allow
> this to build for Windows?
>
> -Brian

Brian, thank you for your feedback.

Whoops! Yes, I'll take care of this.

-- 
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Re: [Mesa-dev] [PATCH 62/95] i965/vec4: Add a shuffle_64bit_data helper

[Francisco Jerez]

Iago Toral Quiroga  writes:

> SIMD4x2 64bit data is stored in register space like this:
>
> r0.0:DF  x0 y0 z0 w0
> r0.1:DF  x1 y1 z1 w1
>
> When we need to write data such as this to memory using 32-bit write
> messages we need to shuffle it in this fashion:
>
> r0.0:DF  x0 y0 x1 y1
> r0.1:DF  z0 w0 z1 w1
>
> and emit two 32-bit write messages, one for r0.0 at base_offset
> and another one for r0.1 at base_offset+16.
>
> We also need to do the inverse operation when we read using 32-bit messages
> to produce valid SIMD4x2 64bit data from the data read. We can achieve this
> by aplying the exact same shuffling to the data read, although we need to
> apply different channel enables since the layout of the data is reversed.
>
> This helper implements the data shuffling logic and we will use it in
> various places where we read and write 64bit data from/to memory.
> ---
>  src/mesa/drivers/dri/i965/brw_vec4.h   |  5 ++
>  src/mesa/drivers/dri/i965/brw_vec4_nir.cpp | 96 
> ++
>  2 files changed, 101 insertions(+)
>
> diff --git a/src/mesa/drivers/dri/i965/brw_vec4.h 
> b/src/mesa/drivers/dri/i965/brw_vec4.h
> index 26228d0..3337fc0 100644
> --- a/src/mesa/drivers/dri/i965/brw_vec4.h
> +++ b/src/mesa/drivers/dri/i965/brw_vec4.h
> @@ -327,6 +327,11 @@ public:
>  
> src_reg setup_imm_df(double v);
>  
> +   vec4_instruction *shuffle_64bit_data(dst_reg dst, src_reg src,
> +bool for_write,
> +bblock_t *block = NULL,
> +vec4_instruction *ref = NULL);
> +
> virtual void emit_nir_code();
> virtual void nir_setup_uniforms();
> virtual void nir_setup_system_value_intrinsic(nir_intrinsic_instr *instr);
> diff --git a/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp 
> b/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp
> index 450db92..346e822 100644
> --- a/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp
> +++ b/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp
> @@ -2145,4 +2145,100 @@ vec4_visitor::nir_emit_undef(nir_ssa_undef_instr 
> *instr)
>dst_reg(VGRF, alloc.allocate(instr->def.bit_size / 32));
>  }
>  
> +/* SIMD4x2 64bit data is stored in register space like this:
> + *
> + * r0.0:DF  x0 y0 z0 w0
> + * r0.1:DF  x1 y1 z1 w1
> + *
> + * When we need to write data such as this to memory using 32-bit write
> + * messages we need to shuffle it in this fashion:
> + *
> + * r0.0:DF  x0 y0 x1 y1 (to be written at base offset)
> + * r0.0:DF  z0 w0 z1 w1 (to be written at base offset + 16)
> + *
> + * We need to do the inverse operation when we read using 32-bit messages,
> + * which we can do by applying the same exact shuffling on the 64-bit data
> + * read, only that because the data for each vertex is positioned differently
> + * we need to apply different channel enables.
> + *
> + * This function takes 64bit data and shuffles it as explained above.
> + *
> + * The @for_write parameter is used to specify if the shuffling is being done
> + * for proper SIMD4x2 64-bit data that needs to be shuffled prior to a 32-bit
> + * write message (for_write = true), or instead we are doing the inverse
> + * opperation and we have just read 64-bit data using a 32-bit messages that 
> we
> + * need to shuffle to create valid SIMD4x2 64-bit data (for_write = false).
> + *
> + * If @block and @ref are non-NULL, then the shuffling is done after @ref,
> + * otherwise the instructions are emitted normally at the end. The function
> + * returns the last instruction inserted.
> + *
> + * Notice that @src and @dst cannot be the same register.
> + */
> +vec4_instruction *
> +vec4_visitor::shuffle_64bit_data(dst_reg dst, src_reg src, bool for_write,
> + bblock_t *block, vec4_instruction *ref)
> +{
> +   assert(type_sz(src.type) == 8);
> +   assert(type_sz(dst.type) == 8);
> +   assert(!src.in_range(dst, 2));
> +   assert(dst.writemask == WRITEMASK_XYZW);
> +   assert(!ref == !block);
> +
> +   vec4_instruction *inst, *last;
> +   bool emit_before = ref != NULL;
> +
> +   #define EMIT(i) \
> +  if (!emit_before) { \
> + emit(i); \
> +  } else { \
> + ref->insert_after(block, i); \
> + ref = i; \
> +  }  \
> +  last = i;
> +
> +   /* Resolve swizzle in src */
> +   if (src.swizzle != BRW_SWIZZLE_XYZW) {
> +  dst_reg data = dst_reg(this, glsl_type::dvec4_type);
> +  inst = MOV(data, src);
> +  EMIT(inst);
> +  src = src_reg(data);
> +   }
> +
> +   /* dst+0.XY = src+0.XY */
> +   dst.writemask = WRITEMASK_XY;
> +   inst = MOV(dst, src);
> +   inst->regs_written = 1;
> +   inst->exec_size = 4;
> +   EMIT(inst);
> +
> +   /* dst+0.ZW = src+1.XY */
> +   dst.writemask = WRITEMASK_ZW;
> +   inst = MOV(dst, swizzle(offset(src, 1), BRW_SWIZZLE_XYXY));
> +   inst->regs_written = 1;
> +   inst->exec_size = 4;
> +   inst->group = for_write ? 4 : 0;
> +   EMIT(inst);
> +
> +   /* dst+1.XY = 

Re: [Mesa-dev] [PATCH] HUD: Add support for block I/O, network I/O and lmsensor stats

[Steven Toth]

> nice work regarding the lmsensor bits. But I think it makes sense to
> also wire the power things in, cause we actually expose them within
> nouveau. Others might want or actually do the same as well.

Karol, thank you for your feedback.

I'm happy and willing to adapt to any changes recommended. That being
said, I'm not sure I fully understand what you mean. Can you please be
more specific?

If the nouveau driver is exposing a specific set of sensors that you'd
like me to test, I'd be happy to do this and report back  or adapt
the patchset accordingly.

Thanks.

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[Mesa-dev] [PATCH 1/2] ddebug: fix a crash in resource_get_handle

[Marek Olšák]

From: Marek Olšák 

broken recently
---
 src/gallium/drivers/ddebug/dd_screen.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/gallium/drivers/ddebug/dd_screen.c 
b/src/gallium/drivers/ddebug/dd_screen.c
index 4050e39..a0c0dd0 100644
--- a/src/gallium/drivers/ddebug/dd_screen.c
+++ b/src/gallium/drivers/ddebug/dd_screen.c
@@ -236,21 +236,21 @@ dd_screen_resource_destroy(struct pipe_screen *_screen,
 }
 
 static boolean
 dd_screen_resource_get_handle(struct pipe_screen *_screen,
   struct pipe_context *_pipe,
   struct pipe_resource *resource,
   struct winsys_handle *handle,
   unsigned usage)
 {
struct pipe_screen *screen = dd_screen(_screen)->screen;
-   struct pipe_context *pipe = dd_context(_pipe)->pipe;
+   struct pipe_context *pipe = _pipe ? dd_context(_pipe)->pipe : NULL;
 
return screen->resource_get_handle(screen, pipe, resource, handle, usage);
 }
 
 
 /
  * fence
  */
 
 static void
-- 
2.7.4

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[Mesa-dev] [PATCH 2/2] ddebug: dump shader buffers and images

[Marek Olšák]

From: Marek Olšák 

this was unimplemented
---
 src/gallium/auxiliary/util/u_dump.h   |  3 +++
 src/gallium/auxiliary/util/u_dump_state.c | 19 +++
 src/gallium/drivers/ddebug/dd_draw.c  | 30 +++---
 3 files changed, 49 insertions(+), 3 deletions(-)

diff --git a/src/gallium/auxiliary/util/u_dump.h 
b/src/gallium/auxiliary/util/u_dump.h
index 2598851..bce8517 100644
--- a/src/gallium/auxiliary/util/u_dump.h
+++ b/src/gallium/auxiliary/util/u_dump.h
@@ -152,20 +152,23 @@ util_dump_sampler_state(FILE *stream,
 const struct pipe_sampler_state *state);
 
 void
 util_dump_surface(FILE *stream,
   const struct pipe_surface *state);
 
 void
 util_dump_image_view(FILE *stream, const struct pipe_image_view *state);
 
 void
+util_dump_shader_buffer(FILE *stream, const struct pipe_shader_buffer *state);
+
+void
 util_dump_sampler_view(FILE *stream, const struct pipe_sampler_view *state);
 
 void
 util_dump_transfer(FILE *stream,
const struct pipe_transfer *state);
 
 void
 util_dump_constant_buffer(FILE *stream,
   const struct pipe_constant_buffer *state);
 
diff --git a/src/gallium/auxiliary/util/u_dump_state.c 
b/src/gallium/auxiliary/util/u_dump_state.c
index 6aecee1..06d5e78 100644
--- a/src/gallium/auxiliary/util/u_dump_state.c
+++ b/src/gallium/auxiliary/util/u_dump_state.c
@@ -729,20 +729,39 @@ util_dump_image_view(FILE *stream, const struct 
pipe_image_view *state)
   util_dump_member(stream, uint, state, u.tex.first_layer);
   util_dump_member(stream, uint, state, u.tex.last_layer);
   util_dump_member(stream, uint, state, u.tex.level);
}
 
util_dump_struct_end(stream);
 }
 
 
 void
+util_dump_shader_buffer(FILE *stream, const struct pipe_shader_buffer *state)
+{
+   if (!state) {
+  util_dump_null(stream);
+  return;
+   }
+
+   util_dump_struct_begin(stream, "pipe_shader_buffer");
+
+   util_dump_member(stream, ptr, state, buffer);
+   util_dump_member(stream, uint, state, buffer_offset);
+   util_dump_member(stream, uint, state, buffer_size);
+
+   util_dump_struct_end(stream);
+
+}
+
+
+void
 util_dump_sampler_view(FILE *stream, const struct pipe_sampler_view *state)
 {
if (!state) {
   util_dump_null(stream);
   return;
}
 
util_dump_struct_begin(stream, "pipe_sampler_view");
 
util_dump_member(stream, enum_tex_target, state, target);
diff --git a/src/gallium/drivers/ddebug/dd_draw.c 
b/src/gallium/drivers/ddebug/dd_draw.c
index 3124d05..511daf4 100644
--- a/src/gallium/drivers/ddebug/dd_draw.c
+++ b/src/gallium/drivers/ddebug/dd_draw.c
@@ -306,22 +306,33 @@ dd_dump_draw_vbo(struct dd_draw_state *dstate, struct 
pipe_draw_info *info, FILE
   for (i = 0; i < PIPE_MAX_SAMPLERS; i++)
  if (dstate->sampler_states[sh][i])
 DUMP_I(sampler_state, 
>sampler_states[sh][i]->state.sampler, i);
 
   for (i = 0; i < PIPE_MAX_SAMPLERS; i++)
  if (dstate->sampler_views[sh][i]) {
 DUMP_I(sampler_view, dstate->sampler_views[sh][i], i);
 DUMP_M(resource, dstate->sampler_views[sh][i], texture);
  }
 
-  /* TODO: print shader images */
-  /* TODO: print shader buffers */
+  for (i = 0; i < PIPE_MAX_SHADER_IMAGES; i++)
+ if (dstate->shader_images[sh][i].resource) {
+DUMP_I(image_view, >shader_images[sh][i], i);
+if (dstate->shader_images[sh][i].resource)
+   DUMP_M(resource, >shader_images[sh][i], resource);
+ }
+
+  for (i = 0; i < PIPE_MAX_SHADER_BUFFERS; i++)
+ if (dstate->shader_buffers[sh][i].buffer) {
+DUMP_I(shader_buffer, >shader_buffers[sh][i], i);
+if (dstate->shader_buffers[sh][i].buffer)
+   DUMP_M(resource, >shader_buffers[sh][i], buffer);
+ }
 
   fprintf(f, COLOR_SHADER "end shader: %s" COLOR_RESET "\n\n", 
shader_str[sh]);
}
 
if (dstate->dsa)
   DUMP(depth_stencil_alpha_state, >dsa->state.dsa);
DUMP(stencil_ref, >stencil_ref);
 
if (dstate->blend)
   DUMP(blend_state, >blend->state.blend);
@@ -797,21 +808,34 @@ dd_copy_draw_state(struct dd_draw_state *dst, struct 
dd_draw_state *src)
 
   for (j = 0; j < PIPE_MAX_SAMPLERS; j++) {
  pipe_sampler_view_reference(>sampler_views[i][j],
  src->sampler_views[i][j]);
  if (src->sampler_states[i][j])
 dst->sampler_states[i][j]->state.sampler =
src->sampler_states[i][j]->state.sampler;
  else
 dst->sampler_states[i][j] = NULL;
   }
-  /* TODO: shader buffers & images */
+
+  for (j = 0; j < PIPE_MAX_SHADER_IMAGES; j++) {
+ pipe_resource_reference(>shader_images[i][j].resource,
+ src->shader_images[i][j].resource);
+ memcpy(>shader_images[i][j], >shader_images[i][j],
+

Re: [Mesa-dev] [PATCH 53/95] i965/disasm: fix subreg for dst in Align16 mode

[Francisco Jerez]

Iago Toral Quiroga  writes:

> There is a single bit for this, so it is a binary 0 or 1 meaning
> offset 0B or 16B respectively.
> ---
>  src/mesa/drivers/dri/i965/brw_disasm.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/src/mesa/drivers/dri/i965/brw_disasm.c 
> b/src/mesa/drivers/dri/i965/brw_disasm.c
> index d5e9916..f4f41de 100644
> --- a/src/mesa/drivers/dri/i965/brw_disasm.c
> +++ b/src/mesa/drivers/dri/i965/brw_disasm.c
> @@ -748,7 +748,7 @@ dest(FILE *file, const struct brw_device_info *devinfo, 
> brw_inst *inst)
>   if (err == -1)
>  return 0;
>   if (brw_inst_dst_da16_subreg_nr(devinfo, inst))
> -format(file, ".%"PRIu64, brw_inst_dst_da16_subreg_nr(devinfo, 
> inst) /
> +format(file, ".%"PRIu64, 16 * 
> brw_inst_dst_da16_subreg_nr(devinfo, inst) /
> reg_type_size[brw_inst_dst_reg_type(devinfo, inst)]);

If brw_inst_dst_da16_subreg_nr(devinfo, inst) is guaranteed to be one,
isn't this equivalent to '16 /
reg_type_size[brw_inst_dst_reg_type(devinfo, inst)]'?

With that fixed:

Reviewed-by: Francisco Jerez 

>   string(file, "<1>");
>   err |= control(file, "writemask", writemask,
> -- 
> 2.7.4
>
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Re: [Mesa-dev] [PATCH 48/95] i965/vec4: add a force_vstride0 flag to src_reg

[Francisco Jerez]

Iago Toral Quiroga  writes:

> We will use this in cases where we want to force the vstride of a src_reg
> to 0 to exploit a particular behavior of the hardware. It will come in
> handy to implement access to components Z/W.
> ---
>  src/mesa/drivers/dri/i965/brw_ir_vec4.h | 1 +
>  src/mesa/drivers/dri/i965/brw_vec4.cpp  | 2 ++
>  2 files changed, 3 insertions(+)
>
> diff --git a/src/mesa/drivers/dri/i965/brw_ir_vec4.h 
> b/src/mesa/drivers/dri/i965/brw_ir_vec4.h
> index f66c093..f3cce4b 100644
> --- a/src/mesa/drivers/dri/i965/brw_ir_vec4.h
> +++ b/src/mesa/drivers/dri/i965/brw_ir_vec4.h
> @@ -51,6 +51,7 @@ public:
> explicit src_reg(const dst_reg );
>  
> src_reg *reladdr;
> +   bool force_vstride0;

I was wondering whether it would make more sense to unify this with the
FS back-end's fs_reg::stride (a numeric stride field is also likely more
convenient to do arithmetic on than a boolean) and promote it to
backend_reg?  It could be defined as the number of components to jump
over for each logical channel of the register, which is just the vstride
in single-precision SIMD4x2 and the hstride in scalar mode.

But thinking about it some more, I wonder if it's really necessary to
expose vertical strides at the IR level?  Aren't you planing to use this
during the conversion to HW registers exclusively?  Why don't you set
the vstride field directly in that case?

>  };
>  
>  static inline src_reg
> diff --git a/src/mesa/drivers/dri/i965/brw_vec4.cpp 
> b/src/mesa/drivers/dri/i965/brw_vec4.cpp
> index a20b2fd..bfbbd96 100644
> --- a/src/mesa/drivers/dri/i965/brw_vec4.cpp
> +++ b/src/mesa/drivers/dri/i965/brw_vec4.cpp
> @@ -70,6 +70,7 @@ src_reg::src_reg(struct ::brw_reg reg) :
>  {
> this->reg_offset = 0;
> this->reladdr = NULL;
> +   this->force_vstride0 = false;
>  }
>  
>  src_reg::src_reg(const dst_reg ) :
> @@ -77,6 +78,7 @@ src_reg::src_reg(const dst_reg ) :
>  {
> this->reladdr = reg.reladdr;
> this->swizzle = brw_swizzle_for_mask(reg.writemask);
> +   this->force_vstride0 = false;
>  }
>  
>  void
> -- 
> 2.7.4
>
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Re: [Mesa-dev] [PATCH 27/33] anv: Use blorp for CopyImageToBuffer

[Jason Ekstrand]

On Sep 12, 2016 1:31 PM, "Nanley Chery"  wrote:
>
> On Mon, Sep 12, 2016 at 12:45:51PM -0700, Jason Ekstrand wrote:
> > On Mon, Sep 12, 2016 at 12:30 PM, Nanley Chery 
> > wrote:
> >
> > > On Wed, Aug 31, 2016 at 02:22:46PM -0700, Jason Ekstrand wrote:
> > > > ---
> > > >  src/intel/vulkan/anv_blorp.c | 134
++
> > > +
> > > >  src/intel/vulkan/anv_meta_copy.c |  16 -
> > > >  2 files changed, 134 insertions(+), 16 deletions(-)
> > > >
> > > > diff --git a/src/intel/vulkan/anv_blorp.c
b/src/intel/vulkan/anv_blorp.c
> > > > index 5d715fc..a838b55 100644
> > > > --- a/src/intel/vulkan/anv_blorp.c
> > > > +++ b/src/intel/vulkan/anv_blorp.c
> > > > @@ -120,6 +120,38 @@ anv_device_finish_blorp(struct anv_device
*device)
> > > >  }
> > > >
> > > >  static void
> > > > +get_blorp_surf_for_anv_buffer(struct anv_device *device,
> > > > +  struct anv_buffer *buffer, uint64_t
> > > offset,
> > > > +  uint32_t width, uint32_t height,
> > > > +  uint32_t row_pitch, enum isl_format
> > > format,
> > > > +  struct blorp_surf *blorp_surf,
> > > > +  struct isl_surf *isl_surf)
> > > > +{
> > > > +   *blorp_surf = (struct blorp_surf) {
> > > > +  .surf = isl_surf,
> > > > +  .addr = {
> > > > + .buffer = buffer->bo,
> > > > + .offset = buffer->offset + offset,
> > > > +  },
> > > > +   };
> > > > +
> > > > +   isl_surf_init(>isl_dev, isl_surf,
> > > > + .dim = ISL_SURF_DIM_2D,
> > > > + .format = format,
> > > > + .width = width,
> > > > + .height = height,
> > > > + .depth = 1,
> > > > + .levels = 1,
> > > > + .array_len = 1,
> > > > + .samples = 1,
> > > > + .min_pitch = row_pitch,
> > >
> > > I don't think we want to set the min_pitch field. If ISL creates a
> > > surface with a pitch smaller than the required pitch, I think we'd
> > > want to know about it rather than silently aligning up. If it does
> > > get aligned up I wouldn't be confident that the HW will render or
> > > texture from the image correctly. Just having the assertion would
> > > provide such confidence whoever.
> > >
> >
> > This is one of the places where the blorp code and the old meta code
> > differ.  The blorp code just creates an image with the actual width and
> > height of the copy and pulls the row_pitch from bufferRowLength.
> >
> >
>
> I forgot that bufferRowLength could be greater than the image's
> width * block_size. Using min_pitch is in fact necessary.
>
> > > > + .usage = ISL_SURF_USAGE_TEXTURE_BIT |
> > > > +  ISL_SURF_USAGE_RENDER_TARGET_BIT,
> > > > + .tiling_flags = ISL_TILING_LINEAR_BIT);
> > > > +   assert(isl_surf->row_pitch == row_pitch);
> > > > +}
> > > > +
> > > > +static void
> > > >  get_blorp_surf_for_anv_image(const struct anv_image *image,
> > > >   VkImageAspectFlags aspect,
> > > >   struct blorp_surf *blorp_surf)
> > > > @@ -136,6 +168,108 @@ get_blorp_surf_for_anv_image(const struct
> > > anv_image *image,
> > > > };
> > > >  }
> > > >
> > > > +static void
> > > > +copy_buffer_to_image(struct anv_cmd_buffer *cmd_buffer,
> > > > + struct anv_buffer *anv_buffer,
> > > > + struct anv_image *anv_image,
> > > > + uint32_t regionCount,
> > > > + const VkBufferImageCopy* pRegions,
> > > > + bool buffer_to_image)
> > > > +{
> > > > +   struct blorp_batch batch;
> > > > +   blorp_batch_init(_buffer->device->blorp, ,
cmd_buffer);
> > > > +
> > > > +   struct {
> > > > +  struct blorp_surf surf;
> > > > +  uint32_t level;
> > > > +  VkOffset3D offset;
> > > > +   } image, buffer, *src, *dst;
> > > > +
> > > > +   buffer.level = 0;
> > > > +   buffer.offset = (VkOffset3D) { 0, 0, 0 };
> > > > +
> > > > +   if (buffer_to_image) {
> > > > +  src = 
> > > > +  dst = 
> > > > +   } else {
> > > > +  src = 
> > > > +  dst = 
> > > > +   }
> > > > +
> > > > +   for (unsigned r = 0; r < regionCount; r++) {
> > > > +  const VkImageAspectFlags aspect =
pRegions[r].imageSubresource.
> > > aspectMask;
> > > > +
> > > > +  get_blorp_surf_for_anv_image(anv_image, aspect, );
> > > > +  image.offset =
> > > > + anv_sanitize_image_offset(anv_image->type,
> > > pRegions[r].imageOffset);
> > > > +  image.level = pRegions[r].imageSubresource.mipLevel;
> > > > +
> > > > +  VkExtent3D extent =
> > > > + anv_sanitize_image_extent(anv_image->type,
> > > pRegions[r].imageExtent);
> > > > +  if (anv_image->type != VK_IMAGE_TYPE_3D) {
> > > > + image.offset.z =

Re: [Mesa-dev] [PATCH 00/57] i965/ir: Switch representation of register offsets and sizes to byte units.

[Francisco Jerez]

Francisco Jerez  writes:

> Iago Toral  writes:
>
>> On Fri, 2016-09-09 at 11:37 +0200, Iago Toral wrote:
>>> On Thu, 2016-09-08 at 11:36 +0200, Iago Toral wrote:
>>> > 
>>> > On Wed, 2016-09-07 at 18:48 -0700, Francisco Jerez wrote:
>>> > > 
>>> > > 
>>> > > This series reworks the representation of register region offsets
>>> > > in
>>> > > the i965 IR to be universally byte-based instead of the rather
>>> > > awkward
>>> > > split between reg_offset and subreg_offset we have in the FS
>>> > > back-
>>> > > end
>>> > > right now, or the reg_offset field currently used in the VEC4 IR
>>> > > which
>>> > > doesn't allow better granularity than 32B.  The most immediate
>>> > > motivation is to enable sub-GRF offsets in the VEC4 back-end,
>>> > > which
>>> > > will be useful for various kinds of lowering and instruction
>>> > > splitting
>>> > > required for FP64 support on VEC4 platforms.
>>> > Thanks a lot for taking care of this!
>>> > 
>>> > > 
>>> > > 
>>> > > Patches 01-11 take care of scaling the regs_written and regs_read
>>> > > instruction methods on both back-ends and the reg_offset register
>>> > > field of VEC4 IR registers.  The fs_reg::reg_offset and
>>> > > ::subreg_offset fields are also unified into a single register
>>> > > field.
>>> > > Because this part of the series is rather bulky I've tried to
>>> > > keep
>>> > > the
>>> > > changes as obvious and functionally equivalent as possible at the
>>> > > cost
>>> > > of introducing not particularly clever code in some cases that
>>> > > could
>>> > > be simplified with some knowledge of the context.  Patches 31-46
>>> > > make
>>> > > a second pass through the code touched in the first part of the
>>> > > series
>>> > > in order to get rid of an amount of cruft.
>>> > I have reviewed this part and intend to continue reviewing the rest
>>> > in
>>> > the following days. Might be a good idea to have another set of
>>> > eyes
>>> > reviewing the series or at least skimming through it just in case.
>>> > 
>>> > You might want to look at least at the second comment I made to
>>> > patch
>>> > 2
>>> > and the comment to patch 7, since these might be actual problems.
>>> > All
>>> > other comments are minor things or small clarifications and you can
>>> > ignore them if you want.
>>> > 
>>> > With the issues I point out in patches 2 and 7 addressed (or
>>> > confirmation from your side that these are not real problems),
>>> > patches
>>> > 1-11 are:
>>> > 
>>> > Reviewed-by: Iago Toral Quiroga 
>>> > 
>>> > > 
>>> > > 
>>> > > Patches 12-30 address an amount of bugs that became obvious
>>> > > during
>>> > > the
>>> > > conversion to byte units, some of them seem worrying enough that
>>> > > it
>>> > > might make sense to back-port them to stable releases.
>>> I have just reviewed this part too and it looks good to me.
>>> 
>>> You probably want to look at least at the comment to patch 25, since
>>> I
>>> think that might be a genuine mistake. The comment to patch 27 points
>>> out a possible problem (but even if it is a problem it is not really
>>> related this patch set). I find patch 28 a bit confusing since it
>>> seems
>>> to be doing something that is not quite right and then fixing it in
>>> patch 29, I may be misunderstanding what is going on there, but
>>> otherwise I think it would be best to squash both together.
>>> 
>>> Other than these things, patches 12-31 are:
>>> 
>>> Reviewed-by: Iago Toral Quiroga 
>>
>> Patches 32-46 are:
>>
>> Reviewed-by: Iago Toral Quiroga 
>>
>> I hope to finish reviewing the series tomorrow.
>>
> Thanks!
>

BTW, I forgot to point you at this branch which may be useful to you if
you want to rebase your FP64 series on top:

https://cgit.freedesktop.org/~currojerez/mesa/log/?h=i965-ir-byte-units

>>> > 
>>> > > 
>>> > > Patches 47-57 go through the VEC4 back-end and address a number
>>> > > of
>>> > > issues that would arise in existing optimization passes with
>>> > > non-GRF-aligned regions, which will be useful for FP64
>>> > > support.  It's
>>> > > likely not complete and the handling of sub-GRF offsets doesn't
>>> > > attempt to be nearly as clever as the FS back-end, but they
>>> > > should
>>> > > make a substantial improvement over the current situation.
>>> > > 
>>> > > [PATCH 01/57] i965/fs: Replace fs_reg::reg_offset with
>>> > > fs_reg::offset
>>> > > expressed in bytes.
>>> > > [PATCH 02/57] i965/vec4: Replace dst/src_reg::reg_offset with
>>> > > dst/src_reg::offset expressed in bytes.
>>> > > [PATCH 03/57] i965/ir: Remove backend_reg::reg_offset.
>>> > > [PATCH 04/57] i965/fs: Replace fs_reg::subreg_offset with
>>> > > fs_reg::offset expressed in bytes.
>>> > > [PATCH 05/57] i965/fs: Add wrapper functions for
>>> > > fs_inst::regs_read
>>> > > and ::regs_written.
>>> > > [PATCH 06/57] i965/vec4: Add wrapper functions for
>>> > > vec4_instruction::regs_read and ::regs_written.
>>> > > [PATCH 

Re: [Mesa-dev] [PATCH 27/33] anv: Use blorp for CopyImageToBuffer

[Nanley Chery]

On Mon, Sep 12, 2016 at 12:45:51PM -0700, Jason Ekstrand wrote:
> On Mon, Sep 12, 2016 at 12:30 PM, Nanley Chery 
> wrote:
> 
> > On Wed, Aug 31, 2016 at 02:22:46PM -0700, Jason Ekstrand wrote:
> > > ---
> > >  src/intel/vulkan/anv_blorp.c | 134 ++
> > +
> > >  src/intel/vulkan/anv_meta_copy.c |  16 -
> > >  2 files changed, 134 insertions(+), 16 deletions(-)
> > >
> > > diff --git a/src/intel/vulkan/anv_blorp.c b/src/intel/vulkan/anv_blorp.c
> > > index 5d715fc..a838b55 100644
> > > --- a/src/intel/vulkan/anv_blorp.c
> > > +++ b/src/intel/vulkan/anv_blorp.c
> > > @@ -120,6 +120,38 @@ anv_device_finish_blorp(struct anv_device *device)
> > >  }
> > >
> > >  static void
> > > +get_blorp_surf_for_anv_buffer(struct anv_device *device,
> > > +  struct anv_buffer *buffer, uint64_t
> > offset,
> > > +  uint32_t width, uint32_t height,
> > > +  uint32_t row_pitch, enum isl_format
> > format,
> > > +  struct blorp_surf *blorp_surf,
> > > +  struct isl_surf *isl_surf)
> > > +{
> > > +   *blorp_surf = (struct blorp_surf) {
> > > +  .surf = isl_surf,
> > > +  .addr = {
> > > + .buffer = buffer->bo,
> > > + .offset = buffer->offset + offset,
> > > +  },
> > > +   };
> > > +
> > > +   isl_surf_init(>isl_dev, isl_surf,
> > > + .dim = ISL_SURF_DIM_2D,
> > > + .format = format,
> > > + .width = width,
> > > + .height = height,
> > > + .depth = 1,
> > > + .levels = 1,
> > > + .array_len = 1,
> > > + .samples = 1,
> > > + .min_pitch = row_pitch,
> >
> > I don't think we want to set the min_pitch field. If ISL creates a
> > surface with a pitch smaller than the required pitch, I think we'd
> > want to know about it rather than silently aligning up. If it does
> > get aligned up I wouldn't be confident that the HW will render or
> > texture from the image correctly. Just having the assertion would
> > provide such confidence whoever.
> >
> 
> This is one of the places where the blorp code and the old meta code
> differ.  The blorp code just creates an image with the actual width and
> height of the copy and pulls the row_pitch from bufferRowLength.
> 
> 

I forgot that bufferRowLength could be greater than the image's
width * block_size. Using min_pitch is in fact necessary.

> > > + .usage = ISL_SURF_USAGE_TEXTURE_BIT |
> > > +  ISL_SURF_USAGE_RENDER_TARGET_BIT,
> > > + .tiling_flags = ISL_TILING_LINEAR_BIT);
> > > +   assert(isl_surf->row_pitch == row_pitch);
> > > +}
> > > +
> > > +static void
> > >  get_blorp_surf_for_anv_image(const struct anv_image *image,
> > >   VkImageAspectFlags aspect,
> > >   struct blorp_surf *blorp_surf)
> > > @@ -136,6 +168,108 @@ get_blorp_surf_for_anv_image(const struct
> > anv_image *image,
> > > };
> > >  }
> > >
> > > +static void
> > > +copy_buffer_to_image(struct anv_cmd_buffer *cmd_buffer,
> > > + struct anv_buffer *anv_buffer,
> > > + struct anv_image *anv_image,
> > > + uint32_t regionCount,
> > > + const VkBufferImageCopy* pRegions,
> > > + bool buffer_to_image)
> > > +{
> > > +   struct blorp_batch batch;
> > > +   blorp_batch_init(_buffer->device->blorp, , cmd_buffer);
> > > +
> > > +   struct {
> > > +  struct blorp_surf surf;
> > > +  uint32_t level;
> > > +  VkOffset3D offset;
> > > +   } image, buffer, *src, *dst;
> > > +
> > > +   buffer.level = 0;
> > > +   buffer.offset = (VkOffset3D) { 0, 0, 0 };
> > > +
> > > +   if (buffer_to_image) {
> > > +  src = 
> > > +  dst = 
> > > +   } else {
> > > +  src = 
> > > +  dst = 
> > > +   }
> > > +
> > > +   for (unsigned r = 0; r < regionCount; r++) {
> > > +  const VkImageAspectFlags aspect = pRegions[r].imageSubresource.
> > aspectMask;
> > > +
> > > +  get_blorp_surf_for_anv_image(anv_image, aspect, );
> > > +  image.offset =
> > > + anv_sanitize_image_offset(anv_image->type,
> > pRegions[r].imageOffset);
> > > +  image.level = pRegions[r].imageSubresource.mipLevel;
> > > +
> > > +  VkExtent3D extent =
> > > + anv_sanitize_image_extent(anv_image->type,
> > pRegions[r].imageExtent);
> > > +  if (anv_image->type != VK_IMAGE_TYPE_3D) {
> > > + image.offset.z = pRegions[r].imageSubresource.baseArrayLayer;
> > > + extent.depth = pRegions[r].imageSubresource.layerCount;
> > > +  }
> >
> > Always making the image 3D is a great idea.
> >
> > > +
> > > +  const enum isl_format buffer_format =
> > > + anv_get_isl_format(_buffer->device->info,
> > 

[Mesa-dev] [PATCH] fixup! EGL: Implement the libglvnd interface for EGL.

[Kyle Brenneman]

Remove a couple of leftover hacks in the previous libglvnd patch.
---
 src/egl/main/egldispatchstubs.c | 17 +++--
 1 file changed, 3 insertions(+), 14 deletions(-)

diff --git a/src/egl/main/egldispatchstubs.c b/src/egl/main/egldispatchstubs.c
index 212a1fd..e02abd7 100644
--- a/src/egl/main/egldispatchstubs.c
+++ b/src/egl/main/egldispatchstubs.c
@@ -5,15 +5,6 @@
 
 #include "eglcurrent.h"
 
-// HACK: This should call the EGL_KHR_debug callback.
-static void
-_eglDebugReportFull(EGLenum error, const char *command, const char *funcName,
-  EGLint type, void *objectLabel, const char *message, ...)
-{
-_eglError(error, command);
-}
-#define EGL_DEBUG_MSG_ERROR_KHR 0
-
 static const __EGLapiExports *exports;
 
 const int __EGL_DISPATCH_FUNC_COUNT = __EGL_DISPATCH_COUNT;
@@ -72,8 +63,7 @@ static __eglMustCastToProperFunctionPointerType 
FetchVendorFunc(__EGLvendorInfo
 }
 if (func == NULL) {
 if (errorCode != EGL_SUCCESS) {
-_eglDebugReportFull(errorCode, __EGL_DISPATCH_FUNC_NAMES[index],
-__EGL_DISPATCH_FUNC_NAMES[index], EGL_DEBUG_MSG_ERROR_KHR, 
NULL, NULL);
+_eglError(errorCode, __EGL_DISPATCH_FUNC_NAMES[index]);
 }
 return NULL;
 }
@@ -81,8 +71,7 @@ static __eglMustCastToProperFunctionPointerType 
FetchVendorFunc(__EGLvendorInfo
 if (!exports->setLastVendor(vendor)) {
 // Don't bother trying to set an error code in libglvnd. If
 // setLastVendor failed, then setEGLError would also fail.
-_eglDebugReportFull(errorCode, __EGL_DISPATCH_FUNC_NAMES[index],
-__EGL_DISPATCH_FUNC_NAMES[index], EGL_DEBUG_MSG_ERROR_KHR, 
NULL, NULL);
+_eglError(errorCode, __EGL_DISPATCH_FUNC_NAMES[index]);
 return NULL;
 }
 
@@ -116,6 +105,6 @@ __eglMustCastToProperFunctionPointerType 
__eglDispatchFetchByDevice(EGLDeviceEXT
 
 exports->threadInit();
 vendor = exports->getVendorFromDevice(dev);
-return FetchVendorFunc(vendor, index, EGL_BAD_DISPLAY);
+return FetchVendorFunc(vendor, index, EGL_BAD_DEVICE_EXT);
 }
 
-- 
2.7.4

___
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Re: [Mesa-dev] [PATCH 27/33] anv: Use blorp for CopyImageToBuffer

[Jason Ekstrand]

On Mon, Sep 12, 2016 at 12:30 PM, Nanley Chery 
wrote:

> On Wed, Aug 31, 2016 at 02:22:46PM -0700, Jason Ekstrand wrote:
> > ---
> >  src/intel/vulkan/anv_blorp.c | 134 ++
> +
> >  src/intel/vulkan/anv_meta_copy.c |  16 -
> >  2 files changed, 134 insertions(+), 16 deletions(-)
> >
> > diff --git a/src/intel/vulkan/anv_blorp.c b/src/intel/vulkan/anv_blorp.c
> > index 5d715fc..a838b55 100644
> > --- a/src/intel/vulkan/anv_blorp.c
> > +++ b/src/intel/vulkan/anv_blorp.c
> > @@ -120,6 +120,38 @@ anv_device_finish_blorp(struct anv_device *device)
> >  }
> >
> >  static void
> > +get_blorp_surf_for_anv_buffer(struct anv_device *device,
> > +  struct anv_buffer *buffer, uint64_t
> offset,
> > +  uint32_t width, uint32_t height,
> > +  uint32_t row_pitch, enum isl_format
> format,
> > +  struct blorp_surf *blorp_surf,
> > +  struct isl_surf *isl_surf)
> > +{
> > +   *blorp_surf = (struct blorp_surf) {
> > +  .surf = isl_surf,
> > +  .addr = {
> > + .buffer = buffer->bo,
> > + .offset = buffer->offset + offset,
> > +  },
> > +   };
> > +
> > +   isl_surf_init(>isl_dev, isl_surf,
> > + .dim = ISL_SURF_DIM_2D,
> > + .format = format,
> > + .width = width,
> > + .height = height,
> > + .depth = 1,
> > + .levels = 1,
> > + .array_len = 1,
> > + .samples = 1,
> > + .min_pitch = row_pitch,
>
> I don't think we want to set the min_pitch field. If ISL creates a
> surface with a pitch smaller than the required pitch, I think we'd
> want to know about it rather than silently aligning up. If it does
> get aligned up I wouldn't be confident that the HW will render or
> texture from the image correctly. Just having the assertion would
> provide such confidence whoever.
>

This is one of the places where the blorp code and the old meta code
differ.  The blorp code just creates an image with the actual width and
height of the copy and pulls the row_pitch from bufferRowLength.


> > + .usage = ISL_SURF_USAGE_TEXTURE_BIT |
> > +  ISL_SURF_USAGE_RENDER_TARGET_BIT,
> > + .tiling_flags = ISL_TILING_LINEAR_BIT);
> > +   assert(isl_surf->row_pitch == row_pitch);
> > +}
> > +
> > +static void
> >  get_blorp_surf_for_anv_image(const struct anv_image *image,
> >   VkImageAspectFlags aspect,
> >   struct blorp_surf *blorp_surf)
> > @@ -136,6 +168,108 @@ get_blorp_surf_for_anv_image(const struct
> anv_image *image,
> > };
> >  }
> >
> > +static void
> > +copy_buffer_to_image(struct anv_cmd_buffer *cmd_buffer,
> > + struct anv_buffer *anv_buffer,
> > + struct anv_image *anv_image,
> > + uint32_t regionCount,
> > + const VkBufferImageCopy* pRegions,
> > + bool buffer_to_image)
> > +{
> > +   struct blorp_batch batch;
> > +   blorp_batch_init(_buffer->device->blorp, , cmd_buffer);
> > +
> > +   struct {
> > +  struct blorp_surf surf;
> > +  uint32_t level;
> > +  VkOffset3D offset;
> > +   } image, buffer, *src, *dst;
> > +
> > +   buffer.level = 0;
> > +   buffer.offset = (VkOffset3D) { 0, 0, 0 };
> > +
> > +   if (buffer_to_image) {
> > +  src = 
> > +  dst = 
> > +   } else {
> > +  src = 
> > +  dst = 
> > +   }
> > +
> > +   for (unsigned r = 0; r < regionCount; r++) {
> > +  const VkImageAspectFlags aspect = pRegions[r].imageSubresource.
> aspectMask;
> > +
> > +  get_blorp_surf_for_anv_image(anv_image, aspect, );
> > +  image.offset =
> > + anv_sanitize_image_offset(anv_image->type,
> pRegions[r].imageOffset);
> > +  image.level = pRegions[r].imageSubresource.mipLevel;
> > +
> > +  VkExtent3D extent =
> > + anv_sanitize_image_extent(anv_image->type,
> pRegions[r].imageExtent);
> > +  if (anv_image->type != VK_IMAGE_TYPE_3D) {
> > + image.offset.z = pRegions[r].imageSubresource.baseArrayLayer;
> > + extent.depth = pRegions[r].imageSubresource.layerCount;
> > +  }
>
> Always making the image 3D is a great idea.
>
> > +
> > +  const enum isl_format buffer_format =
> > + anv_get_isl_format(_buffer->device->info,
> anv_image->vk_format,
> > +aspect, VK_IMAGE_TILING_LINEAR);
> > +
> > +  const VkExtent3D bufferImageExtent = {
> > + .width  = pRegions[r].bufferRowLength ?
> > +   pRegions[r].bufferRowLength : extent.width,
> > + .height = pRegions[r].bufferImageHeight ?
> > +   pRegions[r].bufferImageHeight : extent.height,
> > +  };
> > +
> > +  const struct 

Re: [Mesa-dev] [PATCH] HUD: Add support for block I/O, network I/O and lmsensor stats

[Brian Paul]

Steven,

Can you enclose all the unix-specific parts in #ifdef PIPE_OS_UNIX to allow
this to build for Windows?

-Brian


On Mon, Sep 12, 2016 at 1:22 PM, Karol Herbst  wrote:

> Hey,
>
> nice work regarding the lmsensor bits. But I think it makes sense to
> also wire the power things in, cause we actually expose them within
> nouveau. Others might want or actually do the same as well.
>
> Many thanks
>
> 2016-09-12 20:33 GMT+02:00 Steven Toth :
> > Three new features:
> > 1. Disk/block I/O device read/write stats MB/ps.
> > 2. Network Interface RX/TX transfer statistics as a percentage
> >of the overall NIC speed.
> > 3. lmsensor power, voltage and temperature sensors.
> >
> > The lmsensor changes makes a dependency on libsensors so support
> > so the change is opt out by default.
> >
> > Signed-off-by: Steven Toth 
> > ---
> >  configure.ac |  20 ++
> >  src/gallium/auxiliary/Makefile.am|   4 +
> >  src/gallium/auxiliary/Makefile.sources   |   3 +
> >  src/gallium/auxiliary/hud/hud_context.c  |  67 
> >  src/gallium/auxiliary/hud/hud_diskstat.c | 331 
> >  src/gallium/auxiliary/hud/hud_nic.c  | 437
> +++
> >  src/gallium/auxiliary/hud/hud_private.h  |  23 ++
> >  src/gallium/auxiliary/hud/hud_sensors_temp.c | 374
> +++
> >  src/gallium/include/pipe/p_defines.h |   4 +
> >  9 files changed, 1263 insertions(+)
> >  create mode 100644 src/gallium/auxiliary/hud/hud_diskstat.c
> >  create mode 100644 src/gallium/auxiliary/hud/hud_nic.c
> >  create mode 100644 src/gallium/auxiliary/hud/hud_sensors_temp.c
> >
> > diff --git a/configure.ac b/configure.ac
> > index a413a3a..ef4671a 100644
> > --- a/configure.ac
> > +++ b/configure.ac
> > @@ -91,6 +91,7 @@ XCBGLX_REQUIRED=1.8.1
> >  XSHMFENCE_REQUIRED=1.1
> >  XVMC_REQUIRED=1.0.6
> >  PYTHON_MAKO_REQUIRED=0.8.0
> > +LIBSENSORS_REQUIRED=4.0.0
> >
> >  dnl Check for progs
> >  AC_PROG_CPP
> > @@ -871,6 +872,17 @@ AC_ARG_ENABLE([dri],
> >  [enable_dri="$enableval"],
> >  [enable_dri=yes])
> >
> > +#PKG_CHECK_MODULES([LIBSENSORS], [libsensors >= $LIBSENSORS_REQUIRED],
> [enable_lmsensors=yes], [enable_lmsensors=no])
> > +AC_ARG_ENABLE([lmsensors],
> > +[AS_HELP_STRING([--enable-lmsensors],
> > +[enable HUD lmsensor support @<:@default=disabled@:>@])],
> > +[enable_lmsensors="$enableval"],
> > +[enable_lmsensors=no])
> > +AM_CONDITIONAL(HAVE_LMSENSORS, test "x$enable_lmsensors" = xyes)
> > +if test "x$enable_lmsensors" = xyes ; then
> > +DEFINES="${DEFINES} -DHAVE_LMSENSORS=1"
> > +fi
> > +
> >  case "$host_os" in
> >  linux*)
> >  dri3_default=yes
> > @@ -1122,6 +1134,7 @@ AM_CONDITIONAL(HAVE_DRISW_KMS, test
> "x$have_drisw_kms" = xyes )
> >  AM_CONDITIONAL(HAVE_DRI2, test "x$enable_dri" = xyes -a
> "x$dri_platform" = xdrm -a "x$have_libdrm" = xyes )
> >  AM_CONDITIONAL(HAVE_DRI3, test "x$enable_dri3" = xyes -a
> "x$dri_platform" = xdrm -a "x$have_libdrm" = xyes )
> >  AM_CONDITIONAL(HAVE_APPLEDRI, test "x$enable_dri" = xyes -a
> "x$dri_platform" = xapple )
> > +AM_CONDITIONAL(HAVE_LMSENSORS, test "x$enable_lmsensors" = xyes )
> >
> >  AC_ARG_ENABLE([shared-glapi],
> >  [AS_HELP_STRING([--enable-shared-glapi],
> > @@ -2876,6 +2889,13 @@ else
> >  echo "Gallium: no"
> >  fi
> >
> > +echo ""
> > +if test "x$enable_lmsensors" != xyes; then
> > +echo "lmsensors:   no"
> > +else
> > +echo "lmsensors:   yes"
> > +fi
> > +
> >  dnl Shader cache
> >  echo ""
> >  echo "Shader cache:$enable_shader_cache"
> > diff --git a/src/gallium/auxiliary/Makefile.am b/src/gallium/auxiliary/
> Makefile.am
> > index d971a2b..4e77c9d 100644
> > --- a/src/gallium/auxiliary/Makefile.am
> > +++ b/src/gallium/auxiliary/Makefile.am
> > @@ -34,6 +34,10 @@ libgallium_la_SOURCES += \
> >
> >  endif
> >
> > +if HAVE_LMSENSORS
> > +libgallium_la_LDFLAGS = -lsensors
> > +endif
> > +
> >  MKDIR_GEN = $(AM_V_at)$(MKDIR_P) $(@D)
> >  PYTHON_GEN =  $(AM_V_GEN)$(PYTHON2) $(PYTHON_FLAGS)
> >
> > diff --git a/src/gallium/auxiliary/Makefile.sources
> b/src/gallium/auxiliary/Makefile.sources
> > index f8954c9..650a403 100644
> > --- a/src/gallium/auxiliary/Makefile.sources
> > +++ b/src/gallium/auxiliary/Makefile.sources
> > @@ -62,6 +62,9 @@ C_SOURCES := \
> > hud/hud_context.c \
> > hud/hud_context.h \
> > hud/hud_cpu.c \
> > +   hud/hud_nic.c \
> > +   hud/hud_diskstat.c \
> > +   hud/hud_sensors_temp.c \
> > hud/hud_driver_query.c \
> > hud/hud_fps.c \
> > hud/hud_private.h \
> > diff --git a/src/gallium/auxiliary/hud/hud_context.c
> b/src/gallium/auxiliary/hud/hud_context.c
> > index f1a1cee..a90103b 100644
> > --- a/src/gallium/auxiliary/hud/hud_context.c
> > +++ b/src/gallium/auxiliary/hud/hud_context.c
> > @@ -257,6 +257,10 @@ 

Re: [Mesa-dev] [PATCH 3/7] mesa/st: support lowering multi-planar YUV

[Rob Clark]

On Sat, Sep 10, 2016 at 10:04 AM, Roland Scheidegger  wrote:
> Am 09.09.2016 um 02:58 schrieb Rob Clark:
>> On Thu, Sep 8, 2016 at 8:28 PM, Roland Scheidegger  
>> wrote:
>>> Am 09.09.2016 um 02:19 schrieb Rob Clark:
 On Thu, Sep 8, 2016 at 7:54 PM, Rob Clark  wrote:
> On Thu, Sep 8, 2016 at 6:41 PM, Roland Scheidegger  
> wrote:
>> Am 08.09.2016 um 23:43 schrieb Rob Clark:
>>> On Thu, Sep 8, 2016 at 5:11 PM, Roland Scheidegger  
>>> wrote:
 Am 08.09.2016 um 22:30 schrieb Rob Clark:
> Support multi-planar YUV for external EGLImage's (currently just in 
> the
> dma-buf import path) by lowering to multiple texture fetch's for each
> plane and CSC in shader.
>
> Signed-off-by: Rob Clark 
> ---
>  src/gallium/auxiliary/util/u_inlines.h  |   4 +-
>  src/gallium/include/pipe/p_state.h  |   9 +++
>  src/gallium/include/state_tracker/st_api.h  |   3 +
>  src/gallium/state_trackers/dri/dri2.c   | 119 
> +++-
>  src/gallium/state_trackers/dri/dri_screen.c |  11 +++
>  src/mesa/main/mtypes.h  |  16 
>  src/mesa/program/ir_to_mesa.cpp |   1 +
>  src/mesa/state_tracker/st_atom_sampler.c|  41 +-
>  src/mesa/state_tracker/st_atom_shader.c |   3 +
>  src/mesa/state_tracker/st_atom_texture.c|  58 ++
>  src/mesa/state_tracker/st_cb_eglimage.c |  18 +
>  src/mesa/state_tracker/st_context.c |   7 +-
>  src/mesa/state_tracker/st_glsl_to_nir.cpp   |   1 +
>  src/mesa/state_tracker/st_glsl_to_tgsi.cpp  |   4 +
>  src/mesa/state_tracker/st_manager.c |   1 +
>  src/mesa/state_tracker/st_program.c |  35 
>  src/mesa/state_tracker/st_program.h |  37 +
>  src/mesa/state_tracker/st_texture.h |  21 +
>  18 files changed, 362 insertions(+), 27 deletions(-)
>
> diff --git a/src/gallium/auxiliary/util/u_inlines.h 
> b/src/gallium/auxiliary/util/u_inlines.h
> index c2a0b08..b7b8313 100644
> --- a/src/gallium/auxiliary/util/u_inlines.h
> +++ b/src/gallium/auxiliary/util/u_inlines.h
> @@ -136,8 +136,10 @@ pipe_resource_reference(struct pipe_resource 
> **ptr, struct pipe_resource *tex)
> struct pipe_resource *old_tex = *ptr;
>
> if (pipe_reference_described(&(*ptr)->reference, >reference,
> -
> (debug_reference_descriptor)debug_describe_resource))
> +
> (debug_reference_descriptor)debug_describe_resource)) {
> +  pipe_resource_reference(_tex->next, NULL);
>old_tex->screen->resource_destroy(old_tex->screen, old_tex);
> +   }
> *ptr = tex;
>  }
>
> diff --git a/src/gallium/include/pipe/p_state.h 
> b/src/gallium/include/pipe/p_state.h
> index ebd0337..4a88da6 100644
> --- a/src/gallium/include/pipe/p_state.h
> +++ b/src/gallium/include/pipe/p_state.h
> @@ -498,6 +498,15 @@ struct pipe_resource
>
> unsigned bind;/**< bitmask of PIPE_BIND_x */
> unsigned flags;   /**< bitmask of PIPE_RESOURCE_FLAG_x */
> +
> +   /**
> +* For planar images, ie. YUV EGLImage external, etc, pointer to 
> the
> +* next plane.
> +*
> +* TODO might be useful for dealing w/ z32s8 too, since at least a
> +* couple drivers split these out into separate buffers 
> internally.
> +*/
> +   struct pipe_resource *next;
 Would it be possible to stuff the multiple resources somewhere else
 (__DRIImage ?)? Seems a bit of a hack to have resources referencing
 other resources that way.
 (Also, it's odd since things are mostly lowered really outside of
 gallium so it's odd that some of the yuv state still sneaks in there.)
>>>
>>> I did originally start down the path of making __DRIImage have
>>> multiple pipe_resource's.. I'm not really sure that would end up
>>> better, and it certainly would be more invasive.
>>>
>>> Maybe we should just make that something like 'void *stpriv' to let st
>>> stick whatever it wants in there.  That seems more sane than making
>>> the st use a hashtable to map the rsc back to something else.
>>
>> Can't you just put 3 resources in somewhere without pointers?
>> I just think it really should be outside gallium interfaces. The
>> lowering is all done by the state 

Re: [Mesa-dev] [PATCH 27/33] anv: Use blorp for CopyImageToBuffer

[Nanley Chery]

On Wed, Aug 31, 2016 at 02:22:46PM -0700, Jason Ekstrand wrote:
> ---
>  src/intel/vulkan/anv_blorp.c | 134 
> +++
>  src/intel/vulkan/anv_meta_copy.c |  16 -
>  2 files changed, 134 insertions(+), 16 deletions(-)
> 
> diff --git a/src/intel/vulkan/anv_blorp.c b/src/intel/vulkan/anv_blorp.c
> index 5d715fc..a838b55 100644
> --- a/src/intel/vulkan/anv_blorp.c
> +++ b/src/intel/vulkan/anv_blorp.c
> @@ -120,6 +120,38 @@ anv_device_finish_blorp(struct anv_device *device)
>  }
>  
>  static void
> +get_blorp_surf_for_anv_buffer(struct anv_device *device,
> +  struct anv_buffer *buffer, uint64_t offset,
> +  uint32_t width, uint32_t height,
> +  uint32_t row_pitch, enum isl_format format,
> +  struct blorp_surf *blorp_surf,
> +  struct isl_surf *isl_surf)
> +{
> +   *blorp_surf = (struct blorp_surf) {
> +  .surf = isl_surf,
> +  .addr = {
> + .buffer = buffer->bo,
> + .offset = buffer->offset + offset,
> +  },
> +   };
> +
> +   isl_surf_init(>isl_dev, isl_surf,
> + .dim = ISL_SURF_DIM_2D,
> + .format = format,
> + .width = width,
> + .height = height,
> + .depth = 1,
> + .levels = 1,
> + .array_len = 1,
> + .samples = 1,
> + .min_pitch = row_pitch,

I don't think we want to set the min_pitch field. If ISL creates a
surface with a pitch smaller than the required pitch, I think we'd
want to know about it rather than silently aligning up. If it does
get aligned up I wouldn't be confident that the HW will render or
texture from the image correctly. Just having the assertion would
provide such confidence whoever.

> + .usage = ISL_SURF_USAGE_TEXTURE_BIT |
> +  ISL_SURF_USAGE_RENDER_TARGET_BIT,
> + .tiling_flags = ISL_TILING_LINEAR_BIT);
> +   assert(isl_surf->row_pitch == row_pitch);
> +}
> +
> +static void
>  get_blorp_surf_for_anv_image(const struct anv_image *image,
>   VkImageAspectFlags aspect,
>   struct blorp_surf *blorp_surf)
> @@ -136,6 +168,108 @@ get_blorp_surf_for_anv_image(const struct anv_image 
> *image,
> };
>  }
>  
> +static void
> +copy_buffer_to_image(struct anv_cmd_buffer *cmd_buffer,
> + struct anv_buffer *anv_buffer,
> + struct anv_image *anv_image,
> + uint32_t regionCount,
> + const VkBufferImageCopy* pRegions,
> + bool buffer_to_image)
> +{
> +   struct blorp_batch batch;
> +   blorp_batch_init(_buffer->device->blorp, , cmd_buffer);
> +
> +   struct {
> +  struct blorp_surf surf;
> +  uint32_t level;
> +  VkOffset3D offset;
> +   } image, buffer, *src, *dst;
> +
> +   buffer.level = 0;
> +   buffer.offset = (VkOffset3D) { 0, 0, 0 };
> +
> +   if (buffer_to_image) {
> +  src = 
> +  dst = 
> +   } else {
> +  src = 
> +  dst = 
> +   }
> +
> +   for (unsigned r = 0; r < regionCount; r++) {
> +  const VkImageAspectFlags aspect = 
> pRegions[r].imageSubresource.aspectMask;
> +
> +  get_blorp_surf_for_anv_image(anv_image, aspect, );
> +  image.offset =
> + anv_sanitize_image_offset(anv_image->type, pRegions[r].imageOffset);
> +  image.level = pRegions[r].imageSubresource.mipLevel;
> +
> +  VkExtent3D extent =
> + anv_sanitize_image_extent(anv_image->type, pRegions[r].imageExtent);
> +  if (anv_image->type != VK_IMAGE_TYPE_3D) {
> + image.offset.z = pRegions[r].imageSubresource.baseArrayLayer;
> + extent.depth = pRegions[r].imageSubresource.layerCount;
> +  }

Always making the image 3D is a great idea.

> +
> +  const enum isl_format buffer_format =
> + anv_get_isl_format(_buffer->device->info, anv_image->vk_format,
> +aspect, VK_IMAGE_TILING_LINEAR);
> +
> +  const VkExtent3D bufferImageExtent = {
> + .width  = pRegions[r].bufferRowLength ?
> +   pRegions[r].bufferRowLength : extent.width,
> + .height = pRegions[r].bufferImageHeight ?
> +   pRegions[r].bufferImageHeight : extent.height,
> +  };
> +
> +  const struct isl_format_layout *buffer_fmtl =
> + isl_format_get_layout(buffer_format);
> +
> +  const uint32_t buffer_row_pitch =
> + DIV_ROUND_UP(bufferImageExtent.width, buffer_fmtl->bw) *
> + (buffer_fmtl->bpb / 8);
> +
> +  const uint32_t buffer_layer_stride =
> + DIV_ROUND_UP(bufferImageExtent.height, buffer_fmtl->bh) *
> + buffer_row_pitch;
> +
> +  struct isl_surf buffer_isl_surf;
> +  get_blorp_surf_for_anv_buffer(cmd_buffer->device,
> +anv_buffer, 

Re: [Mesa-dev] [PATCH] HUD: Add support for block I/O, network I/O and lmsensor stats

[Karol Herbst]

Hey,

nice work regarding the lmsensor bits. But I think it makes sense to
also wire the power things in, cause we actually expose them within
nouveau. Others might want or actually do the same as well.

Many thanks

2016-09-12 20:33 GMT+02:00 Steven Toth :
> Three new features:
> 1. Disk/block I/O device read/write stats MB/ps.
> 2. Network Interface RX/TX transfer statistics as a percentage
>of the overall NIC speed.
> 3. lmsensor power, voltage and temperature sensors.
>
> The lmsensor changes makes a dependency on libsensors so support
> so the change is opt out by default.
>
> Signed-off-by: Steven Toth 
> ---
>  configure.ac |  20 ++
>  src/gallium/auxiliary/Makefile.am|   4 +
>  src/gallium/auxiliary/Makefile.sources   |   3 +
>  src/gallium/auxiliary/hud/hud_context.c  |  67 
>  src/gallium/auxiliary/hud/hud_diskstat.c | 331 
>  src/gallium/auxiliary/hud/hud_nic.c  | 437 
> +++
>  src/gallium/auxiliary/hud/hud_private.h  |  23 ++
>  src/gallium/auxiliary/hud/hud_sensors_temp.c | 374 +++
>  src/gallium/include/pipe/p_defines.h |   4 +
>  9 files changed, 1263 insertions(+)
>  create mode 100644 src/gallium/auxiliary/hud/hud_diskstat.c
>  create mode 100644 src/gallium/auxiliary/hud/hud_nic.c
>  create mode 100644 src/gallium/auxiliary/hud/hud_sensors_temp.c
>
> diff --git a/configure.ac b/configure.ac
> index a413a3a..ef4671a 100644
> --- a/configure.ac
> +++ b/configure.ac
> @@ -91,6 +91,7 @@ XCBGLX_REQUIRED=1.8.1
>  XSHMFENCE_REQUIRED=1.1
>  XVMC_REQUIRED=1.0.6
>  PYTHON_MAKO_REQUIRED=0.8.0
> +LIBSENSORS_REQUIRED=4.0.0
>
>  dnl Check for progs
>  AC_PROG_CPP
> @@ -871,6 +872,17 @@ AC_ARG_ENABLE([dri],
>  [enable_dri="$enableval"],
>  [enable_dri=yes])
>
> +#PKG_CHECK_MODULES([LIBSENSORS], [libsensors >= $LIBSENSORS_REQUIRED], 
> [enable_lmsensors=yes], [enable_lmsensors=no])
> +AC_ARG_ENABLE([lmsensors],
> +[AS_HELP_STRING([--enable-lmsensors],
> +[enable HUD lmsensor support @<:@default=disabled@:>@])],
> +[enable_lmsensors="$enableval"],
> +[enable_lmsensors=no])
> +AM_CONDITIONAL(HAVE_LMSENSORS, test "x$enable_lmsensors" = xyes)
> +if test "x$enable_lmsensors" = xyes ; then
> +DEFINES="${DEFINES} -DHAVE_LMSENSORS=1"
> +fi
> +
>  case "$host_os" in
>  linux*)
>  dri3_default=yes
> @@ -1122,6 +1134,7 @@ AM_CONDITIONAL(HAVE_DRISW_KMS, test "x$have_drisw_kms" 
> = xyes )
>  AM_CONDITIONAL(HAVE_DRI2, test "x$enable_dri" = xyes -a "x$dri_platform" = 
> xdrm -a "x$have_libdrm" = xyes )
>  AM_CONDITIONAL(HAVE_DRI3, test "x$enable_dri3" = xyes -a "x$dri_platform" = 
> xdrm -a "x$have_libdrm" = xyes )
>  AM_CONDITIONAL(HAVE_APPLEDRI, test "x$enable_dri" = xyes -a "x$dri_platform" 
> = xapple )
> +AM_CONDITIONAL(HAVE_LMSENSORS, test "x$enable_lmsensors" = xyes )
>
>  AC_ARG_ENABLE([shared-glapi],
>  [AS_HELP_STRING([--enable-shared-glapi],
> @@ -2876,6 +2889,13 @@ else
>  echo "Gallium: no"
>  fi
>
> +echo ""
> +if test "x$enable_lmsensors" != xyes; then
> +echo "lmsensors:   no"
> +else
> +echo "lmsensors:   yes"
> +fi
> +
>  dnl Shader cache
>  echo ""
>  echo "Shader cache:$enable_shader_cache"
> diff --git a/src/gallium/auxiliary/Makefile.am 
> b/src/gallium/auxiliary/Makefile.am
> index d971a2b..4e77c9d 100644
> --- a/src/gallium/auxiliary/Makefile.am
> +++ b/src/gallium/auxiliary/Makefile.am
> @@ -34,6 +34,10 @@ libgallium_la_SOURCES += \
>
>  endif
>
> +if HAVE_LMSENSORS
> +libgallium_la_LDFLAGS = -lsensors
> +endif
> +
>  MKDIR_GEN = $(AM_V_at)$(MKDIR_P) $(@D)
>  PYTHON_GEN =  $(AM_V_GEN)$(PYTHON2) $(PYTHON_FLAGS)
>
> diff --git a/src/gallium/auxiliary/Makefile.sources 
> b/src/gallium/auxiliary/Makefile.sources
> index f8954c9..650a403 100644
> --- a/src/gallium/auxiliary/Makefile.sources
> +++ b/src/gallium/auxiliary/Makefile.sources
> @@ -62,6 +62,9 @@ C_SOURCES := \
> hud/hud_context.c \
> hud/hud_context.h \
> hud/hud_cpu.c \
> +   hud/hud_nic.c \
> +   hud/hud_diskstat.c \
> +   hud/hud_sensors_temp.c \
> hud/hud_driver_query.c \
> hud/hud_fps.c \
> hud/hud_private.h \
> diff --git a/src/gallium/auxiliary/hud/hud_context.c 
> b/src/gallium/auxiliary/hud/hud_context.c
> index f1a1cee..a90103b 100644
> --- a/src/gallium/auxiliary/hud/hud_context.c
> +++ b/src/gallium/auxiliary/hud/hud_context.c
> @@ -257,6 +257,10 @@ number_to_human_readable(uint64_t num, uint64_t 
> max_value,
> static const char *hz_units[] =
>{" Hz", " KHz", " MHz", " GHz"};
> static const char *percent_units[] = {"%"};
> +   static const char *dbm_units[] = {" (-dBm)"};
> +   static const char *temperature_units[] = {" C"};
> +   static const char *volt_units[] = {" V"};
> +   static const char *amp_units[] = {" mA", " A"};
>
> const char **units;
> 

Re: [Mesa-dev] [PATCH 2/2] aubinator: print_help swap "FILE *file" with "bool critical"

[Kristian Høgsberg]

On Mon, Sep 12, 2016 at 4:59 AM, Emil Velikov  wrote:
> From: Emil Velikov 
>
> Derive file locally and exit() accordingly based on the bool.
> Allows us to save a couple lines of code.
>

If we're nit-picking, I'd rather just pass the exit code than a bool parameter.

Kristian

> Signed-off-by: Emil Velikov 
> ---
> s/print_help/print_help_and_exit/ and/or too bike sheddy ?
> ---
>  src/intel/tools/aubinator.c | 22 ++
>  1 file changed, 10 insertions(+), 12 deletions(-)
>
> diff --git a/src/intel/tools/aubinator.c b/src/intel/tools/aubinator.c
> index 9d29b68..e48ab3e 100644
> --- a/src/intel/tools/aubinator.c
> +++ b/src/intel/tools/aubinator.c
> @@ -1011,8 +1011,10 @@ setup_pager(void)
>  }
>
>  static void
> -print_help(const char *progname, FILE *file)
> +print_help(const char *progname, bool critical)
>  {
> +   FILE *file = critical ? stderr : stdout;
> +
> fprintf(file,
> "Usage: %s [OPTION]... FILE\n"
> "Decode aub file contents.\n\n"
> @@ -1025,6 +1027,7 @@ print_help(const char *progname, FILE *file)
> "  --no-pager  don't launch pager\n"
> "  --no-offsetsdon't print instruction offsets\n",
> progname);
> +   exit(critical ? EXIT_FAILURE : EXIT_SUCCESS);
>  }
>
>  static bool
> @@ -1054,10 +1057,8 @@ int main(int argc, char *argv[])
> const char *value;
> char gen_file[256], gen_val[24];
>
> -   if (argc == 1) {
> -  print_help(argv[0], stderr);
> -  exit(EXIT_FAILURE);
> -   }
> +   if (argc == 1)
> +  print_help(argv[0], true);
>
> for (i = 1; i < argc; ++i) {
>if (strcmp(argv[i], "--no-pager") == 0) {
> @@ -1087,8 +1088,7 @@ int main(int argc, char *argv[])
>  exit(EXIT_FAILURE);
>   }
>} else if (strcmp(argv[i], "--help") == 0) {
> - print_help(argv[0], stdout);
> - exit(EXIT_SUCCESS);
> + print_help(argv[0], false);
>} else {
>   if (argv[i][0] == '-') {
>  fprintf(stderr, "unknown option %s\n", argv[i]);
> @@ -1166,12 +1166,10 @@ int main(int argc, char *argv[])
> spec = gen_spec_load(gen_file);
> disasm = gen_disasm_create(pci_id);
>
> -   if (argv[i] == NULL) {
> -   print_help(argv[0], stderr);
> -   exit(EXIT_FAILURE);
> -   } else {
> +   if (argv[i] == NULL)
> +   print_help(argv[0], true);
> +   else
> file = aub_file_open(argv[i]);
> -   }
>
> while (aub_file_more_stuff(file))
>aub_file_decode_batch(file, spec);
> --
> 2.9.3
>
> ___
> mesa-dev mailing list
> mesa-dev@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/mesa-dev
___
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Re: [Mesa-dev] [PATCH v2 30.1/33] anv/blorp: Add a gcd_pow2_u64 helper and use it

[Nanley Chery]

On Mon, Sep 12, 2016 at 11:11:25AM -0700, Jason Ekstrand wrote:
> This is a lot cleaner and easier to read than the old piles of if
> statements.
> 
> Signed-off-by: Jason Ekstrand 
> ---
>  src/intel/vulkan/anv_blorp.c | 48 
> ++--
>  1 file changed, 24 insertions(+), 24 deletions(-)

Perhaps we should also mention that a bug is fixed here? Regardless,
with patch 30 fixed as discussed, patches 30 and 30.1 are,

Reviewed-by: Nanley Chery 

> 
> diff --git a/src/intel/vulkan/anv_blorp.c b/src/intel/vulkan/anv_blorp.c
> index 9a1c833..bc63c13 100644
> --- a/src/intel/vulkan/anv_blorp.c
> +++ b/src/intel/vulkan/anv_blorp.c
> @@ -537,6 +537,24 @@ do_buffer_copy(struct blorp_batch *batch,
>0, 0, 0, 0, width, height);
>  }
>  
> +/**
> + * Returns the greatest common divisor of a and b that is a power of two.
> + */
> +static inline uint64_t
> +gcd_pow2_u64(uint64_t a, uint64_t b)
> +{
> +   assert(a > 0 || b > 0);
> +
> +   unsigned a_log2 = ffsll(a) - 1;
> +   unsigned b_log2 = ffsll(b) - 1;
> +
> +   /* If either a or b is 0, then a_log2 or b_log2 till be UINT_MAX in which
> +* case, the MIN2() will take the other one.  If both are 0 then we will
> +* hit the assert above.
> +*/
> +   return 1 << MIN2(a_log2, b_log2);
> +}
> +
>  /* This is maximum possible width/height our HW can handle */
>  #define MAX_SURFACE_DIM (1ull << 14)
>  
> @@ -563,21 +581,9 @@ void anv_CmdCopyBuffer(
> * given offsets and size.
> */
>int bs = 16;
> -
> -  int fs = ffs(src_offset) - 1;
> -  if (fs != -1)
> - bs = MIN2(bs, 1 << fs);
> -  assert(src_offset % bs == 0);
> -
> -  fs = ffs(dst_offset) - 1;
> -  if (fs != -1)
> - bs = MIN2(bs, 1 << fs);
> -  assert(dst_offset % bs == 0);
> -
> -  fs = ffs(pRegions[r].size) - 1;
> -  if (fs != -1)
> - bs = MIN2(bs, 1 << fs);
> -  assert(pRegions[r].size % bs == 0);
> +  bs = gcd_pow2_u64(bs, src_offset);
> +  bs = gcd_pow2_u64(bs, dst_offset);
> +  bs = gcd_pow2_u64(bs, pRegions[r].size);
>  
>/* First, we make a bunch of max-sized copies */
>uint64_t max_copy_size = MAX_SURFACE_DIM * MAX_SURFACE_DIM * bs;
> @@ -643,15 +649,9 @@ void anv_CmdUpdateBuffer(
>  
>memcpy(tmp_data.map, pData, copy_size);
>  
> -  int bs;
> -  if ((copy_size & 15) == 0 && (dstOffset & 15) == 0) {
> - bs = 16;
> -  } else if ((copy_size & 7) == 0 && (dstOffset & 7) == 0) {
> - bs = 8;
> -  } else {
> - assert((copy_size & 3) == 0 && (dstOffset & 3) == 0);
> - bs = 4;
> -  }
> +  int bs = 16;
> +  bs = gcd_pow2_u64(bs, dstOffset);
> +  bs = gcd_pow2_u64(bs, copy_size);
>  
>do_buffer_copy(,
>   _buffer->device->dynamic_state_block_pool.bo,
> -- 
> 2.5.0.400.gff86faf
> 
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[Mesa-dev] [PATCH] HUD: Add support for block I/O, network I/O and lmsensor stats

[Steven Toth]

Three new features:
1. Disk/block I/O device read/write stats MB/ps.
2. Network Interface RX/TX transfer statistics as a percentage
   of the overall NIC speed.
3. lmsensor power, voltage and temperature sensors.

The lmsensor changes makes a dependency on libsensors so support
so the change is opt out by default.

Signed-off-by: Steven Toth 
---
 configure.ac |  20 ++
 src/gallium/auxiliary/Makefile.am|   4 +
 src/gallium/auxiliary/Makefile.sources   |   3 +
 src/gallium/auxiliary/hud/hud_context.c  |  67 
 src/gallium/auxiliary/hud/hud_diskstat.c | 331 
 src/gallium/auxiliary/hud/hud_nic.c  | 437 +++
 src/gallium/auxiliary/hud/hud_private.h  |  23 ++
 src/gallium/auxiliary/hud/hud_sensors_temp.c | 374 +++
 src/gallium/include/pipe/p_defines.h |   4 +
 9 files changed, 1263 insertions(+)
 create mode 100644 src/gallium/auxiliary/hud/hud_diskstat.c
 create mode 100644 src/gallium/auxiliary/hud/hud_nic.c
 create mode 100644 src/gallium/auxiliary/hud/hud_sensors_temp.c

diff --git a/configure.ac b/configure.ac
index a413a3a..ef4671a 100644
--- a/configure.ac
+++ b/configure.ac
@@ -91,6 +91,7 @@ XCBGLX_REQUIRED=1.8.1
 XSHMFENCE_REQUIRED=1.1
 XVMC_REQUIRED=1.0.6
 PYTHON_MAKO_REQUIRED=0.8.0
+LIBSENSORS_REQUIRED=4.0.0
 
 dnl Check for progs
 AC_PROG_CPP
@@ -871,6 +872,17 @@ AC_ARG_ENABLE([dri],
 [enable_dri="$enableval"],
 [enable_dri=yes])
 
+#PKG_CHECK_MODULES([LIBSENSORS], [libsensors >= $LIBSENSORS_REQUIRED], 
[enable_lmsensors=yes], [enable_lmsensors=no])
+AC_ARG_ENABLE([lmsensors],
+[AS_HELP_STRING([--enable-lmsensors],
+[enable HUD lmsensor support @<:@default=disabled@:>@])],
+[enable_lmsensors="$enableval"],
+[enable_lmsensors=no])
+AM_CONDITIONAL(HAVE_LMSENSORS, test "x$enable_lmsensors" = xyes)
+if test "x$enable_lmsensors" = xyes ; then
+DEFINES="${DEFINES} -DHAVE_LMSENSORS=1"
+fi
+
 case "$host_os" in
 linux*)
 dri3_default=yes
@@ -1122,6 +1134,7 @@ AM_CONDITIONAL(HAVE_DRISW_KMS, test "x$have_drisw_kms" = 
xyes )
 AM_CONDITIONAL(HAVE_DRI2, test "x$enable_dri" = xyes -a "x$dri_platform" = 
xdrm -a "x$have_libdrm" = xyes )
 AM_CONDITIONAL(HAVE_DRI3, test "x$enable_dri3" = xyes -a "x$dri_platform" = 
xdrm -a "x$have_libdrm" = xyes )
 AM_CONDITIONAL(HAVE_APPLEDRI, test "x$enable_dri" = xyes -a "x$dri_platform" = 
xapple )
+AM_CONDITIONAL(HAVE_LMSENSORS, test "x$enable_lmsensors" = xyes )
 
 AC_ARG_ENABLE([shared-glapi],
 [AS_HELP_STRING([--enable-shared-glapi],
@@ -2876,6 +2889,13 @@ else
 echo "Gallium: no"
 fi
 
+echo ""
+if test "x$enable_lmsensors" != xyes; then
+echo "lmsensors:   no"
+else
+echo "lmsensors:   yes"
+fi
+
 dnl Shader cache
 echo ""
 echo "Shader cache:$enable_shader_cache"
diff --git a/src/gallium/auxiliary/Makefile.am 
b/src/gallium/auxiliary/Makefile.am
index d971a2b..4e77c9d 100644
--- a/src/gallium/auxiliary/Makefile.am
+++ b/src/gallium/auxiliary/Makefile.am
@@ -34,6 +34,10 @@ libgallium_la_SOURCES += \
 
 endif
 
+if HAVE_LMSENSORS
+libgallium_la_LDFLAGS = -lsensors
+endif
+
 MKDIR_GEN = $(AM_V_at)$(MKDIR_P) $(@D)
 PYTHON_GEN =  $(AM_V_GEN)$(PYTHON2) $(PYTHON_FLAGS)
 
diff --git a/src/gallium/auxiliary/Makefile.sources 
b/src/gallium/auxiliary/Makefile.sources
index f8954c9..650a403 100644
--- a/src/gallium/auxiliary/Makefile.sources
+++ b/src/gallium/auxiliary/Makefile.sources
@@ -62,6 +62,9 @@ C_SOURCES := \
hud/hud_context.c \
hud/hud_context.h \
hud/hud_cpu.c \
+   hud/hud_nic.c \
+   hud/hud_diskstat.c \
+   hud/hud_sensors_temp.c \
hud/hud_driver_query.c \
hud/hud_fps.c \
hud/hud_private.h \
diff --git a/src/gallium/auxiliary/hud/hud_context.c 
b/src/gallium/auxiliary/hud/hud_context.c
index f1a1cee..a90103b 100644
--- a/src/gallium/auxiliary/hud/hud_context.c
+++ b/src/gallium/auxiliary/hud/hud_context.c
@@ -257,6 +257,10 @@ number_to_human_readable(uint64_t num, uint64_t max_value,
static const char *hz_units[] =
   {" Hz", " KHz", " MHz", " GHz"};
static const char *percent_units[] = {"%"};
+   static const char *dbm_units[] = {" (-dBm)"};
+   static const char *temperature_units[] = {" C"};
+   static const char *volt_units[] = {" V"};
+   static const char *amp_units[] = {" mA", " A"};
 
const char **units;
unsigned max_unit;
@@ -269,6 +273,22 @@ number_to_human_readable(uint64_t num, uint64_t max_value,
   max_unit = ARRAY_SIZE(time_units)-1;
   units = time_units;
   break;
+   case PIPE_DRIVER_QUERY_TYPE_VOLTS:
+  max_unit = ARRAY_SIZE(volt_units)-1;
+  units = volt_units;
+  break;
+   case PIPE_DRIVER_QUERY_TYPE_AMPS:
+  max_unit = ARRAY_SIZE(amp_units)-1;
+  units = amp_units;
+  break;
+   case PIPE_DRIVER_QUERY_TYPE_DBM:
+  max_unit = ARRAY_SIZE(dbm_units)-1;
+  units = 

[Mesa-dev] [PATCH v2 30.1/33] anv/blorp: Add a gcd_pow2_u64 helper and use it

[Jason Ekstrand]

This is a lot cleaner and easier to read than the old piles of if
statements.

Signed-off-by: Jason Ekstrand 
---
 src/intel/vulkan/anv_blorp.c | 48 ++--
 1 file changed, 24 insertions(+), 24 deletions(-)

diff --git a/src/intel/vulkan/anv_blorp.c b/src/intel/vulkan/anv_blorp.c
index 9a1c833..bc63c13 100644
--- a/src/intel/vulkan/anv_blorp.c
+++ b/src/intel/vulkan/anv_blorp.c
@@ -537,6 +537,24 @@ do_buffer_copy(struct blorp_batch *batch,
   0, 0, 0, 0, width, height);
 }
 
+/**
+ * Returns the greatest common divisor of a and b that is a power of two.
+ */
+static inline uint64_t
+gcd_pow2_u64(uint64_t a, uint64_t b)
+{
+   assert(a > 0 || b > 0);
+
+   unsigned a_log2 = ffsll(a) - 1;
+   unsigned b_log2 = ffsll(b) - 1;
+
+   /* If either a or b is 0, then a_log2 or b_log2 till be UINT_MAX in which
+* case, the MIN2() will take the other one.  If both are 0 then we will
+* hit the assert above.
+*/
+   return 1 << MIN2(a_log2, b_log2);
+}
+
 /* This is maximum possible width/height our HW can handle */
 #define MAX_SURFACE_DIM (1ull << 14)
 
@@ -563,21 +581,9 @@ void anv_CmdCopyBuffer(
* given offsets and size.
*/
   int bs = 16;
-
-  int fs = ffs(src_offset) - 1;
-  if (fs != -1)
- bs = MIN2(bs, 1 << fs);
-  assert(src_offset % bs == 0);
-
-  fs = ffs(dst_offset) - 1;
-  if (fs != -1)
- bs = MIN2(bs, 1 << fs);
-  assert(dst_offset % bs == 0);
-
-  fs = ffs(pRegions[r].size) - 1;
-  if (fs != -1)
- bs = MIN2(bs, 1 << fs);
-  assert(pRegions[r].size % bs == 0);
+  bs = gcd_pow2_u64(bs, src_offset);
+  bs = gcd_pow2_u64(bs, dst_offset);
+  bs = gcd_pow2_u64(bs, pRegions[r].size);
 
   /* First, we make a bunch of max-sized copies */
   uint64_t max_copy_size = MAX_SURFACE_DIM * MAX_SURFACE_DIM * bs;
@@ -643,15 +649,9 @@ void anv_CmdUpdateBuffer(
 
   memcpy(tmp_data.map, pData, copy_size);
 
-  int bs;
-  if ((copy_size & 15) == 0 && (dstOffset & 15) == 0) {
- bs = 16;
-  } else if ((copy_size & 7) == 0 && (dstOffset & 7) == 0) {
- bs = 8;
-  } else {
- assert((copy_size & 3) == 0 && (dstOffset & 3) == 0);
- bs = 4;
-  }
+  int bs = 16;
+  bs = gcd_pow2_u64(bs, dstOffset);
+  bs = gcd_pow2_u64(bs, copy_size);
 
   do_buffer_copy(,
  _buffer->device->dynamic_state_block_pool.bo,
-- 
2.5.0.400.gff86faf

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Re: [Mesa-dev] [PATCH 00/57] i965/ir: Switch representation of register offsets and sizes to byte units.

[Francisco Jerez]

Iago Toral  writes:

> On Fri, 2016-09-09 at 11:37 +0200, Iago Toral wrote:
>> On Thu, 2016-09-08 at 11:36 +0200, Iago Toral wrote:
>> > 
>> > On Wed, 2016-09-07 at 18:48 -0700, Francisco Jerez wrote:
>> > > 
>> > > 
>> > > This series reworks the representation of register region offsets
>> > > in
>> > > the i965 IR to be universally byte-based instead of the rather
>> > > awkward
>> > > split between reg_offset and subreg_offset we have in the FS
>> > > back-
>> > > end
>> > > right now, or the reg_offset field currently used in the VEC4 IR
>> > > which
>> > > doesn't allow better granularity than 32B.  The most immediate
>> > > motivation is to enable sub-GRF offsets in the VEC4 back-end,
>> > > which
>> > > will be useful for various kinds of lowering and instruction
>> > > splitting
>> > > required for FP64 support on VEC4 platforms.
>> > Thanks a lot for taking care of this!
>> > 
>> > > 
>> > > 
>> > > Patches 01-11 take care of scaling the regs_written and regs_read
>> > > instruction methods on both back-ends and the reg_offset register
>> > > field of VEC4 IR registers.  The fs_reg::reg_offset and
>> > > ::subreg_offset fields are also unified into a single register
>> > > field.
>> > > Because this part of the series is rather bulky I've tried to
>> > > keep
>> > > the
>> > > changes as obvious and functionally equivalent as possible at the
>> > > cost
>> > > of introducing not particularly clever code in some cases that
>> > > could
>> > > be simplified with some knowledge of the context.  Patches 31-46
>> > > make
>> > > a second pass through the code touched in the first part of the
>> > > series
>> > > in order to get rid of an amount of cruft.
>> > I have reviewed this part and intend to continue reviewing the rest
>> > in
>> > the following days. Might be a good idea to have another set of
>> > eyes
>> > reviewing the series or at least skimming through it just in case.
>> > 
>> > You might want to look at least at the second comment I made to
>> > patch
>> > 2
>> > and the comment to patch 7, since these might be actual problems.
>> > All
>> > other comments are minor things or small clarifications and you can
>> > ignore them if you want.
>> > 
>> > With the issues I point out in patches 2 and 7 addressed (or
>> > confirmation from your side that these are not real problems),
>> > patches
>> > 1-11 are:
>> > 
>> > Reviewed-by: Iago Toral Quiroga 
>> > 
>> > > 
>> > > 
>> > > Patches 12-30 address an amount of bugs that became obvious
>> > > during
>> > > the
>> > > conversion to byte units, some of them seem worrying enough that
>> > > it
>> > > might make sense to back-port them to stable releases.
>> I have just reviewed this part too and it looks good to me.
>> 
>> You probably want to look at least at the comment to patch 25, since
>> I
>> think that might be a genuine mistake. The comment to patch 27 points
>> out a possible problem (but even if it is a problem it is not really
>> related this patch set). I find patch 28 a bit confusing since it
>> seems
>> to be doing something that is not quite right and then fixing it in
>> patch 29, I may be misunderstanding what is going on there, but
>> otherwise I think it would be best to squash both together.
>> 
>> Other than these things, patches 12-31 are:
>> 
>> Reviewed-by: Iago Toral Quiroga 
>
> Patches 32-46 are:
>
> Reviewed-by: Iago Toral Quiroga 
>
> I hope to finish reviewing the series tomorrow.
>
Thanks!

>> > 
>> > > 
>> > > Patches 47-57 go through the VEC4 back-end and address a number
>> > > of
>> > > issues that would arise in existing optimization passes with
>> > > non-GRF-aligned regions, which will be useful for FP64
>> > > support.  It's
>> > > likely not complete and the handling of sub-GRF offsets doesn't
>> > > attempt to be nearly as clever as the FS back-end, but they
>> > > should
>> > > make a substantial improvement over the current situation.
>> > > 
>> > > [PATCH 01/57] i965/fs: Replace fs_reg::reg_offset with
>> > > fs_reg::offset
>> > > expressed in bytes.
>> > > [PATCH 02/57] i965/vec4: Replace dst/src_reg::reg_offset with
>> > > dst/src_reg::offset expressed in bytes.
>> > > [PATCH 03/57] i965/ir: Remove backend_reg::reg_offset.
>> > > [PATCH 04/57] i965/fs: Replace fs_reg::subreg_offset with
>> > > fs_reg::offset expressed in bytes.
>> > > [PATCH 05/57] i965/fs: Add wrapper functions for
>> > > fs_inst::regs_read
>> > > and ::regs_written.
>> > > [PATCH 06/57] i965/vec4: Add wrapper functions for
>> > > vec4_instruction::regs_read and ::regs_written.
>> > > [PATCH 07/57] i965/fs: Replace fs_inst::regs_written with
>> > > ::size_written field in bytes.
>> > > [PATCH 08/57] i965/vec4: Replace vec4_instruction::regs_written
>> > > with
>> > > ::size_written field in bytes.
>> > > [PATCH 09/57] i965/ir: Drop backend_instruction::regs_written
>> > > field.
>> > > [PATCH 10/57] i965/fs: Replace fs_inst::regs_read with
>> > > 

Re: [Mesa-dev] [PATCH 30/33] anv: Use blorp for CopyBuffer and UpdateBuffer

[Nanley Chery]

On Fri, Sep 09, 2016 at 07:25:46PM -0700, Jason Ekstrand wrote:
> On Fri, Sep 9, 2016 at 5:47 PM, Nanley Chery  wrote:
> 
> > On Wed, Aug 31, 2016 at 02:22:49PM -0700, Jason Ekstrand wrote:
> > > ---
> > >  src/intel/vulkan/Makefile.sources |   1 -
> > >  src/intel/vulkan/anv_blorp.c  | 184 ++
> > 
> > >  src/intel/vulkan/anv_meta_copy.c  | 180 --
> > ---
> > >  3 files changed, 184 insertions(+), 181 deletions(-)
> > >  delete mode 100644 src/intel/vulkan/anv_meta_copy.c
> > >
> > > diff --git a/src/intel/vulkan/Makefile.sources
> > b/src/intel/vulkan/Makefile.sources
> > > index 35e15f6..6c9853b 100644
> > > --- a/src/intel/vulkan/Makefile.sources
> > > +++ b/src/intel/vulkan/Makefile.sources
> > > @@ -35,7 +35,6 @@ VULKAN_FILES := \
> > >   anv_meta.h \
> > >   anv_meta_blit2d.c \
> > >   anv_meta_clear.c \
> > > - anv_meta_copy.c \
> > >   anv_meta_resolve.c \
> > >   anv_nir.h \
> > >   anv_nir_apply_dynamic_offsets.c \
> > > diff --git a/src/intel/vulkan/anv_blorp.c b/src/intel/vulkan/anv_blorp.c
> > > index 89ff3b3..e2b6672 100644
> > > --- a/src/intel/vulkan/anv_blorp.c
> > > +++ b/src/intel/vulkan/anv_blorp.c
> > > @@ -479,3 +479,187 @@ void anv_CmdBlitImage(
> > >
> > > blorp_batch_finish();
> > >  }
> > > +
> > > +static void
> > > +do_buffer_copy(struct blorp_batch *batch,
> > > +   struct anv_bo *src, uint64_t src_offset,
> > > +   struct anv_bo *dst, uint64_t dst_offset,
> > > +   int width, int height, int block_size)
> > > +{
> > > +   struct anv_device *device = batch->blorp->driver_ctx;
> > > +
> > > +   /* The actual format we pick doesn't matter as blorp will throw it
> > away.
> > > +* The only thing that actually matters is the size.
> > > +*/
> > > +   enum isl_format format;
> > > +   switch (block_size) {
> > > +   case 1:  format = ISL_FORMAT_R8_UINT;  break;
> > > +   case 2:  format = ISL_FORMAT_R8G8_UINT;break;
> > > +   case 4:  format = ISL_FORMAT_R8G8B8A8_UNORM;   break;
> > > +   case 8:  format = ISL_FORMAT_R16G16B16A16_UNORM;   break;
> > > +   case 16: format = ISL_FORMAT_R32G32B32A32_UINT;break;
> > > +   default:
> > > +  unreachable("Not a power-of-two format size");
> > > +   }
> > > +
> > > +   struct isl_surf surf;
> > > +   isl_surf_init(>isl_dev, ,
> > > + .dim = ISL_SURF_DIM_2D,
> > > + .format = format,
> > > + .width = width,
> > > + .height = height,
> > > + .depth = 1,
> > > + .levels = 1,
> > > + .array_len = 1,
> > > + .samples = 1,
> > > + .usage = ISL_SURF_USAGE_TEXTURE_BIT,
> >
> > Shouldn't we also OR in ISL_SURF_USAGE_RENDER_TARGET_BIT?
> >
> 
> Yes we should.
> 
> 
> > > + .tiling_flags = ISL_TILING_LINEAR_BIT);
> > > +   assert(surf.row_pitch == width * block_size);
> > > +
> > > +   struct blorp_surf src_blorp_surf = {
> > > +  .surf = ,
> > > +  .addr = {
> > > + .buffer = src,
> > > + .offset = src_offset,
> > > +  },
> > > +   };
> > > +
> > > +   struct blorp_surf dst_blorp_surf = {
> > > +  .surf = ,
> > > +  .addr = {
> > > + .buffer = dst,
> > > + .offset = dst_offset,
> > > +  },
> > > +   };
> > > +
> > > +   blorp_copy(batch, _blorp_surf, 0, 0, _blorp_surf, 0, 0,
> > > +  0, 0, 0, 0, width, height);
> > > +}
> > > +
> > > +void anv_CmdCopyBuffer(
> > > +VkCommandBuffer commandBuffer,
> > > +VkBuffersrcBuffer,
> > > +VkBufferdstBuffer,
> > > +uint32_tregionCount,
> > > +const VkBufferCopy* pRegions)
> > > +{
> > > +   ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
> > > +   ANV_FROM_HANDLE(anv_buffer, src_buffer, srcBuffer);
> > > +   ANV_FROM_HANDLE(anv_buffer, dst_buffer, dstBuffer);
> > > +
> > > +   struct blorp_batch batch;
> > > +   blorp_batch_init(_buffer->device->blorp, , cmd_buffer);
> > > +
> > > +   for (unsigned r = 0; r < regionCount; r++) {
> > > +  uint64_t src_offset = src_buffer->offset + pRegions[r].srcOffset;
> > > +  uint64_t dst_offset = dst_buffer->offset + pRegions[r].dstOffset;
> > > +  uint64_t copy_size = pRegions[r].size;
> > > +
> > > +  /* First, we compute the biggest format that can be used with the
> > > +   * given offsets and size.
> > > +   */
> > > +  int bs = 16;
> > > +
> > > +  int fs = ffs(src_offset) - 1;
> > > +  if (fs != -1)
> > > + bs = MIN2(bs, 1 << fs);
> > > +  assert(src_offset % bs == 0);
> >
> > I think we could replace this math and some math in
> > anv_CmdUpdateBuffer() with logic that's a bit simpler:
> >
> > /* Get the 

Re: [Mesa-dev] [PATCH v3] vl/dri3: handle the case of different GPU

[Nayan Deshmukh]

Hi Michel,


On Mon, Sep 12, 2016 at 7:02 PM, Leo Liu  wrote:

>
>
> On 09/12/2016 04:31 AM, Michel Dänzer wrote:
>
>> On 10/09/16 12:49 AM, Nayan Deshmukh wrote:
>>
>>> In case of prime when rendering is done on GPU other then the
>>> server GPU, use a seprate linear buffer for each back buffer
>>> which will be displayed using present extension.
>>>
>>> v2: Use a seprate linear buffer for each back buffer (Michel)
>>> v3: change variable names and fix coding style (Leo and Emil)
>>>
>>> Signed-off-by: Nayan Deshmukh 
>>>
>> [...]
>>
>> @@ -226,8 +232,7 @@ dri3_alloc_back_buffer(struct vl_dri3_screen *scrn)
>>> goto close_fd;
>>>memset(, 0, sizeof(templ));
>>> -   templ.bind = PIPE_BIND_RENDER_TARGET | PIPE_BIND_SAMPLER_VIEW |
>>> -PIPE_BIND_SCANOUT | PIPE_BIND_SHARED;
>>> +   templ.bind = PIPE_BIND_RENDER_TARGET;
>>>
>> I suspect PIPE_BIND_SAMPLER_VIEW is needed here as well, for when
>> resource_copy_region ends up being a textured draw operation.
>>
>>
>> I will add this.

> @@ -485,6 +513,16 @@ vl_dri3_flush_frontbuffer(struct pipe_screen *screen,
>>>   return;
>>>  }
>>>   +   if (scrn->is_different_gpu) {
>>> +  u_box_origin_2d(scrn->width, scrn->height, _box);
>>> +  scrn->pipe->resource_copy_region(scrn->pipe,
>>> +   back->linear_texture,
>>> +   0, 0, 0, 0,
>>> +   back->texture,
>>> +   0, _box);
>>> +
>>> +  scrn->pipe->flush(scrn->pipe, NULL, 0);
>>> +   }
>>>  xshmfence_reset(back->shm_fence);
>>>  back->busy = true;
>>>   @@ -699,6 +733,9 @@ vl_dri3_screen_create(Display *display, int screen)
>>>  if (!scrn->base.pscreen)
>>> goto release_pipe;
>>>   +   scrn->pipe = scrn->base.pscreen->context_cr
>>> eate(scrn->base.pscreen,
>>> +   >base, 0);
>>>
>> Hmm. AFAICT the callers of vl_dri3_flush_frontbuffer only flush their
>> own context after calling it. Is there any guarantee that the rendering
>> to back->texture is flushed before the resource_copy_region call above?
>>
> No.
>
> ST will call the flush that is only for copying to back buffer for
> presentation.
>
> Either the callers need to be changed to flush before calling
>> flush_frontbuffer, or the flush_frontbuffer hook might need to grow an
>> optional context parameter for this, similar to resource_get_handle.
>>
>>
>> vl_winsys_dri3 is used by vdpau and va, so I can make them flush before
calling
flush_frontbuffer. Adding a context argument will involve changes to a
lot of other files.

Regards,
Nayan.


> BTW, while looking into this, I noticed that vl_dri3_screen_create
>> overrides the pipe_screen flush_frontbuffer hook with
>> vl_dri3_flush_frontbuffer.
>>
>
> That's inherited from DRI2.
>
> Regards,
> Leo
>
>
>   That's a little ugly and would probably break
>> with drivers whose flush_frontbuffer hook actually does something. At
>> the very least, the vl_winsys_dri3.c code should save any previous hook
>> and call down to it from vl_dri3_flush_frontbuffer.
>>
>>
>>
>
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Re: [Mesa-dev] [PATCH v2 11/14] st/mesa: expose ARB_compute_variable_group_size

[Nicolai Hähnle]

On 12.09.2016 17:43, Samuel Pitoiset wrote:



On 09/12/2016 05:26 PM, Nicolai Hähnle wrote:



On 11.09.2016 20:45, Samuel Pitoiset wrote:

This extension is only exposed if the underlying driver supports
ARB_compute_shader and if PIPE_COMPUTE_MAX_VARIABLE_THREADS_PER_BLOCK
is set.

v2: - expose the ext based on that new cap

Signed-off-by: Samuel Pitoiset 
---
 src/mesa/state_tracker/st_extensions.c | 22 ++
 1 file changed, 22 insertions(+)

diff --git a/src/mesa/state_tracker/st_extensions.c
b/src/mesa/state_tracker/st_extensions.c
index 807fbfb..ad7c637 100644
--- a/src/mesa/state_tracker/st_extensions.c
+++ b/src/mesa/state_tracker/st_extensions.c
@@ -1196,6 +1196,28 @@ void st_init_extensions(struct pipe_screen
*screen,
  extensions->ARB_compute_shader =

extensions->ARB_shader_image_load_store &&

extensions->ARB_shader_atomic_counters;
+
+ if (extensions->ARB_compute_shader) {
+uint64_t max_variable_threads_per_block;
+
+screen->get_compute_param(screen, PIPE_SHADER_IR_TGSI,
+
PIPE_COMPUTE_CAP_MAX_VARIABLE_THREADS_PER_BLOCK,
+  _variable_threads_per_block);


I think this should check the return value. Or, in the earlier patch,
the handling in sp_screen.c needs to be changed. Not sure what the
convention should be, but as-is, using this with softpipe will not
initialize max_variable_threads_per_block.


I think we never check the return value of get_compute_param(). But
initializing max_variable_threads_per_block to 0 should actualy help,
what do you think?


Yes, that should work as well. Fine with me.

Cheers,
Nicolai





Nicolai


+
+for (i = 0; i < 3; i++) {
+   /* Clamp the values to avoid having a local work group
size
+* greater than the maximum number of invocations.
+*/
+   consts->MaxComputeVariableGroupSize[i] =
+  MIN2(consts->MaxComputeWorkGroupSize[i],
+   max_variable_threads_per_block);
+}
+consts->MaxComputeVariableGroupInvocations =
+   max_variable_threads_per_block;
+
+extensions->ARB_compute_variable_group_size =
+   max_variable_threads_per_block > 0;
+ }
   }
}





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Re: [Mesa-dev] [PATCH] glsl: remove interpolateAt* instructions for demoted inputs

[Marek Olšák]

On Mon, Sep 12, 2016 at 4:05 PM, Connor Abbott  wrote:
> Since demoted inputs become global variables, wouldn't it be more
> efficient to simply turn it into a straight assignment? Then the
> backend wouldn't have to initialize it to a constant (since it would
> be undefined).

Maybe, but there are no apps using these interp instructions, so it's
probably a waste of time trying to optimize for it.

Marek
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Re: [Mesa-dev] [PATCH 3/7] mesa/st: support lowering multi-planar YUV

[Marek Olšák]

On Mon, Sep 12, 2016 at 4:04 PM, Rob Clark  wrote:
> On Mon, Sep 12, 2016 at 9:01 AM, Marek Olšák  wrote:
>> On Thu, Sep 8, 2016 at 10:30 PM, Rob Clark  wrote:
>>> Support multi-planar YUV for external EGLImage's (currently just in the
>>> dma-buf import path) by lowering to multiple texture fetch's for each
>>> plane and CSC in shader.
>>>
>>> Signed-off-by: Rob Clark 
>>> ---
>>>  src/gallium/auxiliary/util/u_inlines.h  |   4 +-
>>>  src/gallium/include/pipe/p_state.h  |   9 +++
>>>  src/gallium/include/state_tracker/st_api.h  |   3 +
>>>  src/gallium/state_trackers/dri/dri2.c   | 119 
>>> +++-
>>>  src/gallium/state_trackers/dri/dri_screen.c |  11 +++
>>>  src/mesa/main/mtypes.h  |  16 
>>>  src/mesa/program/ir_to_mesa.cpp |   1 +
>>>  src/mesa/state_tracker/st_atom_sampler.c|  41 +-
>>>  src/mesa/state_tracker/st_atom_shader.c |   3 +
>>>  src/mesa/state_tracker/st_atom_texture.c|  58 ++
>>>  src/mesa/state_tracker/st_cb_eglimage.c |  18 +
>>>  src/mesa/state_tracker/st_context.c |   7 +-
>>>  src/mesa/state_tracker/st_glsl_to_nir.cpp   |   1 +
>>>  src/mesa/state_tracker/st_glsl_to_tgsi.cpp  |   4 +
>>>  src/mesa/state_tracker/st_manager.c |   1 +
>>>  src/mesa/state_tracker/st_program.c |  35 
>>>  src/mesa/state_tracker/st_program.h |  37 +
>>>  src/mesa/state_tracker/st_texture.h |  21 +
>>>  18 files changed, 362 insertions(+), 27 deletions(-)
>>>
>>> diff --git a/src/gallium/auxiliary/util/u_inlines.h 
>>> b/src/gallium/auxiliary/util/u_inlines.h
>>> index c2a0b08..b7b8313 100644
>>> --- a/src/gallium/auxiliary/util/u_inlines.h
>>> +++ b/src/gallium/auxiliary/util/u_inlines.h
>>> @@ -136,8 +136,10 @@ pipe_resource_reference(struct pipe_resource **ptr, 
>>> struct pipe_resource *tex)
>>> struct pipe_resource *old_tex = *ptr;
>>>
>>> if (pipe_reference_described(&(*ptr)->reference, >reference,
>>> -
>>> (debug_reference_descriptor)debug_describe_resource))
>>> +
>>> (debug_reference_descriptor)debug_describe_resource)) {
>>> +  pipe_resource_reference(_tex->next, NULL);
>>>old_tex->screen->resource_destroy(old_tex->screen, old_tex);
>>> +   }
>>> *ptr = tex;
>>>  }
>>>
>>> diff --git a/src/gallium/include/pipe/p_state.h 
>>> b/src/gallium/include/pipe/p_state.h
>>> index ebd0337..4a88da6 100644
>>> --- a/src/gallium/include/pipe/p_state.h
>>> +++ b/src/gallium/include/pipe/p_state.h
>>> @@ -498,6 +498,15 @@ struct pipe_resource
>>>
>>> unsigned bind;/**< bitmask of PIPE_BIND_x */
>>> unsigned flags;   /**< bitmask of PIPE_RESOURCE_FLAG_x */
>>> +
>>> +   /**
>>> +* For planar images, ie. YUV EGLImage external, etc, pointer to the
>>> +* next plane.
>>> +*
>>> +* TODO might be useful for dealing w/ z32s8 too, since at least a
>>> +* couple drivers split these out into separate buffers internally.
>>> +*/
>>
>> Please remove this TODO. Radeon can't do separate depth & stencil.
>> Yes, radeon allocates them separately, but they share the tiling mode
>> and HyperZ metadata, which is interleaved.
>>
>>> +   struct pipe_resource *next;
>>
>> How about this:
>> - pipe_resource::next will be removed.
>> - all planes will be backed by the same pipe_resource
>> - resource_from_handle will receive information about all planes.
>> (whatever you need)
>> - PIPE_FORMAT_XX_XX_XX_PLANAR will be added; replace XX with formats
>> of planes (define as many formats as you need)
>> - pipe_sampler_view::u::tex::first_layer will be used to select the plane.
>> - the driver will look at first_layer and the format and will set up
>> texture sampling from that plane
>>
>> What do you think?
>
>
> Hmm, this approach does end up needing some per-driver work, which I
> was hoping to avoid.. and I guess in the end support for most of the
> drivers will be needed: virtio/vc4/freedreno (linaro/aosp) and
> amdgpu/radeon/nouveau (android-x86).  It does sound like maybe less
> churn in mesa/st, but otoh more churn in all the drivers.  Plus having
> to re-work 'struct winsys_handle' to take an array of
> handle/stride/offset (and eventually modifier for tiled yuv, similar
> to how addfb2 works)..
>
> So it probably ends up being more churn than just making
> st_texture_object::pt an array (which I was going to try, time
> permitting, this week).
>
> On the plus side, maybe it would be easier for video state-trackers,
> although I think pipe_resource::next approach has the same advantage.

Well, it's up to you. I don't have a strong opinion either way.

Marek
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Re: [Mesa-dev] [PATCH 1/5] mesa: bump required GCC version to 4.8.0

[Jose Fonseca]

We're internally building and shipping Mesa compiled with GCC 4.4 (more 
specifically 4.4.3).


It's fine if you require GCC 4.8 on automake, but please leave support 
for GCC 4.4.x in SCons.


Jose

On 07/09/16 05:28, Timothy Arceri wrote:

The last time this was bumped we settled on 4.2.0 because OpenBSD
wasn't shipping anything greater than 4.2.1 (as that was the last
GPLv2 licensed version) however they have now imported llvm to
there base repo.

As far as I can tell the oldest distro still using a current version
of Mesa is Red Hat Enterprise Linux 6 which ships with 4.4.7. However
Dave reported that they build Mesa with GCC 4.8.

Cc: Jonathan Gray 
---
 configure.ac | 18 +++---
 include/c99_compat.h | 17 +++--
 2 files changed, 10 insertions(+), 25 deletions(-)

diff --git a/configure.ac b/configure.ac
index a413a3a..5128fc4 100644
--- a/configure.ac
+++ b/configure.ac
@@ -171,7 +171,6 @@ AC_MSG_RESULT([$acv_mesa_CLANG])
 dnl If we're using GCC, make sure that it is at least version 4.2.0.  Older
 dnl versions are explictly not supported.
 GEN_ASM_OFFSETS=no
-USE_GNU99=no
 if test "x$GCC" = xyes -a "x$acv_mesa_CLANG" = xno; then
 AC_MSG_CHECKING([whether gcc version is sufficient])
 major=0
@@ -183,16 +182,13 @@ if test "x$GCC" = xyes -a "x$acv_mesa_CLANG" = xno; then
 GCC_VERSION_MINOR=`echo $GCC_VERSION | cut -d. -f2`
 fi

-if test $GCC_VERSION_MAJOR -lt 4 -o $GCC_VERSION_MAJOR -eq 4 -a 
$GCC_VERSION_MINOR -lt 2 ; then
+if test $GCC_VERSION_MAJOR -lt 4 -o $GCC_VERSION_MAJOR -eq 4 -a 
$GCC_VERSION_MINOR -lt 8 ; then
 AC_MSG_RESULT([no])
-AC_MSG_ERROR([If using GCC, version 4.2.0 or later is required.])
+AC_MSG_ERROR([If using GCC, version 4.8.0 or later is required.])
 else
 AC_MSG_RESULT([yes])
 fi

-if test $GCC_VERSION_MAJOR -lt 4 -o $GCC_VERSION_MAJOR -eq 4 -a 
$GCC_VERSION_MINOR -lt 6 ; then
-USE_GNU99=yes
-fi
 if test "x$cross_compiling" = xyes; then
 GEN_ASM_OFFSETS=yes
 fi
@@ -269,12 +265,7 @@ AM_CONDITIONAL(HAVE_ANDROID, test "x$android" = xyes)
 dnl Add flags for gcc and g++
 if test "x$GCC" = xyes; then
 CFLAGS="$CFLAGS -Wall"
-
-if test "x$USE_GNU99" = xyes; then
-   CFLAGS="$CFLAGS -std=gnu99"
-else
-   CFLAGS="$CFLAGS -std=c99"
-fi
+CFLAGS="$CFLAGS -std=c99"

 # Enable -Werror=implicit-function-declaration and
 # -Werror=missing-prototypes, if available, or otherwise, just
@@ -401,9 +392,6 @@ AC_MSG_CHECKING(whether gcc supports -mpower8-vector)
 save_CFLAGS=$CFLAGS
 CFLAGS="$PWR8_CFLAGS $CFLAGS"
 AC_COMPILE_IFELSE([AC_LANG_SOURCE([[
-#if defined(__GNUC__) && (__GNUC__ < 4 || (__GNUC__ == 4 && __GNUC_MINOR__ < 
8))
-#error "Need GCC >= 4.8 for sane POWER8 support"
-#endif
 #include 
 int main () {
 vector unsigned char r;
diff --git a/include/c99_compat.h b/include/c99_compat.h
index 24e96e0..d76171c 100644
--- a/include/c99_compat.h
+++ b/include/c99_compat.h
@@ -145,8 +145,8 @@ test_c99_compat_h(const void * restrict a,
 #  endif

 #  ifdef __GNUC__
-#if __GNUC__ < 4 || (__GNUC__ == 4 && __GNUC_MINOR__ < 2)
-#  error "GCC version 4.2 or higher required"
+#if __GNUC__ < 4 || (__GNUC__ == 4 && __GNUC_MINOR__ < 8)
+#  error "GCC version 4.8 or higher required"
 #endif

  /* https://gcc.gnu.org/onlinedocs/gcc-4.2.4/gcc/Other-Builtins.html */
@@ -164,15 +164,12 @@ test_c99_compat_h(const void * restrict a,
 #define HAVE_FUNC_ATTRIBUTE_FORMAT 1
 #define HAVE_FUNC_ATTRIBUTE_PACKED 1

-#if __GNUC__ > 4 || (__GNUC__ == 4 && __GNUC_MINOR__ >= 3)
-   /* https://gcc.gnu.org/onlinedocs/gcc-4.3.6/gcc/Other-Builtins.html */
-#  define HAVE___BUILTIN_BSWAP32 1
-#  define HAVE___BUILTIN_BSWAP64 1
-#endif
+ /* https://gcc.gnu.org/onlinedocs/gcc-4.3.6/gcc/Other-Builtins.html */
+#define HAVE___BUILTIN_BSWAP32 1
+#define HAVE___BUILTIN_BSWAP64 1

-#if __GNUC__ > 4 || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5)
-#  define HAVE___BUILTIN_UNREACHABLE 1
-#endif
+ /* GCC 4.5 */
+#define HAVE___BUILTIN_UNREACHABLE 1

 #  endif /* __GNUC__ */




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Re: [Mesa-dev] [PATCH] Remove GL_GLEXT_PROTOTYPES guards from non-ext headers.

[Ilia Mirkin]

On Mon, Sep 12, 2016 at 11:55 AM, Emil Velikov  wrote:
> On 12 September 2016 at 15:35, Ilia Mirkin  wrote:
>> On Mon, Sep 12, 2016 at 10:10 AM, Emil Velikov  
>> wrote:
>>> Keeping diff/patches in git always felt like a hack, imho. Plus
>>> most/all(?) distros rely on the Mesa headers, so I'm not sure how that
>>> is going to work.
>>
>> The alternatives are considerably more painful for just a handful of
>> files with a small number of diffs. This would be as a tool for
>> developers like us who update the mesa versions by importing new KHR
>> versions, which will not have our local changes applied. The patch
>> would not be used as part of the build process or anything else.
>>
> The goal being to have the patches alongside the patched headers.
> This way one can use them as reference ? Sure sounds great imho.

Exactly. So that when I download new KHR headers, I just apply the
patch to them (and hope it applies), and if not, look at what was
being done and try to repeat the process. Then I regenerate the patch
against the (new) originals and check the whole thing in.

> Fwiw it may be that the EGL diff gets sorted sooner than expected /me
> crosses fingers.

OK. Well, your call. I'm definitely going to do it next time I update
headers (which will hopefully not be soon, given how much trouble it's
caused this time around).

  -ilia
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Re: [Mesa-dev] [Mesa-stable] [PATCH] gbm: fix potential NULL deref of mapImage/unmapImage.

[Emil Velikov]

On 12 September 2016 at 16:09, Weng, Chuanbo  wrote:
> Ping for review.
>
R-b and pushed to master.

Thanks for the reminder Chuanbo.
Emil
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Re: [Mesa-dev] [PATCH] Remove GL_GLEXT_PROTOTYPES guards from non-ext headers.

[Emil Velikov]

On 12 September 2016 at 15:35, Ilia Mirkin  wrote:
> On Mon, Sep 12, 2016 at 10:10 AM, Emil Velikov  
> wrote:
>> Keeping diff/patches in git always felt like a hack, imho. Plus
>> most/all(?) distros rely on the Mesa headers, so I'm not sure how that
>> is going to work.
>
> The alternatives are considerably more painful for just a handful of
> files with a small number of diffs. This would be as a tool for
> developers like us who update the mesa versions by importing new KHR
> versions, which will not have our local changes applied. The patch
> would not be used as part of the build process or anything else.
>
The goal being to have the patches alongside the patched headers.
This way one can use them as reference ? Sure sounds great imho.

Fwiw it may be that the EGL diff gets sorted sooner than expected /me
crosses fingers.

Thanks
Emil
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Re: [Mesa-dev] [PATCH] st/mesa: fix is_scissor_enabled when X/Y are negative

[Marek Olšák]

Reviewed-by: Marek Olšák 

Marek

On Sun, Sep 11, 2016 at 7:40 PM, Ilia Mirkin  wrote:
> Similar to commit 49c24d8a24 ("i965: fix noop_scissor range issue on
> width/height") - take the X/Y into account to determine whether the
> scissor covers the whole area or not.
>
> Fixes the recently-added gl-1.0-scissor-depth-clear-negative-xy piglit
> test.
>
> Signed-off-by: Ilia Mirkin 
> Cc: 
> ---
>  src/mesa/state_tracker/st_cb_clear.c | 10 ++
>  1 file changed, 6 insertions(+), 4 deletions(-)
>
> diff --git a/src/mesa/state_tracker/st_cb_clear.c 
> b/src/mesa/state_tracker/st_cb_clear.c
> index e70cba6..813ba9b 100644
> --- a/src/mesa/state_tracker/st_cb_clear.c
> +++ b/src/mesa/state_tracker/st_cb_clear.c
> @@ -313,11 +313,13 @@ clear_with_quad(struct gl_context *ctx, unsigned 
> clear_buffers)
>  static inline GLboolean
>  is_scissor_enabled(struct gl_context *ctx, struct gl_renderbuffer *rb)
>  {
> +   const struct gl_scissor_rect *scissor = >Scissor.ScissorArray[0];
> +
> return (ctx->Scissor.EnableFlags & 1) &&
> -  (ctx->Scissor.ScissorArray[0].X > 0 ||
> -   ctx->Scissor.ScissorArray[0].Y > 0 ||
> -   (unsigned) ctx->Scissor.ScissorArray[0].Width < rb->Width ||
> -   (unsigned) ctx->Scissor.ScissorArray[0].Height < rb->Height);
> +  (scissor->X > 0 ||
> +   scissor->Y > 0 ||
> +   scissor->X + scissor->Width < rb->Width ||
> +   scissor->Y + scissor->Height < rb->Height);
>  }
>
>  /**
> --
> 2.7.3
>
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Re: [Mesa-dev] [PATCH v2 11/14] st/mesa: expose ARB_compute_variable_group_size

[Samuel Pitoiset]

On 09/12/2016 05:26 PM, Nicolai Hähnle wrote:



On 11.09.2016 20:45, Samuel Pitoiset wrote:

This extension is only exposed if the underlying driver supports
ARB_compute_shader and if PIPE_COMPUTE_MAX_VARIABLE_THREADS_PER_BLOCK
is set.

v2: - expose the ext based on that new cap

Signed-off-by: Samuel Pitoiset 
---
 src/mesa/state_tracker/st_extensions.c | 22 ++
 1 file changed, 22 insertions(+)

diff --git a/src/mesa/state_tracker/st_extensions.c
b/src/mesa/state_tracker/st_extensions.c
index 807fbfb..ad7c637 100644
--- a/src/mesa/state_tracker/st_extensions.c
+++ b/src/mesa/state_tracker/st_extensions.c
@@ -1196,6 +1196,28 @@ void st_init_extensions(struct pipe_screen
*screen,
  extensions->ARB_compute_shader =

extensions->ARB_shader_image_load_store &&

extensions->ARB_shader_atomic_counters;
+
+ if (extensions->ARB_compute_shader) {
+uint64_t max_variable_threads_per_block;
+
+screen->get_compute_param(screen, PIPE_SHADER_IR_TGSI,
+
PIPE_COMPUTE_CAP_MAX_VARIABLE_THREADS_PER_BLOCK,
+  _variable_threads_per_block);


I think this should check the return value. Or, in the earlier patch,
the handling in sp_screen.c needs to be changed. Not sure what the
convention should be, but as-is, using this with softpipe will not
initialize max_variable_threads_per_block.


I think we never check the return value of get_compute_param(). But 
initializing max_variable_threads_per_block to 0 should actualy help, 
what do you think?




Nicolai


+
+for (i = 0; i < 3; i++) {
+   /* Clamp the values to avoid having a local work group
size
+* greater than the maximum number of invocations.
+*/
+   consts->MaxComputeVariableGroupSize[i] =
+  MIN2(consts->MaxComputeWorkGroupSize[i],
+   max_variable_threads_per_block);
+}
+consts->MaxComputeVariableGroupInvocations =
+   max_variable_threads_per_block;
+
+extensions->ARB_compute_variable_group_size =
+   max_variable_threads_per_block > 0;
+ }
   }
}




--
-Samuel
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Re: [Mesa-dev] [PATCH v2 08/14] gallium: add PIPE_COMPUTE_CAP_MAX_VARIABLE_THREADS_PER_BLOCK

[Samuel Pitoiset]

On 09/12/2016 05:19 PM, Nicolai Hähnle wrote:



On 11.09.2016 20:45, Samuel Pitoiset wrote:

Signed-off-by: Samuel Pitoiset 
---
 src/gallium/docs/source/screen.rst | 4 
 src/gallium/drivers/ilo/ilo_screen.c   | 2 ++
 src/gallium/drivers/nouveau/nv50/nv50_screen.c | 2 ++
 src/gallium/drivers/nouveau/nvc0/nvc0_screen.c | 2 ++
 src/gallium/drivers/radeon/r600_pipe_common.c  | 1 +
 src/gallium/drivers/softpipe/sp_screen.c   | 1 +
 src/gallium/include/pipe/p_defines.h   | 3 ++-
 7 files changed, 14 insertions(+), 1 deletion(-)

diff --git a/src/gallium/docs/source/screen.rst
b/src/gallium/docs/source/screen.rst
index 5dff650..cfc0a1b 100644
--- a/src/gallium/docs/source/screen.rst
+++ b/src/gallium/docs/source/screen.rst
@@ -498,6 +498,10 @@ pipe_screen::get_compute_param.
   threads. Also known as wavefront size, warp size or SIMD width.
 * ``PIPE_COMPUTE_CAP_ADDRESS_BITS``: The default compute device
address space
   size specified as an unsigned integer value in bits.
+* ``PIPE_COMPUTE_CAP_MAX_VARIABLE_THREADS_PER_BLOCK``: Maximum
variable number
+  of threads that a single block can contain. This is similar to
+  PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK, except that the variable
size is not
+  known a compile-time but at dispatch-time.

 .. _pipe_bind:

diff --git a/src/gallium/drivers/ilo/ilo_screen.c
b/src/gallium/drivers/ilo/ilo_screen.c
index b9e5ad6..85357fa 100644
--- a/src/gallium/drivers/ilo/ilo_screen.c
+++ b/src/gallium/drivers/ilo/ilo_screen.c
@@ -303,6 +303,8 @@ ilo_get_compute_param(struct pipe_screen *screen,
   ptr = _size;
   size = sizeof(val.subgroup_size);
   break;
+   case PIPE_COMPUTE_CAP_MAX_VARIABLE_THREADS_PER_BLOCK:
+  /* fallthrough */
default:
   ptr = NULL;
   size = 0;
diff --git a/src/gallium/drivers/nouveau/nv50/nv50_screen.c
b/src/gallium/drivers/nouveau/nv50/nv50_screen.c
index 1ec791d..6eb18ea 100644
--- a/src/gallium/drivers/nouveau/nv50/nv50_screen.c
+++ b/src/gallium/drivers/nouveau/nv50/nv50_screen.c
@@ -418,6 +418,8 @@ nv50_screen_get_compute_param(struct pipe_screen
*pscreen,
   RET((uint32_t []) { 512 }); /* FIXME: arbitrary limit */
case PIPE_COMPUTE_CAP_ADDRESS_BITS:
   RET((uint32_t []) { 32 });
+   case PIPE_COMPUTE_CAP_MAX_VARIABLE_THREADS_PER_BLOCK:
+  RET((uint64_t []) { 0 });
default:
   return 0;
}
diff --git a/src/gallium/drivers/nouveau/nvc0/nvc0_screen.c
b/src/gallium/drivers/nouveau/nvc0/nvc0_screen.c
index 1757cbb..df6c6af 100644
--- a/src/gallium/drivers/nouveau/nvc0/nvc0_screen.c
+++ b/src/gallium/drivers/nouveau/nvc0/nvc0_screen.c
@@ -478,6 +478,8 @@ nvc0_screen_get_compute_param(struct pipe_screen
*pscreen,
   RET((uint32_t []) { 512 }); /* FIXME: arbitrary limit */
case PIPE_COMPUTE_CAP_ADDRESS_BITS:
   RET((uint32_t []) { 64 });
+   case PIPE_COMPUTE_CAP_MAX_VARIABLE_THREADS_PER_BLOCK:
+  RET((uint64_t []) { 0 });
default:
   return 0;
}
diff --git a/src/gallium/drivers/radeon/r600_pipe_common.c
b/src/gallium/drivers/radeon/r600_pipe_common.c
index 6d7cc1b..a7c6729 100644
--- a/src/gallium/drivers/radeon/r600_pipe_common.c
+++ b/src/gallium/drivers/radeon/r600_pipe_common.c
@@ -955,6 +955,7 @@ static int r600_get_compute_param(struct
pipe_screen *screen,
 }
 return sizeof(uint32_t);
 case PIPE_COMPUTE_CAP_MAX_PRIVATE_SIZE:
+case PIPE_COMPUTE_CAP_MAX_VARIABLE_THREADS_PER_BLOCK:
 break; /* unused */


Add a separate case statement and return 0; instead, because the break
falls through to a fprintf(stderr, ...) statement.


Okay.



Cheers,
Nicolai


 case PIPE_COMPUTE_CAP_SUBGROUP_SIZE:
 if (ret) {
diff --git a/src/gallium/drivers/softpipe/sp_screen.c
b/src/gallium/drivers/softpipe/sp_screen.c
index cd4269f..29e898b 100644
--- a/src/gallium/drivers/softpipe/sp_screen.c
+++ b/src/gallium/drivers/softpipe/sp_screen.c
@@ -522,6 +522,7 @@ softpipe_get_compute_param(struct pipe_screen
*_screen,
case PIPE_COMPUTE_CAP_IMAGES_SUPPORTED:
case PIPE_COMPUTE_CAP_SUBGROUP_SIZE:
case PIPE_COMPUTE_CAP_ADDRESS_BITS:
+   case PIPE_COMPUTE_CAP_MAX_VARIABLE_THREADS_PER_BLOCK;
   break;
}
return 0;
diff --git a/src/gallium/include/pipe/p_defines.h
b/src/gallium/include/pipe/p_defines.h
index 88aa050..655995e 100644
--- a/src/gallium/include/pipe/p_defines.h
+++ b/src/gallium/include/pipe/p_defines.h
@@ -847,7 +847,8 @@ enum pipe_compute_cap
PIPE_COMPUTE_CAP_MAX_CLOCK_FREQUENCY,
PIPE_COMPUTE_CAP_MAX_COMPUTE_UNITS,
PIPE_COMPUTE_CAP_IMAGES_SUPPORTED,
-   PIPE_COMPUTE_CAP_SUBGROUP_SIZE
+   PIPE_COMPUTE_CAP_SUBGROUP_SIZE,
+   PIPE_COMPUTE_CAP_MAX_VARIABLE_THREADS_PER_BLOCK,
 };

 /**



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Re: [Mesa-dev] [PATCH v2 08/14] gallium: add PIPE_COMPUTE_CAP_MAX_VARIABLE_THREADS_PER_BLOCK

[Samuel Pitoiset]

On 09/12/2016 05:35 PM, Nicolai Hähnle wrote:

On 11.09.2016 20:45, Samuel Pitoiset wrote:

Signed-off-by: Samuel Pitoiset 
---
 src/gallium/docs/source/screen.rst | 4 
 src/gallium/drivers/ilo/ilo_screen.c   | 2 ++
 src/gallium/drivers/nouveau/nv50/nv50_screen.c | 2 ++
 src/gallium/drivers/nouveau/nvc0/nvc0_screen.c | 2 ++
 src/gallium/drivers/radeon/r600_pipe_common.c  | 1 +
 src/gallium/drivers/softpipe/sp_screen.c   | 1 +
 src/gallium/include/pipe/p_defines.h   | 3 ++-
 7 files changed, 14 insertions(+), 1 deletion(-)

diff --git a/src/gallium/docs/source/screen.rst
b/src/gallium/docs/source/screen.rst
index 5dff650..cfc0a1b 100644
--- a/src/gallium/docs/source/screen.rst
+++ b/src/gallium/docs/source/screen.rst
@@ -498,6 +498,10 @@ pipe_screen::get_compute_param.
   threads. Also known as wavefront size, warp size or SIMD width.
 * ``PIPE_COMPUTE_CAP_ADDRESS_BITS``: The default compute device
address space
   size specified as an unsigned integer value in bits.
+* ``PIPE_COMPUTE_CAP_MAX_VARIABLE_THREADS_PER_BLOCK``: Maximum
variable number
+  of threads that a single block can contain. This is similar to
+  PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK, except that the variable
size is not
+  known a compile-time but at dispatch-time.

 .. _pipe_bind:

diff --git a/src/gallium/drivers/ilo/ilo_screen.c
b/src/gallium/drivers/ilo/ilo_screen.c
index b9e5ad6..85357fa 100644
--- a/src/gallium/drivers/ilo/ilo_screen.c
+++ b/src/gallium/drivers/ilo/ilo_screen.c
@@ -303,6 +303,8 @@ ilo_get_compute_param(struct pipe_screen *screen,
   ptr = _size;
   size = sizeof(val.subgroup_size);
   break;
+   case PIPE_COMPUTE_CAP_MAX_VARIABLE_THREADS_PER_BLOCK:
+  /* fallthrough */
default:
   ptr = NULL;
   size = 0;
diff --git a/src/gallium/drivers/nouveau/nv50/nv50_screen.c
b/src/gallium/drivers/nouveau/nv50/nv50_screen.c
index 1ec791d..6eb18ea 100644
--- a/src/gallium/drivers/nouveau/nv50/nv50_screen.c
+++ b/src/gallium/drivers/nouveau/nv50/nv50_screen.c
@@ -418,6 +418,8 @@ nv50_screen_get_compute_param(struct pipe_screen
*pscreen,
   RET((uint32_t []) { 512 }); /* FIXME: arbitrary limit */
case PIPE_COMPUTE_CAP_ADDRESS_BITS:
   RET((uint32_t []) { 32 });
+   case PIPE_COMPUTE_CAP_MAX_VARIABLE_THREADS_PER_BLOCK:
+  RET((uint64_t []) { 0 });
default:
   return 0;
}
diff --git a/src/gallium/drivers/nouveau/nvc0/nvc0_screen.c
b/src/gallium/drivers/nouveau/nvc0/nvc0_screen.c
index 1757cbb..df6c6af 100644
--- a/src/gallium/drivers/nouveau/nvc0/nvc0_screen.c
+++ b/src/gallium/drivers/nouveau/nvc0/nvc0_screen.c
@@ -478,6 +478,8 @@ nvc0_screen_get_compute_param(struct pipe_screen
*pscreen,
   RET((uint32_t []) { 512 }); /* FIXME: arbitrary limit */
case PIPE_COMPUTE_CAP_ADDRESS_BITS:
   RET((uint32_t []) { 64 });
+   case PIPE_COMPUTE_CAP_MAX_VARIABLE_THREADS_PER_BLOCK:
+  RET((uint64_t []) { 0 });
default:
   return 0;
}
diff --git a/src/gallium/drivers/radeon/r600_pipe_common.c
b/src/gallium/drivers/radeon/r600_pipe_common.c
index 6d7cc1b..a7c6729 100644
--- a/src/gallium/drivers/radeon/r600_pipe_common.c
+++ b/src/gallium/drivers/radeon/r600_pipe_common.c
@@ -955,6 +955,7 @@ static int r600_get_compute_param(struct
pipe_screen *screen,
 }
 return sizeof(uint32_t);
 case PIPE_COMPUTE_CAP_MAX_PRIVATE_SIZE:
+case PIPE_COMPUTE_CAP_MAX_VARIABLE_THREADS_PER_BLOCK:
 break; /* unused */
 case PIPE_COMPUTE_CAP_SUBGROUP_SIZE:
 if (ret) {
diff --git a/src/gallium/drivers/softpipe/sp_screen.c
b/src/gallium/drivers/softpipe/sp_screen.c
index cd4269f..29e898b 100644
--- a/src/gallium/drivers/softpipe/sp_screen.c
+++ b/src/gallium/drivers/softpipe/sp_screen.c
@@ -522,6 +522,7 @@ softpipe_get_compute_param(struct pipe_screen
*_screen,
case PIPE_COMPUTE_CAP_IMAGES_SUPPORTED:
case PIPE_COMPUTE_CAP_SUBGROUP_SIZE:
case PIPE_COMPUTE_CAP_ADDRESS_BITS:
+   case PIPE_COMPUTE_CAP_MAX_VARIABLE_THREADS_PER_BLOCK;
   break;


Now that I'm actually trying to compile this: there's a semi-colon here ;p


Ooops...
I was sure to have added all the underlying drivers in my mesa build 
script, but it should be incorrect actually.

I will double check, sorry.



Nicolai


}
return 0;
diff --git a/src/gallium/include/pipe/p_defines.h
b/src/gallium/include/pipe/p_defines.h
index 88aa050..655995e 100644
--- a/src/gallium/include/pipe/p_defines.h
+++ b/src/gallium/include/pipe/p_defines.h
@@ -847,7 +847,8 @@ enum pipe_compute_cap
PIPE_COMPUTE_CAP_MAX_CLOCK_FREQUENCY,
PIPE_COMPUTE_CAP_MAX_COMPUTE_UNITS,
PIPE_COMPUTE_CAP_IMAGES_SUPPORTED,
-   PIPE_COMPUTE_CAP_SUBGROUP_SIZE
+   PIPE_COMPUTE_CAP_SUBGROUP_SIZE,
+   PIPE_COMPUTE_CAP_MAX_VARIABLE_THREADS_PER_BLOCK,
 };

 /**



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Re: [Mesa-dev] [PATCH v2 08/14] gallium: add PIPE_COMPUTE_CAP_MAX_VARIABLE_THREADS_PER_BLOCK

[Nicolai Hähnle]

On 11.09.2016 20:45, Samuel Pitoiset wrote:

Signed-off-by: Samuel Pitoiset 
---
 src/gallium/docs/source/screen.rst | 4 
 src/gallium/drivers/ilo/ilo_screen.c   | 2 ++
 src/gallium/drivers/nouveau/nv50/nv50_screen.c | 2 ++
 src/gallium/drivers/nouveau/nvc0/nvc0_screen.c | 2 ++
 src/gallium/drivers/radeon/r600_pipe_common.c  | 1 +
 src/gallium/drivers/softpipe/sp_screen.c   | 1 +
 src/gallium/include/pipe/p_defines.h   | 3 ++-
 7 files changed, 14 insertions(+), 1 deletion(-)

diff --git a/src/gallium/docs/source/screen.rst 
b/src/gallium/docs/source/screen.rst
index 5dff650..cfc0a1b 100644
--- a/src/gallium/docs/source/screen.rst
+++ b/src/gallium/docs/source/screen.rst
@@ -498,6 +498,10 @@ pipe_screen::get_compute_param.
   threads. Also known as wavefront size, warp size or SIMD width.
 * ``PIPE_COMPUTE_CAP_ADDRESS_BITS``: The default compute device address space
   size specified as an unsigned integer value in bits.
+* ``PIPE_COMPUTE_CAP_MAX_VARIABLE_THREADS_PER_BLOCK``: Maximum variable number
+  of threads that a single block can contain. This is similar to
+  PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK, except that the variable size is not
+  known a compile-time but at dispatch-time.

 .. _pipe_bind:

diff --git a/src/gallium/drivers/ilo/ilo_screen.c 
b/src/gallium/drivers/ilo/ilo_screen.c
index b9e5ad6..85357fa 100644
--- a/src/gallium/drivers/ilo/ilo_screen.c
+++ b/src/gallium/drivers/ilo/ilo_screen.c
@@ -303,6 +303,8 @@ ilo_get_compute_param(struct pipe_screen *screen,
   ptr = _size;
   size = sizeof(val.subgroup_size);
   break;
+   case PIPE_COMPUTE_CAP_MAX_VARIABLE_THREADS_PER_BLOCK:
+  /* fallthrough */
default:
   ptr = NULL;
   size = 0;
diff --git a/src/gallium/drivers/nouveau/nv50/nv50_screen.c 
b/src/gallium/drivers/nouveau/nv50/nv50_screen.c
index 1ec791d..6eb18ea 100644
--- a/src/gallium/drivers/nouveau/nv50/nv50_screen.c
+++ b/src/gallium/drivers/nouveau/nv50/nv50_screen.c
@@ -418,6 +418,8 @@ nv50_screen_get_compute_param(struct pipe_screen *pscreen,
   RET((uint32_t []) { 512 }); /* FIXME: arbitrary limit */
case PIPE_COMPUTE_CAP_ADDRESS_BITS:
   RET((uint32_t []) { 32 });
+   case PIPE_COMPUTE_CAP_MAX_VARIABLE_THREADS_PER_BLOCK:
+  RET((uint64_t []) { 0 });
default:
   return 0;
}
diff --git a/src/gallium/drivers/nouveau/nvc0/nvc0_screen.c 
b/src/gallium/drivers/nouveau/nvc0/nvc0_screen.c
index 1757cbb..df6c6af 100644
--- a/src/gallium/drivers/nouveau/nvc0/nvc0_screen.c
+++ b/src/gallium/drivers/nouveau/nvc0/nvc0_screen.c
@@ -478,6 +478,8 @@ nvc0_screen_get_compute_param(struct pipe_screen *pscreen,
   RET((uint32_t []) { 512 }); /* FIXME: arbitrary limit */
case PIPE_COMPUTE_CAP_ADDRESS_BITS:
   RET((uint32_t []) { 64 });
+   case PIPE_COMPUTE_CAP_MAX_VARIABLE_THREADS_PER_BLOCK:
+  RET((uint64_t []) { 0 });
default:
   return 0;
}
diff --git a/src/gallium/drivers/radeon/r600_pipe_common.c 
b/src/gallium/drivers/radeon/r600_pipe_common.c
index 6d7cc1b..a7c6729 100644
--- a/src/gallium/drivers/radeon/r600_pipe_common.c
+++ b/src/gallium/drivers/radeon/r600_pipe_common.c
@@ -955,6 +955,7 @@ static int r600_get_compute_param(struct pipe_screen 
*screen,
}
return sizeof(uint32_t);
case PIPE_COMPUTE_CAP_MAX_PRIVATE_SIZE:
+   case PIPE_COMPUTE_CAP_MAX_VARIABLE_THREADS_PER_BLOCK:
break; /* unused */
case PIPE_COMPUTE_CAP_SUBGROUP_SIZE:
if (ret) {
diff --git a/src/gallium/drivers/softpipe/sp_screen.c 
b/src/gallium/drivers/softpipe/sp_screen.c
index cd4269f..29e898b 100644
--- a/src/gallium/drivers/softpipe/sp_screen.c
+++ b/src/gallium/drivers/softpipe/sp_screen.c
@@ -522,6 +522,7 @@ softpipe_get_compute_param(struct pipe_screen *_screen,
case PIPE_COMPUTE_CAP_IMAGES_SUPPORTED:
case PIPE_COMPUTE_CAP_SUBGROUP_SIZE:
case PIPE_COMPUTE_CAP_ADDRESS_BITS:
+   case PIPE_COMPUTE_CAP_MAX_VARIABLE_THREADS_PER_BLOCK;
   break;


Now that I'm actually trying to compile this: there's a semi-colon here ;p

Nicolai


}
return 0;
diff --git a/src/gallium/include/pipe/p_defines.h 
b/src/gallium/include/pipe/p_defines.h
index 88aa050..655995e 100644
--- a/src/gallium/include/pipe/p_defines.h
+++ b/src/gallium/include/pipe/p_defines.h
@@ -847,7 +847,8 @@ enum pipe_compute_cap
PIPE_COMPUTE_CAP_MAX_CLOCK_FREQUENCY,
PIPE_COMPUTE_CAP_MAX_COMPUTE_UNITS,
PIPE_COMPUTE_CAP_IMAGES_SUPPORTED,
-   PIPE_COMPUTE_CAP_SUBGROUP_SIZE
+   PIPE_COMPUTE_CAP_SUBGROUP_SIZE,
+   PIPE_COMPUTE_CAP_MAX_VARIABLE_THREADS_PER_BLOCK,
 };

 /**


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Re: [Mesa-dev] [PATCH 1/2] i965: check for GL_TEXTURE_EXTERNAL_OES at miptree_create_for_teximage

[Jason Ekstrand]

Reviewed-by: Jason Ekstrand 

On Sat, Sep 10, 2016 at 3:07 PM, Alejandro Piñeiro 
wrote:

> Forgotten on commit "i965: Fix calculation of the image height at start
> level".
>
> Thanks to Ilia Mirkin for point it.
>
> Fixes the following regressions on Haswell and Broadwell:
> ES2-CTS.gtf.GL2ExtensionTests.egl_image_external.TestSimpleUnassociated
> (crash back to pass)
> ES2-CTS.gtf.GL2ExtensionTests.egl_image_external.TestSimple (crash back
> to fail)
> ES2-CTS.gtf.GL2ExtensionTests.egl_image_external.TestVertexShader (crash
> back to fail)
>
> https://bugs.freedesktop.org/show_bug.cgi?id=97761
> ---
>  src/mesa/drivers/dri/i965/intel_tex_image.c | 1 +
>  1 file changed, 1 insertion(+)
>
> diff --git a/src/mesa/drivers/dri/i965/intel_tex_image.c
> b/src/mesa/drivers/dri/i965/intel_tex_image.c
> index 65962eb..a012927 100644
> --- a/src/mesa/drivers/dri/i965/intel_tex_image.c
> +++ b/src/mesa/drivers/dri/i965/intel_tex_image.c
> @@ -51,6 +51,7 @@ intel_miptree_create_for_teximage(struct brw_context
> *brw,
> case GL_TEXTURE_2D_MULTISAMPLE:
> case GL_TEXTURE_2D_MULTISAMPLE_ARRAY:
> case GL_TEXTURE_RECTANGLE:
> +   case GL_TEXTURE_EXTERNAL_OES:
>assert(intelImage->base.Base.Level == 0);
>break;
> case GL_TEXTURE_3D:
> --
> 2.7.4
>
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Re: [Mesa-dev] [PATCH v2 11/14] st/mesa: expose ARB_compute_variable_group_size

[Nicolai Hähnle]

On 11.09.2016 20:45, Samuel Pitoiset wrote:

This extension is only exposed if the underlying driver supports
ARB_compute_shader and if PIPE_COMPUTE_MAX_VARIABLE_THREADS_PER_BLOCK
is set.

v2: - expose the ext based on that new cap

Signed-off-by: Samuel Pitoiset 
---
 src/mesa/state_tracker/st_extensions.c | 22 ++
 1 file changed, 22 insertions(+)

diff --git a/src/mesa/state_tracker/st_extensions.c 
b/src/mesa/state_tracker/st_extensions.c
index 807fbfb..ad7c637 100644
--- a/src/mesa/state_tracker/st_extensions.c
+++ b/src/mesa/state_tracker/st_extensions.c
@@ -1196,6 +1196,28 @@ void st_init_extensions(struct pipe_screen *screen,
  extensions->ARB_compute_shader =
   extensions->ARB_shader_image_load_store 
&&
   extensions->ARB_shader_atomic_counters;
+
+ if (extensions->ARB_compute_shader) {
+uint64_t max_variable_threads_per_block;
+
+screen->get_compute_param(screen, PIPE_SHADER_IR_TGSI,
+  
PIPE_COMPUTE_CAP_MAX_VARIABLE_THREADS_PER_BLOCK,
+  _variable_threads_per_block);


I think this should check the return value. Or, in the earlier patch, 
the handling in sp_screen.c needs to be changed. Not sure what the 
convention should be, but as-is, using this with softpipe will not 
initialize max_variable_threads_per_block.


Nicolai


+
+for (i = 0; i < 3; i++) {
+   /* Clamp the values to avoid having a local work group size
+* greater than the maximum number of invocations.
+*/
+   consts->MaxComputeVariableGroupSize[i] =
+  MIN2(consts->MaxComputeWorkGroupSize[i],
+   max_variable_threads_per_block);
+}
+consts->MaxComputeVariableGroupInvocations =
+   max_variable_threads_per_block;
+
+extensions->ARB_compute_variable_group_size =
+   max_variable_threads_per_block > 0;
+ }
   }
}



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[Mesa-dev] [Bug 34495] Selecting objects in Blender 2.56 slow due the software gl_select mode

[bugzilla-daemon]

https://bugs.freedesktop.org/show_bug.cgi?id=34495

Eero Tamminen  changed:

   What|Removed |Added

   See Also||https://bugs.freedesktop.or
   ||g/show_bug.cgi?id=62011

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Re: [Mesa-dev] EGL_EXT_*_drm - primary vs render node (Was Re: [Piglit] [PATCH 1/2] egl: Add sanity test for EGL_EXT_device_query (v3))

[James Jones]

On 09/12/2016 07:00 AM, Emil Velikov wrote:

Hi James,

On 8 September 2016 at 17:27, Emil Velikov  wrote:


In order to clear any ambiguity in EGL_EXT_device_drm we need to
"s/DRM driver./DRM driver which support KMS./". With that small change
things should be fine.



Further to the above (trivial) clarification can we update the spec to
mention that correct extension the Status section ?
Namely: s/functionality in EXT_dispay_device/functionality in EXT_device_query/


Yes, I will include this in the updates.

Thanks,
-James


Thanks
Emil


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Re: [Mesa-dev] [PATCH v2 08/14] gallium: add PIPE_COMPUTE_CAP_MAX_VARIABLE_THREADS_PER_BLOCK

[Nicolai Hähnle]

On 11.09.2016 20:45, Samuel Pitoiset wrote:

Signed-off-by: Samuel Pitoiset 
---
 src/gallium/docs/source/screen.rst | 4 
 src/gallium/drivers/ilo/ilo_screen.c   | 2 ++
 src/gallium/drivers/nouveau/nv50/nv50_screen.c | 2 ++
 src/gallium/drivers/nouveau/nvc0/nvc0_screen.c | 2 ++
 src/gallium/drivers/radeon/r600_pipe_common.c  | 1 +
 src/gallium/drivers/softpipe/sp_screen.c   | 1 +
 src/gallium/include/pipe/p_defines.h   | 3 ++-
 7 files changed, 14 insertions(+), 1 deletion(-)

diff --git a/src/gallium/docs/source/screen.rst 
b/src/gallium/docs/source/screen.rst
index 5dff650..cfc0a1b 100644
--- a/src/gallium/docs/source/screen.rst
+++ b/src/gallium/docs/source/screen.rst
@@ -498,6 +498,10 @@ pipe_screen::get_compute_param.
   threads. Also known as wavefront size, warp size or SIMD width.
 * ``PIPE_COMPUTE_CAP_ADDRESS_BITS``: The default compute device address space
   size specified as an unsigned integer value in bits.
+* ``PIPE_COMPUTE_CAP_MAX_VARIABLE_THREADS_PER_BLOCK``: Maximum variable number
+  of threads that a single block can contain. This is similar to
+  PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK, except that the variable size is not
+  known a compile-time but at dispatch-time.

 .. _pipe_bind:

diff --git a/src/gallium/drivers/ilo/ilo_screen.c 
b/src/gallium/drivers/ilo/ilo_screen.c
index b9e5ad6..85357fa 100644
--- a/src/gallium/drivers/ilo/ilo_screen.c
+++ b/src/gallium/drivers/ilo/ilo_screen.c
@@ -303,6 +303,8 @@ ilo_get_compute_param(struct pipe_screen *screen,
   ptr = _size;
   size = sizeof(val.subgroup_size);
   break;
+   case PIPE_COMPUTE_CAP_MAX_VARIABLE_THREADS_PER_BLOCK:
+  /* fallthrough */
default:
   ptr = NULL;
   size = 0;
diff --git a/src/gallium/drivers/nouveau/nv50/nv50_screen.c 
b/src/gallium/drivers/nouveau/nv50/nv50_screen.c
index 1ec791d..6eb18ea 100644
--- a/src/gallium/drivers/nouveau/nv50/nv50_screen.c
+++ b/src/gallium/drivers/nouveau/nv50/nv50_screen.c
@@ -418,6 +418,8 @@ nv50_screen_get_compute_param(struct pipe_screen *pscreen,
   RET((uint32_t []) { 512 }); /* FIXME: arbitrary limit */
case PIPE_COMPUTE_CAP_ADDRESS_BITS:
   RET((uint32_t []) { 32 });
+   case PIPE_COMPUTE_CAP_MAX_VARIABLE_THREADS_PER_BLOCK:
+  RET((uint64_t []) { 0 });
default:
   return 0;
}
diff --git a/src/gallium/drivers/nouveau/nvc0/nvc0_screen.c 
b/src/gallium/drivers/nouveau/nvc0/nvc0_screen.c
index 1757cbb..df6c6af 100644
--- a/src/gallium/drivers/nouveau/nvc0/nvc0_screen.c
+++ b/src/gallium/drivers/nouveau/nvc0/nvc0_screen.c
@@ -478,6 +478,8 @@ nvc0_screen_get_compute_param(struct pipe_screen *pscreen,
   RET((uint32_t []) { 512 }); /* FIXME: arbitrary limit */
case PIPE_COMPUTE_CAP_ADDRESS_BITS:
   RET((uint32_t []) { 64 });
+   case PIPE_COMPUTE_CAP_MAX_VARIABLE_THREADS_PER_BLOCK:
+  RET((uint64_t []) { 0 });
default:
   return 0;
}
diff --git a/src/gallium/drivers/radeon/r600_pipe_common.c 
b/src/gallium/drivers/radeon/r600_pipe_common.c
index 6d7cc1b..a7c6729 100644
--- a/src/gallium/drivers/radeon/r600_pipe_common.c
+++ b/src/gallium/drivers/radeon/r600_pipe_common.c
@@ -955,6 +955,7 @@ static int r600_get_compute_param(struct pipe_screen 
*screen,
}
return sizeof(uint32_t);
case PIPE_COMPUTE_CAP_MAX_PRIVATE_SIZE:
+   case PIPE_COMPUTE_CAP_MAX_VARIABLE_THREADS_PER_BLOCK:
break; /* unused */


Add a separate case statement and return 0; instead, because the break 
falls through to a fprintf(stderr, ...) statement.


Cheers,
Nicolai


case PIPE_COMPUTE_CAP_SUBGROUP_SIZE:
if (ret) {
diff --git a/src/gallium/drivers/softpipe/sp_screen.c 
b/src/gallium/drivers/softpipe/sp_screen.c
index cd4269f..29e898b 100644
--- a/src/gallium/drivers/softpipe/sp_screen.c
+++ b/src/gallium/drivers/softpipe/sp_screen.c
@@ -522,6 +522,7 @@ softpipe_get_compute_param(struct pipe_screen *_screen,
case PIPE_COMPUTE_CAP_IMAGES_SUPPORTED:
case PIPE_COMPUTE_CAP_SUBGROUP_SIZE:
case PIPE_COMPUTE_CAP_ADDRESS_BITS:
+   case PIPE_COMPUTE_CAP_MAX_VARIABLE_THREADS_PER_BLOCK;
   break;
}
return 0;
diff --git a/src/gallium/include/pipe/p_defines.h 
b/src/gallium/include/pipe/p_defines.h
index 88aa050..655995e 100644
--- a/src/gallium/include/pipe/p_defines.h
+++ b/src/gallium/include/pipe/p_defines.h
@@ -847,7 +847,8 @@ enum pipe_compute_cap
PIPE_COMPUTE_CAP_MAX_CLOCK_FREQUENCY,
PIPE_COMPUTE_CAP_MAX_COMPUTE_UNITS,
PIPE_COMPUTE_CAP_IMAGES_SUPPORTED,
-   PIPE_COMPUTE_CAP_SUBGROUP_SIZE
+   PIPE_COMPUTE_CAP_SUBGROUP_SIZE,
+   PIPE_COMPUTE_CAP_MAX_VARIABLE_THREADS_PER_BLOCK,
 };

 /**


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