[casper] Commissioning Scientist Positions at SKA (Aus)

[Francois Kapp]

Hi all,


There are a number of commissioning scientist positions available for SKA
Low - see link:
https://recruitment.skao.int/vacancy/commissioning-scientists-545230.html


Contact the SKAO for further information and feel free to pass on to others.


Regards,

Francois

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Re: [casper] Help with setting up RFSoC

[Francois Kapp]

Also look into whether your institution is registered under the Xilinx
University Program - if so, Xilinx are generally amenable to donating
licenses.

Cheers,
Francois

On Thu, Oct 5, 2023 at 3:13 AM Jack Hickish  wrote:

> I _think_ that's all you need.
>
> FYI - you can probably get a 30 day trial (or 90 in the case of sysgen)
> license for free, which should save you waiting for XUP.
>
> Cheers
> Jack
>
> On Thu, 5 Oct 2023 at 11:03, Heystek Grobler 
> wrote:
>
>> Hey Jack and Kaj.
>>
>> Thank you so much for the help and guidance. So the license I got with
>> the RFSoC ZSU111 does not contain the Xilinx ML Enterprise Edition and it
>> also does not contain SysGen.
>>
>> My University (The University of Pretoria) is reaching out to Xilinx to
>> buy the appropriate licence. Will it suffice if the University gets the
>> Xilinx ML Enterprise Edition and SysGen or should something else be added
>> to it?
>>
>> Thank you for the help!
>>
>> Heystek
>> -
>> Heystek Grobler
>>
>> 0832721009
>> heystekgrob...@gmail.com
>>
>>
>>
>> On Sun, Oct 1, 2023 at 6:09 PM Jack Hickish 
>> wrote:
>>
>>> I would suggest trying to get the new license. I'm suspect that Vivado
>>> 2020 supports the RFSoC chips you want (though I haven't checked) but using
>>> an older version than the toolflow suggests will almost certainly lead to
>>> other issues. Swimming against the CASPER version-tide is never a
>>> particularly fun thing to do :)
>>>
>>>
>>> On Sun, 1 Oct 2023 at 13:22, Heystek Grobler 
>>> wrote:
>>>
 Hey Jack.

 Should I then try to get a SysGen/ModelComposer license for 2021.1 or
 is there a way to still use Vivado 2020.06 with the RFSoC?

 Thank you for the help!

 Heystek

 -
 Heystek Grobler

 0832721009
 heystekgrob...@gmail.com


 On 01 Oct 2023, at 14:12, Jack Hickish  wrote:

 Not quite sure what to make of this, but I don't see anything for
 SysGen / ModelComposer newer than 2020.06, which wouldn't be valid with
 Vivado 2021.1

 On Sun, 1 Oct 2023 at 12:47, Heystek Grobler 
 wrote:

> Hey Jack.
>
> Thank you so much for the email.
>
> I have included screenshots of the licence manager below:
>
> 
>
> 
>
> 
>
> Do I need another/different licence from Xilinx or is there a way
> around this?
>
> Thank you for the help.
>
> Heystek
> -
> Heystek Grobler
>
> 0832721009
> heystekgrob...@gmail.com
>
>
>
> On Sun, Oct 1, 2023 at 1:10 PM Jack Hickish 
> wrote:
>
>> Hi Heystek,
>>
>> As the error in the diagnostic viewer suggests -- you don't seem to
>> have an appropriate sysgen license, in either the default search paths (I
>> think at least one of these is ~/.Xilinx/Xilinx.lic) or specified with an
>> environment variable. Do you think you have a license the system isn't
>> finding or is it possible you just need to get one from Xilinx?
>>
>> Also, the "Could not find Vitis installation" at the start of the
>> MATLAB prompt is concerning, but I don't think that's the current issue.
>>
>> Cheers
>> Jack
>>
>> On Sun, 1 Oct 2023 at 11:58, Heystek Grobler <
>> heystekgrob...@gmail.com> wrote:
>>
>>> Good day everyone.
>>>
>>> I hope that this email finds you well.
>>>
>>> I am used to working with a ROACH2 and have now started with an
>>> RFSoC ZCU111. I followed the instructions on the CASPER Read The Docs 
>>> Page and
>>> installed Ubuntu 20.04, Matlab 2021a and Vivado 2021.1.
>>>
>>> When I try to compile the first tutorial with jasper I get the
>>> following two errors (screenshots provided).
>>>
>>> 
>>>
>>> 
>>>
>>> Does anyone perhaps know how I can solve this?
>>>
>>> Thank you for the help.
>>>
>>> Heystek
>>>
>>>
>>> -
>>> Heystek Grobler
>>>
>>> 0832721009
>>> heystekgrob...@gmail.com
>>>
>>>
>>> --
>>> You received this message because you are subscribed to the Google
>>> Groups "casper@lists.berkeley.edu" group.
>>> To unsubscribe from this group and stop receiving emails from it,
>>> send an email to casper+unsubscr...@lists.berkeley.edu.
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>>> 
>>> .
>>>
>>
>> --
>> You received this 

[casper] Vacancy at OVRO

[Francois Kapp]

This is a little off-topic, but in case anyone is interested or aware of
someone who is, there is a vacancy at OVRO for a full time electronics
engineer: Position Description (taleo.net)


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[casper] Opportunity: Hosting of the CASPER 2023 Workshop

[Francois Kapp]

Dear Casperites,

Through a combination of (happy) circumstances, the opportunity to host the
2023 CASPER workshop has become available.  If you think your institution
might be interested, please get in touch with the advisory board via
casper-advisory-bo...@lists.berkeley.edu (cc'd), or me directly.

We would be happy to share the experience, effort, and benefits to hosting
this event.  Traditionally, the week long workshop is held early in the
second half of the calendar year, but scheduling is flexible and can be
selected to suit the host.

Please get in touch as soon as possible if you want more information - the
advisory board would like to make a decision within the next couple of
weeks if possible.

Regards,
Francois

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[casper] CASPER Workshop 2022 - Extension of Early Bird Registration

[Francois Kapp]

Hi all,

Thanks to all who have already registered to attend this year's CASPER
workshop in Sardinia.  It is exciting to be planning in-person events again
and we also welcome the people who have registered to attend remotely.

There were a few people who reported problems with the payment of the
registration fee for the workshop.  Our hosts have generously agreed to
extend the early bird pricing and it will be valid until July 10th 23.59,
Italian time.  The registration page is here:
https://sites.google.com/inaf.it/casper2022/home

If anyone has any problem with registration or payment, please email
i...@sardiniameeting.it to help resolve the issue.  Given that some
problems have occurred, it is recommended to do this as soon as possible to
avoid disappointment.

Regards,
Francois
On behalf of the advisory board and LOC

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Re: [casper] viability of VCU128 eval board as production CASPER instrument

[Francois Kapp]

Hi Jonathan et al,

To close an open question: At SARAO we do not intend to pursue a SKARAB2,
for the same cost inconsistency you mentioned.  Instead, we are
CASPER-ising Xilinx Alveo boards, which are intended for production, albeit
in a data centre environment.  Our intention is to further develop hybrid
FPGA/GPU correlators around these boards.  At the moment, as one would
expect, the GPU development leads the FPGA development.

Others, notably CSIRO for the SKA Low design, are also proposing Alveo in a
very CASPER-like architecture:
https://www.spiedigitallibrary.org/journals/Journal-of-Astronomical-Telescopes-Instruments-and-Systems/volume-8/issue-01/011018/Square-Kilometre-Array-Low-Atomic-commercial-off-the-shelf-correlator/10.1117/1.JATIS.8.1.011018.full
- perhaps our CSIRO colleagues can chime in there, but packing 20 Alveo
U55c's in a server looks like something viable, and it certainly reduces
the overhead of the host server per FPGA.

+F.





On Tue, 10 May 2022 at 00:35, Mitchell Burnett 
wrote:

> Hi Jonathan,
>
> To chime in under the “other” category…
>
> We have recently added six RFSoC platforms to CASPER. (Three Xilinx eval
> boards: ZCU111, ZCU216, ZCU208. The Xilinx education platform PYNQ RFSoC
> 2x2. Two boards from HiTech Global: HTG-ZRF16-29DR, and the 49DR version.)
>
> For ALPACA, we have used a couple ZCU111s, with the current plan to field
> 12 ZCU216’s in the final instrument. These are and will operate in a server
> room, so again, nothing extreme. Beyond our ALPACA project, I am aware of
> several folks that have all had success bringing up RFSoCs using Xilinx
> eval boards with CASPER tools (and others that are not immediately using
> CASPER tools, but are still using eval boards). So far, I have not
> experienced or heard of performance issues or failures with the
> ZC111/216/208. But, I am sure they exist and perhaps this brings those out.
> Because, with other Ultrascale+ parts, I have heard of anecdotes similar to
> yours where a significant qty. of eval boards were purchased for a wideband
> system with ~20% failure rate.
>
> Bringing up some boards with folks has been bumpy, but nothing attributed
> to the board. Those cases have mostly been needing to work out the
> documentation, and some strange outliers (like switching out an SD card
> from the one provided with the board).
>
> At least until now, I have had more issues with non-Xilinx RFSoC boards.
> But, that speaks more in general to the relationship with a vendor and what
> they support. Certainly, as pointed out, eval boards will not receive any
> guarantee and in our case we have just decided to knowingly assume that
> risk.
>
> In the end though, I just parrot much of what Jack said: I would try to
> avoid eval boards, but using them is viable and in scenarios like mine, if
> the project can take on and justify the risk then, OK. I believe SOMs are
> very promising to look for first, with more vendors providing options. When
> possible, choose vendors you have had a pretty good dialog about the
> requirements with clear support expectations. Negotiating prices will be
> tough (certainly with how supply is right now).
>
> Don’t think I really added much to the conversation, just another data
> point for you.
>
> Best,
>
> Mitch
>
> On May 9, 2022, at 12:56 PM, Jonathon Kocz  wrote:
>
> Hi Jonathan,
>
> A couple of follow up questions (sorry for getting into nitty gritty you
> wanted to avoid!):
>
> 1) Are you actually using the HBM? You can get much cheaper FPGAs with
> similar DSP/BRAM resources without HBM (if you are using HBM, are you doing
> this via CASPER?!)
> 2) I've been using the VCU128 a bit - I'm working on a couple of projects
> with your ADC board now. I've not found any issues (yet!) with loading of
> code on power up, or with the 1Gb coming up - though I note that the 1Gb
> CASPER core for the VCU128 doesn't work properly (an init issue, it's on my
> list to fix that in the next couple of weeks). - Which set of libraries are
> you using, or are you working outside CASPER?
> 3) On the CASPER conference/busy week front: With the 100Gb, is that also
> a CASPER core? We currently have at least two in the CASPER libraries, and
> part of the busy week I want to try to either integrate or find a use case
> where one might use one or the other to reduce confusion for users - if you
> have a third (and it's open source) it would be good to merge that in as
> well!
>
> In terms of eval boards in general:
>
> I've fielded a few VCU128s and they're fine, but we're not running them in
> an extreme environment - just in labs / server rooms. I've previously had
> issues with other eval boards when trying to use them to maximum capacity -
> as Dan said, they're not really designed for it.
>
> In terms of other boards - which should be merged into the main branch
> after the busy week:
>
> We've put the HiTech Global HTG940 and HTG9200 boards into the CASPER
> library if either of those was useful.
>
> I 

[casper] CASPER Advisory Board

[Francois Kapp]

Dear casperites,

As we gradually emerge from the 2 year pandemic imposed hiatus of almost
everything, this is a long overdue message to announce that I have taken
over as chair of the CASPER advisory board from Jack Hickish.  I want to
take this opportunity to thank Jack for the years that he was the chair and
all the fantastic work that he has done for CASPER.

We are also looking for nominations for some new members of the Advisory
Board.  We encourage diversity in membership in as many dimensions as
feasible.  Please submit nominations to me or to any of the other current
Advisory Board members that you know.  You can find the current members
here: https://casper.berkeley.edu/index.php/about/casper-advisory-board/

A nomination should be accompanied by a brief motivation that at least
includes the rationale for the nomination, and preferably sufficient
information for the Advisory Board to make a decision.  If necessary, we
will seek additional information regarding nominees - either from the
person who nominated them or via any other reasonable means.

We are looking forward to the next workshop to be hosted in Sardinia from 5
- 9 September 2022 - hopefully many of us will be able to attend in person.

As always, it bears reminding that CASPER is a collection of volunteers,
often contributing to the collaboration in their personal capacity, after
hours, over weekends, or whenever there is a spare moment.  Please continue
to respect this and be mindful of increasing the workload that these
volunteers need to juggle.  If you are in any doubt whatsoever about the
code of conduct that is expected, you can read the document here:
https://casper.berkeley.edu/index.php/code-of-conduct/

I welcome any input from the community, but please send it to me directly
to respect the inboxes of everyone on the list.  I will also try to keep
communication to a minimum, while recognising we probably undershot that
mark in recent months.  I would also like to remind the community that we
have a means of receiving anonymous information, should that be necessary,
via a Google Form here: https://goo.gl/forms/u7rNWXrOfJc6DFcf2

On behalf of the CASPER Advisory Board,
Francois

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Re: [casper] ROACH-2: Identifying Spurs in FFT of Noise Spectrum

[Francois Kapp]

Hi Benjamin,

I haven't read the full thread, so not sure if you detailed sampling
frequencies, etc., but in our testing of ROACH and ROACH2, we found the
biggest culprit to be a bus signal that never leaves the PowerPC, and (if
memory serves) causes the biggest spur at 133 MHz (and of course
harmonics).  Depending on where these fall in your band, you may get
interplay between interleaving artefacts and real interferers.

Regards,
Francois

On Fri, 9 Apr 2021 at 08:14, Clifford van Dyk 
wrote:

> Hi Benjamin
>
> When presented with a pure tone input, INL usually exhibits as a few
> low-order (2nd, 3rd harmonic) spurs in a spectrum, that can be reduced by
> high dither levels (in the order of half you ADCs usable dynamic range).
> DNL, on the other hand, typically exhibits as many high order spurs (many
> higher harmonics that alias back) that can be reduced by dither in the
> order of your quantisation step size. Its easy to appreciate this by
> considering a polynomial expansion of the ADCs transfer function - the ADCs
> staircase requires many terms (=high order harmonics) to represent
> accurately by polynomial expansion, whereas INL can be represented by just
> a few terms. It is therefore not surprising to me that you could not solve
> the many spurs by injecting a large scale sinusoidal dither - they are not
> typically caused by INL.
>
> Certain combinations of signal frequency to sample clock frequency or
> signal amplitude to quantisation level can result in apparent periodicity
> in the resultant digitized signal rather than noise that is evenly
> distributed in the spectrum.
>
> It is possible to produce clean spectra to well below -110 dBFS using
> lower sample rate, higher linearity ADCs and low input signal level (50 ohm
> terminated inputs), but when presented with a near Fs signals, linearity
> inevitably becomes the limit on dynamic range/sensitivity due to DNL and
> quantisation effects. I can send you some plots of what we have achieved
> with 16-bit ADCs (at far lower sample rates) if you are interested.
>
> Kind regards,
> Clifford
>
> On Fri, 09 Apr 2021, 03:17 'Benjamin Godfrey' via
> casper@lists.berkeley.edu,  wrote:
>
>> Thank you everyone for all the great input. I haven't been able to try
>> anything substantive yet but I definitely have a laundry list of things to
>> try.
>>
>> Clifford: I've done signal injection tests with sinusoids and seen
>> similar spurs but haven't done a careful check to ensure that the injected
>> signal doesn't have harmonics and things on it. Same goes with
>> investigating the clock. I have a commercial spectrum analyzer that I use
>> to check both of those. You're also right that the ADC isn't shielded from
>> the ROACH (at least with a Faraday shield).
>>
>> On the dither front, I tried measuring the INL of the ADC using the known
>> pdf of a sine wave. This was then used to create a lookup table that I
>> applied to the time-series data before taking the FFT. Unfortunately, it
>> didn't do a whole lot to the spurs. My setup for looking at these spurs
>> (and my result) is likely sub-optimal though (my thinking is explained in
>> the following paragraph) so this is something I should continue thinking
>> about.
>>
>> Dan: A little bit more detail about the ultimate goal: The challenge is
>> to detect a 1 ppm spectrally pure signal (varying only on 12-hour
>> timescales) at femto-volt levels. Since the frequency is unknown we want to
>> maximize the spectral range but to ensure maximum sensitivity we also want
>> to ensure that we're as efficient as possible scanning over that spectral
>> range (aka do it in real time). That's currently what is setting the FFT
>> size. It also means that the data we're feeding into the ADC is basically
>> thermal noise, which we then average many, many times over to be as
>> sensitive as positive. That was my underlying motivation for doing all this
>> spur testing by terminating the ADC input. I'm absolutely not beholden to
>> this method though, and I think some more reading is in order on my end in
>> light of your suggestions.
>>
>> Matt: Good segue from what Dan was suggesting. Thanks for the reading
>> material. This is all new to me so the more resources the better.
>>
>> Atul: That's very good to know. These spurs are showing up every ~15,500
>> bins. But I'll go through the code and make sure I'm casting the ADC data
>> before sending it to the GPU.
>>
>> Once again, thanks everyone for all the great insight.
>> Looking forward to trying things out,
>> Ben
>>
>>
>>
>>
>> On Thu, Apr 8, 2021 at 4:42 PM Atul Ghalame 
>> wrote:
>>
>>> Hi Ben,
>>>
>>> I had experienced a similar problem once with the 64 channel ADC+ROACH.
>>> F-engine was running on ROACH and all fixed-point data, mismatch of data
>>> type+bits created dips in the broadband noise test at regular intervals.
>>> Casting ADC data into expected format before the FFT resolved it.
>>>
>>> While katADC is sending fixed-point data and GPU running on 

Re: [casper] quantum entanglement sensing using high-speed digital sampling and cross-multiplies

[Francois Kapp]

Hi Neil,
If you want to use the CASPER libraries, you will still need a
Matlab/Simulink and toolbox (DSP system, Signal Processing and Fixed Point
Designer) licenses.  The hardware could be used without it and you will
still be able to gain from the libraries, but it will be much more work.
On the FPGA side, you need Vivado (or Vitis) from Xilinx.

I don't know the commercial pricing for the software licenses and I think
it also varies a little by location. Evaluation licenses may be an option -
often it is very short term, but you should definitely ask about that.

If you are new to CASPER, you will get a good start from the tutorials and
attending the (free, online) workshop in May will also give you plenty to
chew on.
+F

On Fri, 19 Mar 2021 at 22:46, salmon.na via casper@lists.berkeley.edu <
casper@lists.berkeley.edu> wrote:

> Hi Dan,
>
>
>
> Thanks for those great options. Those sampling rates are the sort that I’m
> looking for. I can probably operate with a smaller RF band to start with,
> to make the task a little less difficult.
>
>
>
> Hi Francios,
>
>
>
> Thanks for helping out here. I don’t have academic licences but I could
> buy a commercial Mathworks licence. However, I tend to use Python now in
> place of Matlab, so does the CASPER technology work also with Python? If so
> would I need to buy a licence to use the CASPER hardware with Python, any
> idea of costs? (no way am I anywhere near a product it’s all pretty much a
> research activity, profit is nowhere in sight, stay afloat if lucky)
>
>
>
> Many thanks to you both for help.
>
> Best wishes, Neil
>
>
>
> *From:* Dan Werthimer 
> *Sent:* 19 March 2021 17:41
> *To:* CASPER Mailing List 
> *Subject:* Re: [casper] quantum entanglement sensing using high-speed
> digital sampling and cross-multiplies
>
>
>
>
>
>
>
> hi neil,
>
>
>
> there's a quad 16 Gsps 4 bit ADC FMC board developed by CFA/Smithsonian
> that connects to a VCU128 FPGA board that might be useful for your work.
>
> the analog bandwidth of the ADC doesn't get up to 30 GHz, so you'd have to
> mix down your band before digitizing.
>
> you could break your 20 GHz band up into three pieces of 6.6 GHz each
> (using analog mixers and filters), and use three of the four ADC's on the
> board,
>
> or break it up into four pieces of 5 GHz each and use all four ADC's.
>
>
>
> another, less expensive solution is to break your 20 GHz band up into
> eight pieces of 2.4 GHz each,  (and loosing a bit of the 20 GHz),
>
> then you could use a ZCU208 octal 5 Gsps 14 bit ADC/FPGA board.
>
>
>
> best wishes,
>
>
>
> dan
>
>
>
>
>
>
>
>
>
>
>
> On Fri, Mar 19, 2021 at 3:57 AM Francois Kapp 
> wrote:
>
> Hi Neil,
>
>
>
> Second question first - you can access CASPER technology from anywhere.
> The software licensing may be different if you do not get academic
> discounts from Mathworks, and Xilinx may also charge you something
> depending on your exact situation.  Both companies are generous to academic
> users.
>
>
>
> Regarding CASPER technology that you could use - there is work towards
> sampling those bands, but I don't think it is quite integrated into the
> flow yet.  I know there are people on the list working on high sample rate
> converters that can get to your sample rate with the right number of bits.
> I am less certain of the analog performance out to 30GHz, but hopefully
> others can add to this.
>
>
>
> The processing should be covered by existing library elements.
>
>
>
> Regards,
>
> Francois
>
>
>
> On Fri, 19 Mar 2021 at 12:33, salmon.na via casper@lists.berkeley.edu <
> casper@lists.berkeley.edu> wrote:
>
> Dear All,
>
>
>
> Would it be possible to access Casper technology for research into quantum
> entanglement sensing for the micro/mm-wave band?
>
>
>
> To explore some sensor concepts I’d be looking to make 4-bit sampling of
> radiation in the band 10 GHz to 30 GHz at something like 10 Gsps. I’d need
> to digitise on 4 channels (Hs, Vs, Hi, Vi) where H and V are the horizontal
> and linear polarisations of the radiation. Then I’d need to make four
> non-conjugated cross-multiplies and accumulates to create , ,
>  and .
>
>
>
> Is there Casper (or other) technology that could be used for this? Is it
> possible to access Casper technology for research outside of universities?
>
>
>
> Many thanks, Neil
>
> --
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> email to caspe

Re: [casper] quantum entanglement sensing using high-speed digital sampling and cross-multiplies

[Francois Kapp]

Hi Neil,

Second question first - you can access CASPER technology from anywhere.
The software licensing may be different if you do not get academic
discounts from Mathworks, and Xilinx may also charge you something
depending on your exact situation.  Both companies are generous to academic
users.

Regarding CASPER technology that you could use - there is work towards
sampling those bands, but I don't think it is quite integrated into the
flow yet.  I know there are people on the list working on high sample rate
converters that can get to your sample rate with the right number of bits.
I am less certain of the analog performance out to 30GHz, but hopefully
others can add to this.

The processing should be covered by existing library elements.

Regards,
Francois

On Fri, 19 Mar 2021 at 12:33, salmon.na via casper@lists.berkeley.edu <
casper@lists.berkeley.edu> wrote:

> Dear All,
>
>
>
> Would it be possible to access Casper technology for research into quantum
> entanglement sensing for the micro/mm-wave band?
>
>
>
> To explore some sensor concepts I’d be looking to make 4-bit sampling of
> radiation in the band 10 GHz to 30 GHz at something like 10 Gsps. I’d need
> to digitise on 4 channels (Hs, Vs, Hi, Vi) where H and V are the horizontal
> and linear polarisations of the radiation. Then I’d need to make four
> non-conjugated cross-multiplies and accumulates to create , ,
>  and .
>
>
>
> Is there Casper (or other) technology that could be used for this? Is it
> possible to access Casper technology for research outside of universities?
>
>
>
> Many thanks, Neil
>
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> .
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Re: [casper] low cost academic xilinx RFSOC board - feb 28 tutorial 8am pacific

[Francois Kapp]

Hi Colm,

We discussed this and it appears that only two of the ADC's and DAC's will
be routed to connectors, hence the 2x2.  Dan has already asked Xilinx
whether there is any scope to bring additional channels out to headers or
other low cost connectors.  We await an answer.

Regards,
Francois

On Tue, 16 Feb 2021 at 13:45, Colm Bracken  wrote:

> Hi Dan,
>
> Thanks for the info.
> Do you happen to know what the '2x2' signifies in the name RF SoC 2x2?
> I was thinking 2 DACs and 2 ADCs, but you mentioned that it will have the
> XCZU28DR chip which hosts 8 ADCS and 8 DACs.
> Looking forward to learning more about this board!
>
> Thanks,
> Colm
>
> On Wed, 10 Feb 2021 at 19:01, Dan Werthimer  wrote:
>
>>
>>
>> dear casper community,
>>
>> please see email below from xilinx's patrick lysaght,
>> about their new low cost RFSOC board for academia,
>> and the february 28 tutorial about this board.
>>
>> best wishes,
>>
>> dan
>>
>> -- Forwarded message -
>> Date: Wed, Feb 10, 2021 at 10:00 AM
>> Subject: Emailing: isfpga_rfsoc_2x2_tutorial.jpg
>>
>>
>>  Dear Friends
>>
>> I hope you are all doing well in 2021.  I have some good news that I
>> would like to share with you.  At the end of Feb, we will launch a new
>> RFSoC platform for academia.  It features a new board, the RFSoC 2x2,
>> supported with open source designs and teaching material.  We will be
>> hosting a tutorial on Sunday 28th Feb from 8 - 10 AM PST as part of the
>> ISFPGA 2021 conference (https://isfpga.org/) to announce and introduce
>> the new RFSoC 2x2 platform.  Everyone is welcome to attend the tutorial and
>> registration is free for students.
>>
>> Would you kindly share this invitation with the CASPER community?  For
>> those who would like to attend, links to the tutorial site and the
>> registration pages are provided below.  I have also attached a graphic
>> summarizing the tutorial.
>>
>> Best .. Patrick
>>
>> More details ...
>> A Low-Cost Teaching and Research Platform Based on Xilinx RFSoC
>> Technology and the PYNQ Framework
>> Time: February 28, 8:00 AM - 10:00 AM PST
>> Organizer: Patrick Lysaght (Xilinx), Robert W. Stewart (Strathclyde)
>>
>> The Xilinx Zynq(r) UltraScale+(tm) RFSoC architecture integrates ZU+
>> MPSoCs with state-of-the-art, analog-to-digital (ADC) and digital-to-analog
>> (DAC) data converters. The combination of banks of high-precision data
>> converters, capable of processing multi giga samples of data per second,
>> along with FPGA fabric and ARM processors creates a uniquely powerful
>> family architecture.  RFSoC technology re-defines what is possible in
>> applications such as software defined radio (SDR) and advanced
>> instrumentation.
>> This tutorial introduces a new low-cost teaching and research platform
>> for RFSoC, designed especially for academia. The platform exploits the PYNQ
>> open-source framework to provide a highly intuitive user system interface
>> incorporating Linux, Python and Jupyter notebooks. It also comes with a
>> suite of open-source teaching resources including videos, notebooks and
>> design examples.
>> We will demonstrate the benefits of integrating direct RF sampling data
>> converters by introducing  a novel, open-source spectrum analyzer built
>> using the new board. This RFSoC design exploits advanced signal processing
>> techniques, including higher-order Nyquist zones, to demonstrate
>> performance that has only previously been achieved on very high-end
>> instrumentation. Using the spectrum analyzer example, we will also
>> demonstrate new approaches to the rapid prototyping of graphical user
>> interfaces for research demonstrators.
>>
>> Links ...
>> ISFPGA tutorial page: http://bit.ly/ISFPGA_rfsoc2x2
>> Register for ISFPGA & tutorial here: http://bit.ly/ISFPGA_rfsoc2x2
>> #Xilinx #RFSoC
>>
>>
>>
>>
>> This email and any attachments are intended for the sole use of the named
>> recipient(s) and contain(s) confidential information that may be
>> proprietary, privileged or copyrighted under applicable law. If you are not
>> the intended recipient, do not read, copy, or forward this email message or
>> any attachments. Delete this email message and any attachments immediately.
>>
>> --
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>> email to casper+unsubscr...@lists.berkeley.edu.
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>> https://groups.google.com/a/lists.berkeley.edu/d/msgid/casper/CAGHS_vHaL9wJFZjVWYoXPTZfwm%2BE%2BNJPd8QVifZ6-MqhgNX6BQ%40mail.gmail.com
>> 
>> .
>>
>
>
> --
>
> *Dr Colm Bracken*
> Lecturer
> Maynooth University Experimental Physics
>
>
> Maynooth University, Maynooth, Co. Kildare, Ireland.
>
> T: +353 1 708 3641
> E: 

Re: [casper] Quick prototype platform

[Francois Kapp]

The timing and availability might be a factor, but it would be great if
"someone" had the energy to "CASPER-ise" a Xilinx RFSoC development board.
They have up to 16 ADC's that may be overkill in the sample rate
department, but it is an interesting platform.  Maybe development boards
are available?

On 16 Mar 2018 07:05, "Jack Hickish"  wrote:

> Hi Karl,
>
> On Thu, 15 Mar 2018 at 21:59 Karl Warnick  wrote:
>
>> Hi all,
>>
>> I have a non-astronomical comms antenna array project that does not have
>> detailed specs for bandwidth and number of antenna elements. I need to
>> build a programmable platform that I can use for multichannel sampling
>> and real time DSP.
>>
>> Our group has considerable experience with ROACH based systems over the
>> years and hybrid FPGA - GPU architectures, but the students with much of
>> the expertise have graduated and moved on, as students tend to do. We
>> have an x64 board and ROACH that on paper could do the job, but the
>> hardware seems old enough now that I wonder if it might be wise to move
>> to a new platform for my new project. We also like the easier
>> programmability of GPUs for matrix based array signal processing
>> algorithms. We also have a system with digitizers, polyphase filterbanks
>> running on ROACH boards, ethernet switch, and HPCs with GPUs, but that
>> system is in operation at GBO and is probably overkill for the current
>> project.
>>
>> This leads to my question. To realize a system with 16 analog channels
>> and analog bandwidth ranging between a few MHz up to 100 MHz (I realize
>> that this is a rather ill defined range, but I feel fortunate to have
>> the flexibility), that can do digitization, filterbank to separate into
>> frequency channels, and enough processor power for real time XB
>> (correlator/beamformer) type signal processing, with current CASPER
>> hardware, what would be the ideal, recommended hardware setup?
>>
>
> I think your options here are either a/some SNAP board(s) -- 12 ADC
> channels at up to 250 MSample/s sampling rate, or a ROACH2 + adc16 card --
> 16 channels at up to 250MSample/s. Either would give you Ethernet output on
> SFP+ connectors. SNAP can do up to 20Gb/s output, ROACH2 up to 80Gb/s.
> In either case, there should be some simulink designs you could use as a
> starting point, from PAPER/HERA or other projects.
>
> Cheers
> Jack
>
>
>>
>> The relatively modest bandwidth requirement may also point to a
>> commercial FPGA/ARM core board with an ADC expansion board, and I'm
>> pursuing that path as well. From another project, I have an expansion
>> board of our own design with eight ADC channels that plugs into a
>> microZED board, which actually comes somewhat close to meeting the
>> current requirements. Expanding the ADC board and moving to a bigger
>> commercial digital board is an option.
>>
>> Thanks to all for any feedback!
>>
>> Best,
>> Karl
>>
>> --
>> Karl F. Warnick
>> Department of Electrical and Computer Engineering
>> Brigham Young University
>> 459 Clyde Building
>> Provo, UT 84602
>> (801) 422-1732
>>
>>
>>
>>
>>
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Re: [casper] Hardware/Yellow Block Porting Workshop - 30 July - 3 August, SAAO, Cape Town

[Francois Kapp]

Do you want to add the Protea/Marriot hotel as a suggestion? It's very
close to SAAO for those who can foot the bill...
http://www.marriott.com/hotels/travel/cptmw-protea-hotel-cape-town-mowbray/

On 27 February 2018 at 13:23, Adam Isaacson  wrote:

> Hi Casperites,
>
> Thanks to those of you that filled in the Doodle poll. We have a venue and
> a date! Please see details below and diarise:
>
> *Workshop:* Hardware/Yellow Block Porting Workshop
>
> *Workshop Leadership Team: *Jack Hickish (University of Berkeley),
> Jonathon Kocz (Caltech) (TBC), Wesley New (SARAO), Adam Isaacson (SARAO)
> and Amish Patel (SARAO)
>
> *Workshop Description: *
> 1) You bring your completed firmware with hardware and we will help you
> integrate it into the new CASPER toolflow, so that you can target your
> hardware with the new CASPER toolflow
> 2) We will show you how take existing firmware and create a yellow block.
> 3) Workshop will be run informally and will be hands on
>
> *Workshop Prerequisites: *
>
> I would suggest, at least, having run through tutorial 1 and tutorial 2 to
> familiarise yourself with Ubuntu, Matlab and Vivado- see tutorial section
> under http://casper-dsp.org (new unofficially released CASPER site)
>
> *Venue:* South African Astronomical Observatory (SAAO), Cape Town,
> Auditorium
> *Date: *30 July - 3rd August 2018
> *Time:* 9am - 5pm
> *Workshop Cost:* Free :)
>
> *Accommodation:* I suggest City Lodge Pinelands (
> https://clhg.com/hotels/155/City-Lodge-Hotel-Pinelands-Cape-Town
> )
>
> *Directions:* https://www.saao.ac.za/contact-2/ (Cape Town) - just
> between the River Club and Valkenburg hospital here in the suburb of
> Observatory. Security will direct you to the auditorium after you have
> signed in.
>
> *What to Bring:* Your lap top/desktop, target hardware, ethernet
> switches, cables and firmware. We will cater for the food and venue hire.
> There is internet availability (WiFi) at the venue.
>
> *RSVP:* Please respond to my email (aisaac...@ska.ac.za) and not the
> whole CASPER emailing group, if you will be attending by no later than the *31
> March 2018*, thanks.
>
> If you reply, it would also be great if you could give some background as
> to what software tools you are currently using and what you want to achieve
> through this workshop. I would like to know whether you are a beginner or
> advanced.
>
> All further communication will be sent out to participants. I hope to see
> you there!
>
> Kind regards,
>
> Adam Isaacson
> SARAO
> DBE Hardware Manager
> Cell: (+27) 825639602 <082%20563%209602>
> Tel:  (+27) 215067300 <021%20506%207300>
> email: aisaac...@ska.ac.za
>
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Re: [casper] Pulsar backends

[Francois Kapp]

Spot on Justin.  Documentation is still a little scarce and what we have
(requirements specifications, etc.) may be hard to interpret.  What exists
to date is a boresight single beam system, soon to be upgraded to the four
beam system Justin mentioned.  We are open to setting up calls to discuss
though - maybe after our big end of March milestone...

+F

On 26 January 2018 at 08:24, phjj  wrote:

> At the risk of speaking on behalf of my far more knowledgeable colleagues:
>
> The entry-level “MeerKAT beamformer” is embedded in the
> correlator/beamformer and will provide a maximum of 4, currently 1, tied
> array beams using CASPER SKARAB hardware and firmware.  Currently provides
> a tied array voltage beam to the Swinburne pulsar timing back end.
>
> The MeerKAT “transient search beamformer” is being provided by Manchester
> (Ben Stappers) and MPIfR (Michael Kramer), 100s of beams and search
> engines, GPU based.  Ben also has a prototype SKA non-imaging processor
> (protoNIP) installed in our Cape Town office.  The GPUs subscribe to
> channelized antenna voltage SPEAD data streams emanating from the MeerKAT
> correlator/beamformer core switch.
>
> J
>
>
> > On 25 Jan 2018, at 9:45 PM, Scott Ransom  wrote:
> >
> > Hi All,
> >
> > I had a discussion with Rich and Omar yesterday.  I think they are
> interested in slightly more than what is being called a "pulsar backend",
> but more like the whole system to allow fast sampled observations in
> general:  i.e. beam formers or fast-dump correlators and how they are
> interfacing with back-end processing, like the VLAs CBE or more traditional
> pulsar backends like CASPER-based GUPPI and their ilk.
> >
> > I personally don't know much about what is happening with beamformers,
> for example, with MeerKAT.  Is there any documentation on that?
> >
> > Scott
> >
> > On 01/25/2018 02:19 PM, Mark Halpern wrote:
> >> ..or (along with Scott Ransom) contact Emmanual Fonseca or Ingrid
> Stairs to ask about the pulsar timing back end for CHIME.
> >> Mark
> >> On 2018-01-25 10:10 AM, Dan Werthimer wrote:
> >>>
> >>> hi rich,
> >>>
> >>> i know a bit about the meerkat pulsar search.
> >>> (i'm not on the team, but we've been working with those guys...).
> >>> i don't know much about meerkat pulsar timing (the timing and search
> are different groups).
> >>>
> >>> scott ransom knows a bit about SKA pulsar search design team at oxford.
> >>> i know a small bit, but not as much as scott.
> >>> i can introduce you to some of the oxford ska pulsar team if you want.
> >>>
> >>> dan
> >>>
> >>>
> >>>
> >>>
> >>>
> >>> On Thu, Jan 25, 2018 at 7:38 AM, Rich Lacasse  > wrote:
> >>>
> >>> Hi All,
> >>>
> >>> A few of us are starting to think about the pulsar backend for the
> >>> ngVLA.  We were wondering if someone on this list might be able to
> >>> point us to publicly available documentation on what is being done
> >>> and being planned for MeerKat and SKA.  This would give us an
> >>> excellent starting point.  Thanks in advance for any help you can
> offer!
> >>>
> >>> Rich Lacasse, Omar Ojeda, Rob Selina
> >>>
> >>> -- You received this message because you are subscribed to the
> Google
> >>> Groups "casper@lists.berkeley.edu
> >>> " group.
> >>> To unsubscribe from this group and stop receiving emails from it,
> >>> send an email to casper+unsubscr...@lists.berkeley.edu
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> >>> .
> >>>
> >>>
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> .
> >
> > --
> > Scott M. RansomAddress:  NRAO
> > Phone:  (434) 296-0320   520 Edgemont Rd.
> > email:  sran...@nrao.edu Charlottesville, VA 22903 USA
> > GPG Fingerprint: A40A 94F2 3F48 4136 3AC4  9598 92D5 25CB 22A6 7B65
> >
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[casper] Registration now open for CASPER 2016

[Francois Kapp]

Invitation to CASPER2016 - Collaboration for Astronomy Signal Processing
and Electronics Research

The 2016 Collaboration for Astronomy Signal Processing and Electronics
Research (CASPER) workshop will be held in Cape Town from 25 - 29 January
2016. The details for the workshop are available on
https://casper.berkeley.edu/wiki/Workshop_2016. The workshop follows
largely the same structure as in the past: keynote presentations, tool
presentations, working group meetings, tutorials and poster presentations.

If you would like to give a short 15 minute oral presentation (e.g. about
your research) or facilitate a round table discussion (e.g. discussion
concerning specific technology needs or problems) please provide a proposed
title and short abstract so that we can add that to the programme..

While astronomy processing is the main emphases, an added theme for this
year is the use of radio astronomy installations for applications other
than astronomy; such as uses for atmospheric analysis and tracking objects
in orbit. The CASPER workshop is colocated with the High Performance Signal
Processing South Africa (HPSPSA) workshop that has some additional
presentations and tutorial opportunities relevant to digital back-end
development, many of these topics will have some relevance and problems in
common to those related to astronomy data processing.

Details about the programme, including the keynote speakers, registration
and the selection of tutorials available are on the web at
http://www.hpspsa.com/.

Hope to see you in Cape Town next year.

Sincerely,

CASPER2016 workshop organizing team

--

[casper] Research Position in Cape Town

[Francois Kapp]

Research Officer in Digital Signal Processing wanted:
http://www.uct.ac.za/usr/about/intro/vacancies/researchpass/2015/EBE_15124_RO_DSP_Elec.pdf

[casper] CASPER workshop 2016

[Francois Kapp]

Dear all,

Another reminder of the CASPER 2016 workshop, which will be held in Cape
Town at the University of Cape Town from 25 to 29 January 2016.  We are
also planning a bus trip to the MeerKAT site from 29 to 31 January.

There is some more information on the wiki:
https://casper.berkeley.edu/wiki/Workshop_2016

Regards,
François

[casper] First Announcement: CASPER Workshop 2016 in Cape Town

[Francois Kapp]

Dear Casperites,

We are delighted to announce that the 2016 CASPER workshop will be held in
Cape Town from 25 - 29 January 2016.  We are planning a visit to the
MeerKAT telescope site for the weekend of 29-31 January, so keep that in
the diary if you are interested to join us.

The details for the workshop will be published on the wiki here:
https://casper.berkeley.edu/wiki/Workshop_2016 in due course.

Hope to see many of you in Cape Town next year.

-- 
François Kapp

[casper] Fwd: [nrfannounce:354] Recruitment@NRF

[Francois Kapp]

Position for a Pulsar Astronomer at our sister organisation HartRAO in
South Africa.


 [image: Description:
http://www.nrfcoms.info/NRFrecuitment/images/recuitmentLogo.jpg]

The following post is advertised:



Position: Astronomer - Pulsars



To apply: Click here http://nfrintra.careerjunction.co.za







  Meiring Naude Road
Brummeria
PO Box 2600
Pretoria, 0001
South Africa
http://www.nrf.ac.za

   *Patrick Saunders*
Copy Writer and Editor
Corporate Communications
Tel: +27 12 481 4271
Email: patrick.saund...@nrf.ac.za

http://www.nrf.ac.za/email-legal-notice.php
inline: imageb0201e.jpg@778b73bd.0e0b49abinline: image001.jpg

[casper] Vacancies at SKA South Africa

[Francois Kapp]

Apologies for the (once only, I promise) spam, but we are hiring at SKA
South Africa.  The vacancies are listed on our parent organisation's web
site (the National Research Foundation), here:
http://nrfinter.careerjunction.co.za/

Positions are for participation both in MeerKAT and our work towards SKA.
 Because we have many positions, the job descriptions are flexible - if you
think you can contribute, apply - we'll figure out the details along the
way.

Also, please let me know directly if you do apply, so I can make sure all
applications are confirmed.  It goes without saying that CASPER-ites are
highly desirable :-)

And finally - even if you were irritated by this message, please spread the
word!

Regards,
François

[casper] Position at Rhodes University

[Francois Kapp]

Anyone interested in a research/teaching position in Physics/Electronics at
Rhodes University in South Africa, please follow this link:
http://www.ru.ac.za/jobs/currentvacancies/academic/name,96161,en.html

+Francois

Re: [casper] PPC life time buy: please respond if you anticipate needing ROACH1 or ROACH2 boards

[Francois Kapp]

Dear Casperites,

Just a reminder to indicate your interest in ROACH/ROACH2 in the future on
this survey:

http://www.surveymonkey.com/s/ZG7T98F

We are going to close the survey soon.

Regards,
Francois


On Mon, Sep 23, 2013 at 7:43 PM, Alec Rust alec.r...@ska.ac.za wrote:

 Dear Casper Collaborator,

 If you are planning to procure ROACH1 or ROACH2 boards in the next 5
 years, please read this email and please respond to this survey (see the
 link to the survey below).

 Thank you.

 The PowerPC (PPC) embedded processor chip, used on both the ROACH1 and
 ROACH2 boards, is being discontinued.

 We need  to do a lifetime purchase soon. Digicom has generously offered
 to purchase a batch of these chips in anticipation of future orders of
 ROACH1 and ROACH2 boards.

 The safest thing to do to ensure you'll have PPC chips available for the
 roach boards you might need, is to purchase these chips yourself and keep
 them in your stock or at Digicom (with your name on them) for potential
 future builds. The PPC chips cost about $50 each. If you are planning
 large projects we would recommend you buy the chips yourself as Digicom can
 not be expected to take the risk on large orders. Recommended part numbers
 will be sent in a separate email.

 Or you can hope that Digicom will have them in stock or that you and
 Digicom will be able to purchase them when you need the chips.

 So that digicom can estimate the number of PPC chips needed, can you
 please fill out the survey at:

 http://www.surveymonkey.com/s/ZG7T98F


 Please fill out a survey form for each of your potential upcoming
 projects.
 (you can click on the link above multiple times).

 This survey requests name of your project(s), the probability that the
 project will happen, and the years you might  need the boards, and
 whether you plan to the purchase PPC chips yourself and set them aside
 for your projects.

 Please respond within the next week.

 Thanks for responding to this survey.

[casper] Fwd: [saastronomers]

[Francois Kapp]

Position at the CHPC in Cape Town.  Please distribute and contact
Catherine  catherine.cr...@gmail.com directly if anyone is interested.

-Francois


-- Forwarded message --
From: Catherine Cress catherine.cr...@gmail.com
Date: Tue, Aug 20, 2013 at 8:49 AM

Dear All

The Centre for High Performance Computing has a vacancy for a research
scientist who can provide support to the Astronomy user community and
participate in Astronomy research. Closing date for applications is 30
August.

Please contact me for further information.
Thanks
Catherine Cress


-- 
Principal Research Scientist, Centre for High Performance Computing, Cape
Town
Extraordinary Associate Professor, Physics, University of the Western Cape
 !DSPAM:52131191306031067515614!

Re: [casper] Roach Conduction Cooling

[Francois Kapp]

Hi Brad,

Given it's a balloon payload, what are your mass constraints?  Conductive
cooling is going to involve throwing metal at the problem, possibly a lot
of metal...

-Francois


On Tue, Apr 16, 2013 at 12:57 PM, Steve Maher stephen.f.ma...@nasa.govwrote:

 Heatpipes and dunking http://www.pugetsystems.com/submerged.phpin
 liquid (e.g. mineral oil) are options we've explored (with PCs), although
 we seem to be favoring pressure vessels at this point.

 Steve


 On Tue, Apr 16, 2013 at 2:34 AM, Jason Manley jman...@ska.ac.za wrote:

 I don't know of anyone who's actually done this, but we do also have a
 passive-cooled concept for our new digitiser board (loosely based on
 ROACH2). We've been thinking about a prototype that'd essentially be
 turning a ROACH2 board upside-down and bolting it onto a giant metal plate
 that's been appropriately milled out of a solid chunk of alu. The FPGA,
 PPC, QDR and other hot bits would make contact with the plate and use it as
 heatsink. The other high-profile parts (RAM DIMM, for example) needs holes
 or cavities milled out the alu.

 I think Vaughan (cc'd here) might have some mechanical drawings of ROACH2
 with the holes and things in the appropriate place. It might help you get
 started. He could also provide some CFD models and heat load measurements
 of the various components.

 Jason Manley
 DSP Specialist
 SKA-SA

 Cell: +27 82 662 7726
 Work: +27 21 506 7300

 On 15 Apr 2013, at 20:29, Brad Dober wrote:

  Dear Casper Collaboration Members,
 
  My name is Brad Dober, and I'm a grad student at UPenn working on a
 ROACH-based MKID readout for a balloon payload. At our float altitude,
 air-cooling the ROACH and ADC/DACs isn't feasible Has any other group
 looked into or even designed a conduction-cooled system for .either the
 ROACH1 or ROACH2?
 
  Any leads would be extremely helpful.
 
  Sincerely,
 
  Brad Dober
  Ph.D. Candidate
  Department of Physics and Astronomy
  University of Pennsylvania
  Cell: 262-949-4668






-- 
Francois Kapp

Sub-system Manager
Digital Back End
meerKAT

SKA South Africa
Third Floor
The Park
Park Road (off Alexandra Road)
Pinelands
7405
Western Cape
South Africa

Latitude: -33.94329 (South); Longitude: 18.48945 (East).

(p) +27 (0)21 506 7300
(p) +27 (0)21 506 7360 (direct)
(f) +27 (0)21 506 7375
(m) +27 (0)82 787 8407

[casper] Altera + Intel

[Francois Kapp]

http://www.engadget.com/2013/02/26/intel-lands-altera-as-its-biggest-chip-manufacturing-customer-yet/

As predicted - FPGA's are ideal test beds for new process geometries.  This
will keep FPGA's on Moore's law curve for another node.

I do wonder about costs, but that's a wait and see.

Also interesting to see Xilinx's response.

-F

-- 
Francois Kapp

Sub-system Manager
Digital Back End
meerKAT

SKA South Africa
Third Floor
The Park
Park Road (off Alexandra Road)
Pinelands
7405
Western Cape
South Africa

Latitude: -33.94329 (South); Longitude: 18.48945 (East).

(p) +27 (0)21 506 7300
(p) +27 (0)21 506 7360 (direct)
(f) +27 (0)21 506 7375
(m) +27 (0)82 787 8407

Re: [casper] Vitesse data sheets and NDAs

[Francois Kapp]

Afraid David M is right - the last PHY we used that did not require an NDA
for access to the datasheet was the 1Gb National part on ROACH.  It is
unfortunate, but unavoidable at the moment.  Hopefully the PHY will not
need much discussion in terms of applications, so only people who need to
get involved with the actual hardware design will need to sign NDA's.

-Francois


On Tue, Jan 29, 2013 at 11:41 PM, David MacMahon
dav...@astro.berkeley.eduwrote:

 Hi, David,

 I think this is becoming more and more common in the industry, at least
 for networking chips.  I think Marvell also requires an NDA to get the
 datasheet for the 1 GbE PHYs on the ROACH2 itself.  Are you aware of any
 similar SFP+ PHYs that do NOT require an NDA for the datasheet?

 Dave

 On Jan 29, 2013, at 12:34 PM, David Forbes wrote:

  Hi all,
 
  I'm looking at the SFP+ card for the ROACH 2 board. It appears to use a
 Vitesse 8488 PHY chip. The Vitesse folks say I need to sign a
 non-disclosure agreement (NDA) to read the data sheet.
 
  It seems like a big problem to use a chip with secrets in its data sheet
 in a board for an open hardware platform. Which is to say, I will have a
 hard discussing the merits of using this part with my coworkers (or anyone
 else on the CASPER list) unless they sign the NDA as well.
 
  Thoughts?
  --
  David Forbes Steward Observatory / ARO
  University of Arizonadfor...@email.arizona.edu
  933 N Cherry Room 172   phone 520-626-1361
  Tucson AZ 85721   fax 520-621-5554
 
 





-- 
Francois Kapp

Sub-system Manager
Digital Back End
meerKAT

Team founder: Team SKA Africa
http://www.facebook.com/Team.SKA.Africa
http://teamskaafrica.wordpress.com/
http://www.givengain.com/activist/87536/projects/3987/

SKA South Africa
Third Floor
The Park
Park Road (off Alexandra Road)
Pinelands
7405
Western Cape
South Africa

Latitude: -33.94329 (South); Longitude: 18.48945 (East).

(p) +27 (0)21 506 7300
(p) +27 (0)21 506 7360 (direct)
(f) +27 (0)21 506 7375
(m) +27 (0)82 787 8407

Re: [casper] KATADC attenuators

[Francois Kapp]

Hi Tom,

Not sure if you have resolved this, but there is no jumper setting to
override the attenuation on the KatADC.  There are jumpers (J2, 3) that
force the input switches (U30, 31) on for test purposes.

-F


On Thu, Dec 20, 2012 at 10:57 PM, Tom Kuiper kui...@jpl.nasa.gov wrote:

 I have two KATADCs, one each in ZDOC0 of two ROACH-1 boards (named roach1
 and roach2).  It appears that the attenuator for input 0 of the KATADC in
 roach2 is at 0 dB for whatever attenuation setting command is sent to it.
  The other three inputs respond as I expect.  I assume that this is some
 kind of hardware failure but I thought I'd better check if there was some
 jumper setting or control bit that I don't know about.

 With thanks and best regards,

 Tom




-- 
Francois Kapp

Sub-system Manager
Digital Back End
meerKAT

Team founder: Team SKA Africa
http://www.facebook.com/Team.SKA.Africa
http://teamskaafrica.wordpress.com/
http://www.givengain.com/activist/87536/projects/3987/

SKA South Africa
Third Floor
The Park
Park Road (off Alexandra Road)
Pinelands
7405
Western Cape
South Africa

Latitude: -33.94329 (South); Longitude: 18.48945 (East).

(p) +27 (0)21 506 7300
(p) +27 (0)21 506 7360 (direct)
(f) +27 (0)21 506 7375
(m) +27 (0)82 787 8407

Re: [casper] ROACH hardware failures

[Francois Kapp]

Jason M has that right - the device that failed is on the incoming 5V line
from the ATX supply.  It shows up on 1V, because that is the only lower
voltage that is regulated from the 5V input.  Maximum (worst case) current
that should be drawn from this is less than 7A.  I wondered briefly if it
could be an issue with inrush current - as it is immediately followed by
two very low ESR caps of 330uF each, but that is rated at 55A, so the
inductors should slow things down beyond that.

If anyone else has seen this failure, please report it here so we can try
to find the root cause.

-Francois

On Tue, Jun 19, 2012 at 7:39 PM, Jason Ray j...@nrao.edu wrote:

 Jason,

 The parts both looked fine, they just didn't turn on.  No indication of
 heat damage on the part, board, or traces.

 The first roach we found this on is SN 020145 and the second one is SN
 030191.

 Thanks,
 Jason



 At 01:16 PM 6/19/2012, Jason Manley wrote:

 Thanks for the feedback!

 I'd also like to understand this problem a little better.

 Q13 sits on the 5V rail and the P-channel MOSFET is rated at -11A with a
 13mohm on resistance. That's good for over 50W. Was there any indication of
 heat damage on the failed parts (due to overloading or maybe the heat
 sinking was bad)?

 Or did the part look fine, it just didn't turn on anymore? There is a
 resistor between the gate and source, so the gate doesn't float even when
 not in use. It really shouldn't have broken due to ESD after it was
 installed.

 We have had batches of boards with bad components before... once even due
 to passives (termination resistors that didn't all have the right
 resistance) which is the last thing we expect to fail. These are usually
 all caught in the factory during the standard off-the-line tests.

 Can you supply the serial numbers of these boards so we can add this
 issue to our database? We'll then monitor to see if it re-occurs on any
 other boards.

 Jason

 On 19 Jun 2012, at 19:05, John Ford wrote:

  Jason R. and John,
  Was the roach running a particularly intensive design at the time
  around the failure? Just wondering why this part would be failing. Is
  the current limit somehow being exceeded?
 
  We don't know about the first one, because it came to us from Socorro,
 but
  the second roach was being used to test the tutorials, so I don't think
 it
  was particularly heavily loaded.
 
  I had a thought that we should check the serial numbers and see if they
  are from the same batch.  Maybe some bad parts or ESD damage?
 
  John
 
  Thanks,
  Glenn
 
  On Tue, Jun 19, 2012 at 9:52 AM, Jason Ray j...@nrao.edu wrote:
  The first time I was troubleshooting this problem, I did see a fault
 on
  the
  1V supply with roach_monitor.py.  I didn't check roach_monitor.py on
 the
  second roach because the problem was so fresh in our mind we just
 jumped
  to
  the finish line and checked the mosfet with a meter, then replaced it.
 
  For reference, the part in question is Q13 (FD6675BZ).
 
  Thanks,
  Jason
 
 
 
  At 09:33 AM 6/19/2012, Jason Manley wrote:
 
  Good sleuthing!
 
  FWIW, roach_monitor.py is supposed to be able to pull the log out of
  the
  Actel Fusion, which should have logged a fault on the 1V rail before
  shutting-down the board. This should work independent of PPC or dmesg
  states. I'm afraid I have little faith in the Fusion/Xport combo to
  reliably
  catch these issues, but it has helped me a few times.
 
  If it works, it only retrieves the reason for the last shutdown, so
  you'll
  have to plug a laptop into the Xport to query it directly after it
  self-shutdown.
 
  Jason
 
  On 19 Jun 2012, at 15:23, John Ford wrote:
 
  Hi all.  We've had a couple of ROACH failures with identical causes.
  Maybe some of you have seen this, but it's worth keeping in mind in
  case
  you have a problem.
 
  The symptom is that the ROACH would sort of power on, but then turn
  off
  spontaneously.  On one, as soon as the bof was loaded the roach
 would
  turn
  off.  The other one would come on for a brief few seconds and then
  turn
  or, or it would cycle on and off.  The monitor readout in dmesg gave
  non-sense readings.
 
  In any event, the cause was traced to the +1 volt supply MOSFET
  switch.
  Replacing that mosfet fixed both roaches.  Kudos to Jason Ray for
  finding
  the problem originally.
 
  John
 
 
 
 
 
 
 
 
 






-- 
Francois Kapp

Sub-system Manager
Digital Back End
meerKAT

SKA South Africa
Third Floor
The Park
Park Road (off Alexandra Road)
Pinelands
7405
Western Cape
South Africa

Latitude: -33.94329 (South); Longitude: 18.48945 (East).

(p) +27 (0)21 506 7300
(p) +27 (0)21 506 7360 (direct)
(f) +27 (0)21 506 7375
(m) +27 (0)82 787 8407

Re: [casper] 1-2 GHz sampler

[Francois Kapp]

Hi Bill,

Not quite yet, but we are working on a board that could do 2.2 GSPS
non-interleaved.  It is called the adc1x2200-10 which indicates 1 channel,
10 bits, 2200 MSPS.  It is based on the e2v AT84AS008 part with associated
DMUX and the status is that we have a PCB design, PCB's and components
ordered and assembly booked.  If all goes well we should be able to get
some measurement results out within the next two months.

This may be an option depending on your schedule?

Regards,
Francois

On Wed, May 30, 2012 at 2:57 PM, Bill Petrachenko wtpe...@yahoo.ca wrote:

 OK, so it looks like I'll need to pay more attention to interleaving than
 I had hoped. I assume there are no ROACH-compatible boards that use chips
 that clock at 2048-MHz but without interleaving.

 Also, we're using a flexible down-converter to select 1-GHz bands anywhere
 in the 2-14-GHz range. At many sites RFI at S-band will be a problem so
 dynamic range is an issue. The chips on the ASIAA, ADC1x3000, and Kat-ADC
 all seem to drop to about ENOB = 6-bits at 2-GHz which is less than ideal.
 Using a 10- or 12-bit sampler would be preferred but it seems no
 ROACH-compatible sampler boards have been designed with 10- or 12-bit
 capability and the interface won't handle the extra bits anyway. Having
 said that though I seem to recall that you implied in your initial email
 that the ASIAA card could be used in the dual sampler mode (assuming a
 1-GHz bandwidth) if interaced to the ROACH2 and yet the ZDOK connection for
 both ROACH1 and ROACH2 both use a 40 differential pair interface. How do
 you get the extra bandwith with the ROACH2?

 Yes, I did pick up that we would need the higher bandwidth filter.
 However, I also noticed that there were some plans to implement shields and
 heat sinks for the Kat-ADC. Has this come to pass or has it become apparent
 that neither are required?

 Many thanks,
 -Bill.

   *From:* Dan Werthimer d...@ssl.berkeley.edu
 *To:* Bill Petrachenko wtpe...@yahoo.ca
 *Sent:* Monday, May 28, 2012 11:21:40 PM
 *Subject:* Re: [casper] 1-2 GHz sampler

 the kat-adc has two different front end fiilter options.
 make sure to order the filter option for high frequency.

 dan

 On Mon, May 28, 2012 at 7:19 PM, Bill Petrachenko wtpe...@yahoo.ca
 wrote:
  Thanks Dan. It sounds like the Kat-ADC is probably best for us.
 
  -Bill.
 
  
  From: Dan Werthimer d...@ssl.berkeley.edu
  To: Bill Petrachenko wtpe...@yahoo.ca
  Cc: Casper Casper@lists.berkeley.edu
  Sent: Monday, May 28, 2012 8:47:45 PM
  Subject: Re: [casper] 1-2 GHz sampler

 
  hi bill,
 
  i think all the boards you mention have analog bandwidth out to 2 GHz,
  so they should work well for your 1-2 GHz band.
 
  the asiaa board is the least expensive, but this board does not have
  programmable
  attenuators like the Kat-ADC.  the asiaa board can be used as a single
  5 Gsps ADC, or as a dual 2.5 GHz ADC.
  we have used the asiaa board as a single 5 gsps adc, and it works quite
  well.
  but we have never tested it as a dual adc - perhaps others reading
  this email can
  give you advice about using it in dual mode.if you are using roach
  I, you can't
  get the 8 bit version of the asiaa board working at the full 5 gsps.
  if you are using
  roach II, you can use it at 5 Gsps.
 
  best wishes,
 
  dan
 
 
 
 
  On Thu, May 24, 2012 at 11:30 AM, Bill Petrachenko wtpe...@yahoo.ca
 wrote:
  I'm designing a digital data acquisition system using a ROACH1 board. I
  need
  to sample two Nyquist zones at 1024-2048 MHz. It appears that in the
  Casper
  group of products, a pair of ASIAA, ADC1x3000-8, or KatADC boards would
  work
  well and nicely interfaced to a single ROACH1 board (although the ASIAA
  board is not mention explicitly on the web-site). Is there any reason to
  choose one board over another? The gain adjustment stage is attractive
 on
  the KatADC but the performance of the ADC1x3000-8 chip seems marginally
  better at 2-GHz input frequency. The e2v chip seems less established
 than
  the National chips. Is interleaving or calibration an issue for any of
 the
  chips?
 
  I'd be grateful for any opinions on this.
  Thanks, -Bill.
 
 





-- 
Francois Kapp

Sub-system Manager
Digital Back End
meerKAT

SKA South Africa
Third Floor
The Park
Park Road (off Alexandra Road)
Pinelands
7405
Western Cape
South Africa

Latitude: -33.94329 (South); Longitude: 18.48945 (East).

(p) +27 (0)21 506 7300
(p) +27 (0)21 506 7360 (direct)
(f) +27 (0)21 506 7375
(m) +27 (0)82 787 8407

Re: [casper] Gerbers for ROACH

[Francois Kapp]

Hi all,

Thanks Wesley.

Here it is:
https://github.com/ska-sa/roach1_hardware/tree/master/roach/layout/CAM

These files imported easily into GVPrevue when I last needed a free viewer.

Regards,
Francois

On Sat, Feb 11, 2012 at 5:16 PM, Wesley New wes...@ska.ac.za wrote:
 Hi Rich,

 As an aside, we have recently put the repository with all the roach 1
 and 2 hardware files onto github, search for ska-sa and and feel free
 to browse through the repos. I will send you a link as soon as I get
 to a computer.

 Regards

 Wes

 On 2/10/12, Rich Lacasse rlaca...@nrao.edu wrote:
 I received the following from Jason Ray and it worked fine...  Rich

 I too had trouble using the PADS viewer, but was able to open the .PHO files
 in the viewer I normally use --- Pentalogix Viewmate 10.6.
 http://www.pentalogix.com/viewmate.php

 We use the free version of Viewmate.

 casper-requ...@lists.berkeley.edu wrote:

 Send casper mailing list submissions to
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 than Re: Contents of casper digest...


 Today's Topics:

    1. Gerbers for ROACH (Rich Lacasse)


 --

 Message: 1
 Date: Fri, 10 Feb 2012 11:43:35 -0500
 From: Rich Lacasse rlaca...@nrao.edu
 Subject: [casper] Gerbers for ROACH
 To: casper@lists.berkeley.edu
 Message-ID: 4f354937.9040...@nrao.edu
 Content-Type: text/plain; charset=ISO-8859-1; format=flowed

 On the CASPER web site, there is a link for Gerber files and a link to
 get a PADS PCB viewer.  I wanted to have a look at the board layers so
 gave this a try and ran into two problems.  First, the Gerbers are not
 a standard gerber file, viewable by the gerber viewers I already had.
 Second, the downloaded product from Mentor complained that the file I
 gave it to look at, (top silk screen layer) was not compatible with the
 current version of their viewer.  Any advice on how to view the various
 board layers?

 Thanks,
 Rich



 End of casper Digest, Vol 51, Issue 5
 *






-- 
Francois Kapp

Sub-system Manager
Digital Back End
meerKAT

SKA South Africa
Third Floor
The Park
Park Road (off Alexandra Road)
Pinelands
7405
Western Cape
South Africa

Latitude: -33.94329 (South); Longitude: 18.48945 (East).

(p) +27 (0)21 506 7300
(p) +27 (0)21 506 7360 (direct)
(f) +27 (0)21 506 7375
(m) +27 (0)82 787 8407

Re: [casper] Roach I Board Power Requirements

[Francois Kapp]

Hi Joe,

I second John's suggestion (we used the same module for a battery
powered RFI analysis box), but here are the design limits:
12V - 3.4A
5V - 6.8A
5VAUX - 1A
3.3V - 3.5A

These are assuming a full FPGA running at high clock rate, something
that is difficult to achieve in practice, so you can take it as
maximum.

Regards,
Francois


On Thu, Jan 19, 2012 at 9:05 PM, Dan Werthimer d...@ssl.berkeley.edu wrote:

 hi joe,

 the DC-DC converters are standard on the roach boards,
 so you only need to supply 3.3, 5 and 12 volts to the ATX connector.

 if you use john ford's $30 pico-PSU-90, then you only have to supply
 one voltage:   +12 Volts at 8 amps.

 i'm not sure about the maximum currents for each of the
 roaches three input voltages.
 i'm cc'ing the casper lists -  someone will know.

 i can measure these currents with our clamp on amp-meter, but these will
 change a bit, depending on how heavily you load the FGPA and what
 ADC's are plugged into the roach board.

 best wishes,

 dan




 On Thu, Jan 19, 2012 at 10:53 AM, Joseph Greenberg jgree...@nrao.edu
 wrote:

 Hi Dan,
 Thanks for the reply.


 Dan Werthimer wrote:


 hi joe,

 can you leave the DC-DC converters on the roach board?

 Yes.  Are they standard on all Roach I boards or do we have to specify
 them?

 then you only need to supply the 12, 5 and 3.3 volts that
 come from the ATX power supply.

 What is the maximum current we would need to supply for each of these
 Voltages?

 Thanks,
 Joe




 best wishes,

 dan


 On Thu, Jan 19, 2012 at 10:28 AM, Joseph Greenberg jgree...@nrao.edu
 wrote:

 We at NRAO are going to mount the Roach I board on a custom board, rather
 than using the usual chassis.
 We will have DC-DC converters on the board.
 The Roach documentation states:
 Voltages of 12V, 5V, 3.3V, 2.5V, 1.8V, 1.5V, 1V and 1.2V aux rails.

 Is there any specification of what maximum currents we need to supply for
 each voltage?

 Thanks,
 Joe







-- 
Francois Kapp

Sub-system Manager
Digital Back End
meerKAT

SKA South Africa
Third Floor
The Park
Park Road (off Alexandra Road)
Pinelands
7405
Western Cape
South Africa

Latitude: -33.94329 (South); Longitude: 18.48945 (East).

(p) +27 (0)21 506 7300
(p) +27 (0)21 506 7360 (direct)
(f) +27 (0)21 506 7375
(m) +27 (0)82 787 8407

Re: [casper] ROACH and ADC RFI tests

[Francois Kapp]

Hi All,

I don't have our own results in a handy packaged format, but this correlates
well with what we saw.  If the 533 MHz is fundamental, it is pure PowerPC -
the clock is generated on chip from a lower frequency reference.

Regards,
Francois

On Tue, Sep 6, 2011 at 10:29 PM, John Ford jf...@nrao.edu wrote:

  John,
  It's interesting that there is almost no evidence of the 500 MHz ADC
  clock,
  except perhaps the 2000 MHz tone. I guess that means the ADC clock
  transmission lines are well terminated and not radiating. Most of the
  lines
  look like they are related to the PPC (multiples of 33 MHz) and the 100
  MHz
  system clock.

 You're right that most of this is due to the PPC and ancillary circuits.
 I expect that it's because the FPGA is not loaded.  The line from the
 clock to the ADCs is very short.  I am going to test it again later with
 the FPGA running a spectrometer bof, and all the xaui cables connected and
 passing data around.

 For now, this is enough to tell me that we need to be thinking ahead to
 packaging VEGAS.

 John

  Glenn
 
  On Tue, Sep 6, 2011 at 1:14 PM, John Ford jf...@nrao.edu wrote:
 
  Hi all.
 
  We tested a ROACH and and 2 ADC boards (3 GS/s boards) in our anechoic
  chamber to get a feel for the emissions to expect from the new
  spectrometer being designed.  The ADC clock was running at 500 MHz.
 
  The results of the test are attached.  In summary, to use these at our
  site, we will have to have a supplementary shielded enclosure in
  addition
  to our shielded equipment room.
 
  Thanks to Carla Beaudet at NRAO for the testing.
 
  (If anyone has anything they'd like us to test in the chamber, let me
  know.)
 
  John
 






-- 

Francois Kapp

Sub-system Manager
Digital Back End
meerKAT

SKA South Africa
Third Floor
The Park
Park Road (off Alexandra Road)
Pinelands
7405
Western Cape
South Africa

Latitude: -33.94329 (South); Longitude: 18.48945 (East).

(p) +27 (0)21 506 7300
(p) +27 (0)21 506 7360 (direct)
(f) +27 (0)21 506 7375
(m) +27 (0)82 787 8407

Re: [casper] KatADC

[Francois Kapp]

Hi Tom,

The 4GSPS version of KatADC is based on an up-tested version of the
ADC08D1520, which is designated S7002396.  It is unclear whether this
will be released as a commercial product by National - a few inquiries
to them couldn't hurt the cause.  So far we have only received the
one.  The rest of the board is the same as the wide-band front-end
KatADC version, which is the standard version that Mo builds (i.e.
with BOM: 
http://casper.berkeley.edu/wiki/images/7/71/KATADC1.3BOM_HF_Build.pdf).

If you can extract a chip from National it should be a simple matter
to get one built.

Regards,
Francois

On Wed, Jun 1, 2011 at 8:26 PM, Tom Kuiper kui...@jpl.nasa.gov wrote:
 On 06/01/2011 11:19 AM, John Ford wrote:

 I'd like to know more about this ADC on the hardware wiki page under
 KatADC:

 Dual 8-bit 2.0GSPS (or Single 8-bit 4.0GSPS), National Semiconductor
 ADC08D1520/S7002396 ADC, RF Front-End

 However, the KatADC page doesn't seem to have any information about it.
 Can someone direct me to or send me information about this?


 Hi Tom.  The data sheet's linked here:

 http://www.national.com/ds/DC/ADC08D1520.pdf


 That's the original 3 Gsamp/s version.  I was asking about the 4 Gsamp/s
 version (see the /S7002396?).  This data sheet probably predates the newer
 version.

 Cheers

 Tom

 From

 https://casper.berkeley.edu/wiki/KatADC

 John



 Many thanks,

 Tom

 --
 I or me? http://www.oxforddictionaries.com/page/145








 --
 I or me? http://www.oxforddictionaries.com/page/145







-- 

Francois Kapp

Sub-system Manager
Digital Back End
meerKAT

SKA South Africa
Third Floor
The Park
Park Road (off Alexandra Road)
Pinelands
7405
Western Cape
South Africa

Latitude: -33.94329 (South); Longitude: 18.48945 (East).

(p) +27 (0)21 506 7300
(p) +27 (0)21 506 7360 (direct)
(f) +27 (0)21 506 7375
(m) +27 (0)82 787 8407

Re: [casper] The casper library status

[Francois Kapp]

Hi Wan,

Apologies for not responding sooner, I had a personal issue that kept
me away from email for a while.  Questions like these are best
answered by the Casper mailing list (cc'd), where you are much more
likely to get a quick, accurate and up to date response.

Regards,
Francois

On Wed, Apr 20, 2011 at 3:49 AM,  wan.ch...@csiro.au wrote:
 Hi Francois:



 I did not see any capsper library update from git since last year august. Do
 you immigrate the latest library to other server?



 And what’s the status of Xilinx ISE tools? Do you upgrade the Xilinx ISE
 tool bundle to version 12? I find current casper library is not compatible
 with ISE version 12 because some OPB library is removed from EDK.



 Thanks and happy Easter.





 Wanxiang Cheng

 SKA Engineering

 CSIRO Australia Telescope National Facility

 Vimiera  Pembroke Rds

 Marsfield NSW Australia 2122

 Ph 61-2-9372-4515

 Fx 61-2-9372-4310

 Mob 0406 421 776

 www.atnf.csiro.au





-- 

Francois Kapp

Sub-system Manager
Digital Back End
meerKAT

SKA South Africa
Third Floor
The Park
Park Road (off Alexandra Road)
Pinelands
7405
Western Cape
South Africa

Latitude: -33.94329 (South); Longitude: 18.48945 (East).

(p) +27 (0)21 506 7300
(p) +27 (0)21 506 7360 (direct)
(f) +27 (0)21 506 7375
(m) +27 (0)82 787 8407

Re: [casper] ZDOK+ Layout?

[Francois Kapp]

 A follow up question.  From the data sheet I've found concerning the
 6367555-1, it is not clear what (if anything) the utility contacts need to
 be attached to.  What I read seems like a suggestion that is open to the end
 application.  Can someone enlighten me please?


Hi Dan,

Yes, it is open to the application, but for iBob (and ROACH) it is used for
power.  See the schematic for your revision - page 2 under Z-dok+(P/G).
The schematics are linked to on the wiki (
http://casper.berkeley.edu/wiki/IBOB).

Regards,
Francois

Re: [casper] ZDOK+ Layout?

[Francois Kapp]

Hi Dan,

The 6367555-1 is the right one.  It's the same as the 1367555, but more
RoHS compliant.  It has the utility Contacts on the side in addition to the
40 pairs on the 1367130-1.

Regards,
Francois

On Thu, Feb 17, 2011 at 7:13 PM, Daniel S. Klopp dkl...@nrao.edu wrote:

 I am designing a board with a ZDOK+ connector to interface with an IBOB.
  According to the wiki http://casper.berkeley.edu/wiki/IBOB , it uses a
 Tyco ZDOK+ 40 differential pair connector and provides a link to the
 website.  Using the datasheet I was under the impression I would use
 1367130-1 layout with 40 pairs.  But when I measured the dimensions of the
 physical board and looked at the pin layout of another connector we have in
 the lab, it looks as if the correct layout to use is actually 1367555. 
 http://www.tycoelectronics.com/commerce/DocumentDelivery/DDEController'6367555
 ?Action=showdocDocId=Customer+Drawing%7F1367555%7FB%7Fpdf%7FEnglish%7FENG_CD_1367555_B.pdf%7FN-Ahttp://www.tycoelectronics.com/commerce/DocumentDelivery/DDEController?Action=showdocDocId=Customer+Drawing%7F1367555%7FB%7Fpdf%7FEnglish%7FENG_CD_1367555_B.pdf%7FN-A.
   However, that drawing has me a bit nervous as it is a customer provided
 document and not an official Tyco document.

 Could someone please confirm the EXACT connector layout I should use?

 Thank you,
 -Dan


 --
 :(){ :|:  };:

Re: [casper] new memo - external adjustment for Atmel/e2v interleaved ADC's

[Francois Kapp]

Hi Hong,

Nice work, I think the difference between simulated and actual isn't that
bad - I don't think your simulation is quantised?  I'm more interested in
seeing how this behaves over frequency.  If you optimise at one frequency,
does that generally improve things, or are there strong frequency dependent
effects in the ADC?  Another issue is temperature - it would be interesting
to see how it behaves with small temperature changes.  I imagine one would
have to re-calibrate for temperature changes, but it would be nice to put
some bounds on the changes that can be tolerated.  If we lend you a katADC
would you be able to repeat this and compare?

-Francois

On Wed, Feb 2, 2011 at 8:41 AM, Hong Chen chen_1...@berkeley.edu wrote:

 Hello Paul,

 According to the datasheet, the adjustment steps are really small: 0.25LSB
 for offset adjustment, 0.005dB for gain adjustment and 4ps for phase
 adjustment.  This resolution is very fine for the data we were dealing with
 (~100MHz, 8 bits), so theoretically we should get close to a perfect result,
 which the achieved one cannot even compare with.
 The reason why we can't achieve the predicted result seems to be beyond the
 interleaving issue, and currently my best guess is the existence of harmonic
 frequencies.  When I look at the raw data directly (from a single ADC, with
 ~10MHz input signal frequency) and compare it with the 8-bit simulated data
 generated by matlab, I can see very obvious difference, the actual curve is
 rougher for some reason(attached graphs). It appears to be very difficult to
 do the perfect interleaving adjustment or to calculate the gain/phase when
 the other interfering factors are strong.

 Thank you for your question. I'm sorry I don't really know what features
 of the ADCs are limiting the performance.

 Best,
 Hong


 On Sat, Jan 29, 2011 at 7:20 AM, Paul Demorest pdemo...@nrao.edu wrote:

 Hi Hong and Mark,

 Thanks for writing this memo!  This topic is important for our pulsar
 instruments.  I was wondering if you know what the limiting factor is in how
 good the adjustment can be.  For example, given the available resolution of
 the gain/phase adjustments there should be a 'theoretical best' performance.
  How close is your adjustment to achieving that?  Are there any other
 features of the ADCs that might limit the performance?

 -Paul


 On Fri, 28 Jan 2011, Hong Chen wrote:

  Dear Casperites,

 Mark and I have finished a memo on the external adjustment for Atmel/e2v
 interleaved ADC's and
 it is item 40
 http://casper.berkeley.edu/wiki/images/7/7f/Atmel_iadc_external_adjust.pdf
 in

 Casper wiki's memos section.

 This memo investigates the interleaving issue on the e2v 1Gsps iADC board
 and implements python code to adjust the iadc gain, offset and delay by
 adjusting the control registers through the software interface. The result
 shows it is able to reduce the interleaving error by about 60%~85%. Your
 questions and comments will be appreciated.

 Thanks,
 Hong Chen





-- 

Francois Kapp

Sub-system Manager
Digital Back End
meerKAT

SKA South Africa
Third Floor
The Park
Park Road (off Alexandra Road)
Pinelands
7405
Western Cape
South Africa

Latitude: -33.94329 (South); Longitude: 18.48945 (East).

(p) +27 (0)21 506 7300
(p) +27 (0)21 506 7360 (direct)
(f) +27 (0)21 506 7375
(m) +27 (0)82 787 8407

Re: [casper] casper Digest, Vol 39, Issue 2

[Francois Kapp]

Thanks Robert,

I'm afraid this confirms my fears that it is frequency dependent and
therefore a problem for wideband use.  The comment about the ADC083000 is
more encouraging though...

-Francois

On Wed, Feb 2, 2011 at 8:52 PM, Robert F. Jarnot 
robert.f.jar...@jpl.nasa.gov wrote:

 Dana,

I am not sure if this is simply the clock getting into the data path.  I
 remember thinking of it more as the ADC characteristics 'falling to pieces'
 subtly when clocked at its maximum rate.  If memory serves me correctly,
 lowering the sample rate of each ADC from 1 Gsps to 500 Msps improved the
 behavior dramatically, implying that something non-linear was going on.  As
 for the interleaving spurs, I am pretty sure that when we minimized them at
 HF, they became worse at LF.  We ended up just optimizing at LF, and made
 sure that we did not change the clock amplitude.  We did not investigate how
 things changed with temperature, but in a lab environment we did not have to
 go back and periodically change the ADC matching.

 Regards,

 Robert


 On 02/02/2011 10:20 AM, dana whitlow wrote:

 If offsets change with clock level, is that not an indication of clock
 getting
 into the analog input?  If so, it is probably a combination of a little
 bit on
 the ADC chip itself and some from the board layout, which in principle
 could be reduced (but what a pain to figure out just what to do!).

 Regarding interleaving spurs, what happens if one adjusts the interleaving
 for minimal spurs at HF?  Do they then get worse at LF?

 Dana Whitlow
 Arecibo Observatory


 On 2/2/2011 1:32 PM, Robert F. Jarnot wrote:

 Hong, Paul, Francois,

 We (at JPL) have spent a fair amount of time in the past
 struggling with interleaving the e2v AT84AD001B (iADC/iBOB
 combination).  At the highest sample rates (Glenn Jones kurtosis
 spectrometer for example) we find that matching with low frequency
 signals as Hong described works very well.  With high frequency
 signals however the results are quite different, and less
 encouraging.  We find that matching ADC characteristics with low
 frequency signals does not necessarily lead to good results with high
 frequency signals.  This is supported by some of the statements in the
 ADC FAQs at the e2v web site.  Furthermore, we have seen some other
 unexpected behavior, such as offsets changing with the amplitude of
 the ADC clock signal (even within the range specified by the data
 sheet).  At lower sample rates the AT84AD001B behaves much better, and
 I suspect that is why there is now an AT84AD001C.

 Our experience with interleaving the ADC083000 at 3 Gsps has been
 very good in comparison.

 Robert Jarnot

 Message: 2
 Date: Tue, 1 Feb 2011 22:41:14 -0800
 From: Hong Chenchen_1...@berkeley.edu
 Subject: Re: [casper] new memo - external adjustment for Atmel/e2v
 interleaved ADC's
 To: Paul Demorestpdemo...@nrao.edu
 Cc: CASPER Listscasper@lists.berkeley.edu
 Message-ID:
 aanlktikmbeppzl9jbghsdnucgfw+6tgn0dioh_29a...@mail.gmail.comaanlktikmbeppzl9jbghsdnucgfw%2b6tgn0dioh_29a...@mail.gmail.com
 
 Content-Type: text/plain; charset=iso-8859-1

 Hello Paul,

 According to the datasheet, the adjustment steps are really small:
 0.25LSB
 for offset adjustment, 0.005dB for gain adjustment and 4ps for phase
 adjustment.  This resolution is very fine for the data we were
 dealing with
 (~100MHz, 8 bits), so theoretically we should get close to a perfect
 result,
 which the achieved one cannot even compare with.
 The reason why we can't achieve the predicted result seems to be
 beyond the
 interleaving issue, and currently my best guess is the existence of
 harmonic
 frequencies.  When I look at the raw data directly (from a single
 ADC, with
 ~10MHz input signal frequency) and compare it with the 8-bit
 simulated data
 generated by matlab, I can see very obvious difference, the actual
 curve is
 rougher for some reason(attached graphs). It appears to be very
 difficult to
 do the perfect interleaving adjustment or to calculate the gain/phase
 when
 the other interfering factors are strong.

 Thank you for your question. I'm sorry I don't really know what
 features of
 the ADCs are limiting the performance.

 Best,
 Hong


 On Sat, Jan 29, 2011 at 7:20 AM, Paul Demorestpdemo...@nrao.edu
 wrote:

  Hi Hong and Mark,

 Thanks for writing this memo!  This topic is important for our pulsar
 instruments.  I was wondering if you know what the limiting factor
 is in how
 good the adjustment can be.  For example, given the available
 resolution of
 the gain/phase adjustments there should be a 'theoretical best'
 performance.
   How close is your adjustment to achieving that?  Are there any other
 features of the ADCs that might limit the performance?

 -Paul


 On Fri, 28 Jan 2011, Hong Chen wrote:

   Dear Casperites,

 Mark and I have finished a memo on the external adjustment for
 Atmel/e2v
 interleaved ADC's and
 it is item 40

 

Re: [casper] thermal design of ROACH 2

[Francois Kapp]

Hi Jonathan,

We have not had a chance to do the same level of detail for ROACH2
yet, although we are working on it.  I'll ask Philip to do a ROACH run
with your parameters so we can start to form an idea of what would
happen.

Regards,
Francois

On Thu, Oct 28, 2010 at 11:28 PM, Jonathan Weintroub
jweintr...@cfa.harvard.edu wrote:
 I think that the ROACH design team does fairly sophisticated thermal
 analysis using a model of enclosure, PCB and cooling fans.  Is this analysis
 available yet for ROACH 2 and where might I find some data?

 Is it possible extrapolate from the models (or perhaps rerun the models) to
 predict how the ROACH 2 might behave thermally at 4,500m elevation (summit
 of Mauna Kea)?  Atmospheric pressure there is 60% of sea level, and our
 equipment room is air conditioned (servoed to 60 degrees ambient, say) but
 unpressurized.

 Thanks,

 Jonathan

Re: [casper] ROACH basic questions

[Francois Kapp]

Hi Daniel,

Welcome to Casper - the recommendations you received so far are all
good, the tutorials will help you a lot.  I think one of the things
you must bear in mind when working on an open source project like
this, is that you have to try to keep up to date - keep an eye on the
mailing list in particular and also look out for additions to the wiki
- so the printed copy is good to read now, but be aware that sometimes
things change!

Some logs exist for board configurations, so if you do run into
problems, let us know your serial number and any version numbers of
things you have changed.

If you are in Casper for the long term it would be good to start
planning to attend the next workshop where you can put faces to all
the email addresses, although that is probably only in about a year's
time from now.

Regards,
Francois

On Tue, Sep 28, 2010 at 3:02 AM, Daniel Esteban Herrera Pena
danherr...@udec.cl wrote:
 Hi Dan  John,

 Thank you very much for your quick reply, the wiki pages of ROACH I have
 printed out and I keep it as a bible! now I'm going to digest the tutorial
 section you mentioned. The only thing I have done is basic communication
 through serial link, so there I will have a lot to play with.

 About the questions, don't hesitate that the minor inquiry I would have
 I'll post here :).

 Cheers!

 Daniel.

 Hi Daniel.

 I agree with what Dan has said.  Go to
 http://casper.berkeley.edu/wiki/Main_Page, look down to the menu on the
 left, and find the tutorials entry.

 As far as your questions about versions, etc., I think you have to be a
 bit careful about making sure the versions match each other.  In Green
 Bank, we have not worried about messing around in the katcp or the borph,
 or the uboot, we just use what is recommended.  See the
 http://casper.berkeley.edu/wiki/ROACH web page, and near the bottom is a
 list of documents about ROACH.  They are pretty complete, and I hope up to
 date.  Can someone confirm the latest versions of ROACH stuff?

 Another recommendation that I have is to learn well your tool to analyse
 the output of the system, either matlab or python, whichever you know
 best.

 Good luck, and please do ask questions on the list so that all new users
 can benefit from the answers!

 John



 hi daniel,

 i recommend you do some of the roach tutorials to learn
 how to use your system  - i think these tutorials
 include blinking an LED,  adding numbers together,
 (these tutorials teach how to use the operating system,
 simulink tools, borph)
 then building and testing a spectrometer, a correlator,
 (these teach how to use the DSP blocks),
 and using the 10Gbit ethernet interface to send
 high speed data into a computer and GPU.

 best wishes,

 dan



 On 09/27/2010 04:25 PM, Daniel Esteban Herrera Pena wrote:
 Dear CASPER team,

 I'm glad to be subscribed in your mailing list, I hope to receive some
 advice from you these days.

 I'm here because I just joined an Astronomy project in University of
 Concepcion, Chile. I'm the guy who will be in charge of programming the
 ROACH, so I would like to be in touch with the creators of this awesome
 board.

 My experience is related to hardware synthesis/design with boards like
 Basys, Nexus and Virtex 2 XUP, programming on verilog with Xilinx
 software
 (ISE, some entry-level with EDK).

 The problem here (for me) is that the ROACH system have almost nothing
 to
 do with the boards I had programmed before (or at lest what I could see
 till now). This ROACH have file-system, kernel and a bootloader, it's
 almost a PC.

 I saw the ROACH wiki space, and from there I would like to know:

 1.- (from Getting started with ROACH): ROACH comes with Busybox
 filesystem, why adding another (based on Debian Etch)? What advantages
 have compared with Busybox?

 2.- (from ROACH kernel uboot update): Where can I see the improvements
 of
 the lastest uboot image? Do you recommend me to update the default
 version?

 3.- (From setting BORPH on ROACH): I don't clearly have the functions
 of
 the kernel and the operating system (BORPH) on the ROACH. Are those the
 same?

 4.- (From setting BORPH on ROACH): What are the differences between the
 minimal root filesystem and the full-featured filesystem?

 5.- Do you have any examples of code that I could program the board?

 6.- What is the typical step-by-step instructions for doing something
 on
 the ROACH making use of the integrated FPGA?

 I hope you guys give a hand understanding how this system really works,
 I
 really appreciate any contributions to my clarification. Thank you in
 advance!

 Best,

 Daniel.





 --

 Dan Werthimer
 Space Sciences Lab and Berkeley Wireless Research Center
 University of Calfornia, Berkeley













-- 

Francois Kapp

Sub-system Manager
Digital Back End
meerKAT

SKA South Africa
Third Floor
The Park
Park Road (off Alexandra Road)
Pinelands
7405
Western Cape
South Africa

Latitude: -33.9359 deg.; Longitude: 18.5102 deg.

(p) +27 (0)21 506 7300
(p) +27 (0

Re: [casper] Roach outline

[Francois Kapp]

Hi Rick,

I just posted the Gerbers to the wiki, you can get it from
http://casper.berkeley.edu/wiki/Image:Roach103-CAM.zip

The readme has a description of the layers.

-Francois

Rick Raffanti wrote:
 Does anybody have a drawing of the roach, PCB fab drawing, Gerbers,
 something?
 Thanks,
 Rick
 
 
 

[casper] Invitation to attend ROACH II Design Review

[Francois Kapp]

1) All casper collaborators and other interested people are invited to attend a
design review of ROACH II on Tuesday March 16, 16:00 to 18:00 GMT. Local Time:
http://www.timeanddate.com/worldclock/fixedtime.html?day=16month=3year=2010hour=16min=0sec=0p1=0

2) Telecon line: call or skype_out  510-643-3833 (USA)

3) VNC connection information will be emailed out later.

4) LISTEN ONLY:  As this is going to be quite a large meeting, please keep your
line muted unless you are designated as an external reviewer (see list below).
We'd appreciate it if you mostly listen during this meeting unless you have
something urgent and short to say.  If you have questions, suggestions, or
comments, we'd prefer you email them during or after the meeting.  Thanks.

5) Presenters: David George(DG), Francois Kapp(FK), Jason Manley(JM), Philip
Gibbs(PG)

6) Reviewers: Henry Chen, Alan Langman, Pierre Droz, David Hawkins, Matt Dexter,
John Ford, Glenn Jones, Robert Navarro, Dan Werthimer, Kris Adami

7) Chair: Francois Kapp

8) Roach II info is at http://casper.berkeley.edu/wiki/ROACH2

9) Agenda:

The purpose of this review to present the big picture, block diagram and
specifications of ROACH II and to verify these.  We will not be reviewing
schematics and details of the board on Tuesday.

Agenda:
--
 a) ROACH I, what was right, what was wrong? (FK)
 b) Why ROACH II? (FK)
 c) The place of a ROACH II board - where should it be used w.r.t. MORPH, iBOB,
Bee2, Bee3, Roach I. (JM)
 d) Specifications and what motivated them? (JM)
 e) Financial Implications - estimated cost. (DG)
 d) Block diagram review highlighting changes from ROACH I. (DG)
 e) Mezzanine boards - pin out, mechanical, planned and possible boards. (PG)
 f) Short discussion of mechanical and thermal issues. (PG)
 g) Tool flow. (JM)
 h) Applications (user cases). (JM)
 j) Downgrading to smaller Xilinx devices - what is lost? (DG)
 k) Schedule and plans for prototypes and production, hardware, layout, reviews,
testing, tools and assembly. (DG)
 l) Risks - cost of devices, availability of devices, technical. (FK)
 m) Open discussion.
 n) Action items.

Re: [casper] ROACH FPGA chips - part number

[Francois Kapp]

Hi John,

Part numbers:

XC5VSX95T-1FF1136C - this is the lowest speed grade, with lead, commercial 
temperature range.  Available today for purchase from Avnet ($2,735.00, 4 wk 
lead time) or Nu Horizons ($ 2,789.70, 22 in stock in NA).


Lead-free is possible and the speed grade could also be a -2.  -3 is not 
available in SX95T (or SX240T).


Does anyone have a requirement for lead-free?

-Francois

John Ford wrote:

Hi John,

The ROACH can take the LX110T, LX155T, or SX95T. The LX series has very
few multipliers, even the new LX155T only has 128, which is still fewer
than on the IBOB. For sheer size of FFT, we're usually multiplier-limited.
I tried building a PFB for the LX110T on the ROACH prototype and ran out
of multipliers at only about 25% logic utilization.

That build was a 2^13 real PFB (2^12 complex channels) with 4 taps and 4
parallel inputs. Using 8 parallel inputs to get the full bandwidth of the
ADCs, I think that dropped the design down to something like 1K channels.

I think the 64 DSP48E's of the LX110T is definitely not the way to go for
DSP applications. The 128 on the LX155T is a slightly better balance, but
you're still losing 80% of the multipliers for a 65% increase in logic.


Thanks, Henry.  The SX95T is available for a reasonable price (~$2795.00),
so I will go with those.  Do you have an exact part number for that chip?

Just for fun I priced an SX240 that's considered for roach-II.  They're
$15,500 each!  Still cheaper than a BEE-2, though...

John


Thanks,
Henry

John Ford wrote:

Hi all.  What are the recommended FPGA's for the ROACH?  I want the one
that will allow me to build the biggest PFB/FFT's in the chip.  It's not
clear to me that the SX is the best one, but I really have no idea.

What say you all?

John