Given the following scenario... A high speed sampler comprised of...
1 iBOB with logic fabric running at 200MHz, derived from ADC0
1 ADC2x1000-8 operating in its interleaved mode with an 800MHz
sampling clock
1 1PPS Site Timing Reference applied to the ADC's SYNC IN
Is it possible, using the four SYNC outputs of the ADC block, to
ascertain which of the 8 samples presented during a logic clock
cycle was most closely aligned with an in-coming 1PPS signal?
Randy
