Hi, Paul,
On Mar 4, 2010, at 12:46 , Paul Demorest wrote:
Or did you already know that and were just needling Dan? :-)
No, I really was curious why there would be four copies of the same
thing!
I notice that you didn't deny that you were needling Dan. :-)
To summarize your explanation Dave, the four syncs really do
represent the input sync sampled on each of 4 ADC clocks.
Well, to be precise, the four syncs represent the input sync sampled
at four times the FPGA clock rate with all the jitter of the FPGA's DCM.
But there is also some uncertainty after each power-up that means
sync0 doesn't necessarily match up with data0, etc.
This is exactly my understanding. Furthermore, the sync signal will
typically be longer than one ADC sample cycle, so one needs to be
careful about detecting the edge of the sync signal. This can get a
little tricky with 4 parallel inputs. The ATA DDC just uses sync0 to
synchronize the internal 1 PPS with the external 1 PPS. Any slop/
imprecision there gets taken out in calibration.
Is that right?
It's right in that it captures my explanation, but you'll notice I
didn't claim my explanation is correct (though I think it is). :-)
Dave
