The four sync lines are supposed to represent the ADC sample where the
sync was input (as Paul suggests). And this mostly does work, however,
it breaks when using two ADCs on one board, because the sample clock
for the second ADC's 1PPS is derived from the first ADC, not from that
second ADC. This is then a problem for correlator applications where
you have two ADCs in one IBOB where you can have an unknown phase on
that second ADC.
In reality, most people just "OR" the four sync outputs together,
resulting in an unknown phase difference which gets calibrated-out as
Dave suggests.
Jason
On 04 Mar 2010, at 12:46, Paul Demorest wrote:
On Thu, 4 Mar 2010, David MacMahon wrote:
On Mar 4, 2010, at 11:52 , Paul Demorest wrote:
I have to ask.. if all four syncs are the same, why are there four
of them? ;)
Just to clarify, they represent the same signal sampled at (i.e.
registered using) four different phases (0/90/180/270) of the FPGA
clock.
Or did you already know that and were just needling Dan? :-)
No, I really was curious why there would be four copies of the same
thing!
To summarize your explanation Dave, the four syncs really do
represent the input sync sampled on each of 4 ADC clocks. But there
is also some uncertainty after each power-up that means sync0
doesn't necessarily match up with data0, etc. Is that right?
-Paul
