On Thu, 4 Mar 2010, David MacMahon wrote:
On Mar 4, 2010, at 11:52 , Paul Demorest wrote:
I have to ask.. if all four syncs are the same, why are there four of them?
;)
Just to clarify, they represent the same signal sampled at (i.e. registered
using) four different phases (0/90/180/270) of the FPGA clock.
Or did you already know that and were just needling Dan? :-)
No, I really was curious why there would be four copies of the same thing!
To summarize your explanation Dave, the four syncs really do represent the
input sync sampled on each of 4 ADC clocks. But there is also some
uncertainty after each power-up that means sync0 doesn't necessarily match
up with data0, etc. Is that right?
-Paul
