Hi, Jason, On Mar 4, 2010, at 13:18 , Jason Manley wrote:
And this mostly does work, however, it breaks when using two ADCs on one board, because the sample clock for the second ADC's 1PPS is derived from the first ADC, not from that second ADC.
I think the ibob startup software expends to a non-trivial amount of effort to ensure that the two ADC output clocks are in phase, so sampling ADC1's sync using a clock derived from ADC0's output clock shouldn't be much worse than using a clock derived from ADC1's clock. Where it does break down, I think, is across multiple ibobs.
Another small detail is that the sync signal passes straight from the input sma connector to the FPGA (possibly being buffered in between), but I don't know whether it is delayed any in the FPGA (i.e. in the "yellow block") to compensate for the pipeline delay of the ADC.
Dave
