Hi Alec, Your compilation error indicates that running system generator failed. You need to look in the directory created with the design name for the system generator logs to see where the error occurred. I can't remember the exact name but dig through the sub directories for .log files and the search for "error" to see if you can find an error message. I'm not familiar enough with the casper_fpga library to offer much advice. Does fpga.is_connected() return True?
Does the .fpg file look the same as the ones that work for you? Glenn Dear Casperites, I've been trying to complete tutorial 4 <https://casper.berkeley.edu/wiki/Tutorial_Wideband_Pocket_Correlator> for the Roach2, and have run into difficulty compiling either the .slx <https://github.com/casper-astro/tutorials_devel/blob/tutorials_update_2016/tut4/poco_wide_12_r316_new.slx.r2013a.tar.gz> or .mdl <https://github.com/casper-astro/tutorials_devel/blob/tutorials_update_2016/tut4/poco_wide_12_r316_new.mdl.tar.gz>files given for the Roach 2, or uploading the precompoliled .fpg <https://github.com/casper-astro/tutorials_devel/blob/tutorials_update_2016/tut4/poco_wide_1kat.fpg> file onto my Roach2 (using either the python scripts given or simply by command-line uploading the .fpg using ipython). My error messages are attached in this Google Drive document. <https://docs.google.com/document/d/1RY5LSS7mRx3o2Zm6Gyy_a8jhEjJr2bM1k9CCN9ov0bw/edit?usp=sharing> For tutorials 1-3 I have had no trouble compiling the .slx files and upload the corresponding .fpg files to my Roach2. I've made sure in the .slx I cite above (for tutorial 4) that the XSG_core_config block does not have a broken link and that the settings are as follows: - Hardware platform: Roach2:sx475t - User IP clock source: adc0_clk - User IP clock rate (MHz): 200, (and that the adc1 and adc0 are correspondingly clocked to 800 MHz) - Sample period: 1 - Synthesis tool: XST Any advice on how I can complete tutorial 4? Best, Alec
