No, these warnings are almost always safe to ignore. You want to look for
error messages. You will always get lots of warning messages.

Glenn

On Fri, Nov 4, 2016 at 5:09 PM, Alec Josaitis <josai...@umich.edu> wrote:

> Dear Casperites,
>
> One other thing I should clarify, is that before the XSG generation fails,
> the following warning is given in Matlab, regarding inconsistent ADC time
> samples. Does this provide insight as to why my compilation fails?
>
>
> Warning: Inconsistent sample times. Sample time (0.25) of signal driving
> input port 1 of 'tut4_update/adc2/tut4_update_adc2_user_data_valid'
> differs from the expected
> sample time ([0, 0]) at this input port.
> > In 
> > /opt/Xilinx/14.7/ISE_DS/ISE/sysgen/bin/lin64/xlCompileGenerateMdl.p>xlCompileGenerateMdl
> at 203
>   In 
> /opt/Xilinx/14.7/ISE_DS/ISE/sysgen/bin/lin64/xlGenerateButton.p>xlGenerateButton
> at 302
>   In gen_xps_files at 323
>   In casper_xps>run_Callback at 158
>   In casper_xps at 88
>   In 
> @(hObject,eventdata)casper_xps('run_Callback',hObject,eventdata,guidata(hObject))
>
>
> On Fri, Nov 4, 2016 at 5:02 PM, Alec Josaitis <josai...@umich.edu> wrote:
>
>> Dear Glenn,
>>
>> Thanks for getting back to me. Unfortunately, the .log files don't reveal
>> any hints to this issue; below is a print-out of the entire .log file (it
>> is only five lines long). None of these lines refer to
>> 'fpga.is_connected()'.
>>
>> --------------------------------- Version Log
>> ----------------------------------
>> Version                                 Path
>> System Generator                        /opt/Xilinx/14.7/ISE_DS/ISE/sy
>> sgen
>> Matlab 8.0.0.783 (R2012b)               /usr/local/Matlab/2012b
>> ISE                                     /opt/Xilinx/14.7/ISE_DS/ISE
>>
>>
>> Do you have a copy of tutorial 4 that you were able to successfully
>> compile? Upon receiving it, did you have to update any casper_XPS library
>> blocks, or update the .mdl file in any way before attempting to compile it
>> with the casper_xps script in MATLAB?
>>
>> Best,
>> Alec
>>
>> On Wed, Nov 2, 2016 at 3:29 PM, G Jones <glenn.calt...@gmail.com> wrote:
>>
>>> Hi Alec,
>>> Your compilation error indicates that running system generator failed.
>>> You need to look in the directory created with the design name for the
>>> system generator logs to see where the error occurred. I can't remember the
>>> exact name but dig through the sub directories for .log files and the
>>> search for "error" to see if you can find an error message.
>>> I'm not familiar enough with the casper_fpga library to offer much
>>> advice. Does fpga.is_connected() return True?
>>>
>>> Does the .fpg file look the same as the ones that work for you?
>>>
>>>
>>> Glenn
>>> Dear Casperites,
>>>
>>> I've been trying to complete tutorial 4
>>> <https://casper.berkeley.edu/wiki/Tutorial_Wideband_Pocket_Correlator>
>>> for the Roach2, and have run into difficulty compiling either the .slx
>>> <https://github.com/casper-astro/tutorials_devel/blob/tutorials_update_2016/tut4/poco_wide_12_r316_new.slx.r2013a.tar.gz>
>>> or .mdl
>>> <https://github.com/casper-astro/tutorials_devel/blob/tutorials_update_2016/tut4/poco_wide_12_r316_new.mdl.tar.gz>files
>>> given for the Roach 2, or uploading the precompoliled .fpg
>>> <https://github.com/casper-astro/tutorials_devel/blob/tutorials_update_2016/tut4/poco_wide_1kat.fpg>
>>> file onto my Roach2 (using either the python scripts given or simply by
>>> command-line uploading the .fpg using ipython). My error messages are
>>> attached in this Google Drive document.
>>> <https://docs.google.com/document/d/1RY5LSS7mRx3o2Zm6Gyy_a8jhEjJr2bM1k9CCN9ov0bw/edit?usp=sharing>
>>>
>>> For tutorials 1-3 I have had no trouble compiling the .slx files and
>>> upload the corresponding .fpg files to my Roach2.
>>>
>>> I've made sure in the .slx I cite above (for tutorial 4) that the
>>> XSG_core_config block does not have a broken link and that the settings are
>>> as follows:
>>>
>>>
>>>    - Hardware platform: Roach2:sx475t
>>>    - User IP clock source: adc0_clk
>>>    - User IP clock rate (MHz): 200, (and that the adc1 and adc0 are
>>>    correspondingly clocked to 800 MHz)
>>>    - Sample period: 1
>>>    - Synthesis tool: XST
>>>
>>> Any advice on how I can complete tutorial 4?
>>>
>>>
>>> Best,
>>>
>>> Alec
>>>
>>>
>>>
>>>
>>
>

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