Hi,
thanks for the code and getting in touch. Interestingly enough, this
topic was brought on IRC a few days ago as a means to make Migen easier
to use for Verilog designers. I like the idea and I'm looking forward to
integrating it into Migen.
There are however some problems with your code:
* "fhdl" is a library, stand-alone tools should reside elsewhere
* use double quotes (") for strings
* no CamelCase, for functions and variables, use underscores (CamelCase
is for class names only)
* indent with one tab (width 8)
* please write comments in English, in a concise way and without too
much distracting ASCII-art
Could you fix them and send a new patch?
Thanks,
Sébastien
On 07/15/2012 02:05 PM, Florent Kermarrec wrote:
Hi,
I am a Freelance Fpga Designer and found your Milkymist/Migen project
some months ago. I was working on a small tool to enhance Vhdl when I
discovered your work with Migen.
The goal of my tool was only to embedded Python code in Vhdl to generate
Roms, Coefficients, Register mapping, etc... I'm using it on some
designs, but I wanted to try Migen.
Before using migen on a complete design, I only wanted to try it in an
embedded way on the tedious or tricky part of my Verilog files.
That's why on a fork of your project
(https://github.com/Florent-Kermarrec/migen), I have added the
possibility to embedded Migen in Verilog files.
You only have to insert your migen code between tags ( [- , -] ) in your
Verilog and convert your .mig.v file to a .v file with the
migen.fhdl.embedded file. Object and variable are shared between all
embedded blocks.
That's all for my modest contribution, I hope you will find an interest
in it (or not... :) ) , and thanks for your great job!
Bye,
Florent
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