On 07/21/2012 02:28 PM, Florent Kermarrec wrote:
And if declared verilogs wire/regs are parsed by the Python script and
redefined automatically as migen vars and added to the ios lists
(block_ios), it can give something like:
[-
myfsm = FSM("FOO", "BAR")
myfsm.act(myfsm.FOO, control_word.eq(1), myfsm.next_state(myfsm.BAR))
myfsm.act(myfsm.BAR, control_word.eq(0), myfsm.next_state(myfsm.FOO))
print(verilog.convert(myfsm.get_fragment(),{block_ios},module=False))
-]
And if we define a verilog.convertblock function, we can also get rid
of the {block_ios},module=False) part and only have
print(verilog.convertblock(myfsm.get_fragment()))
That's the way to do it, I think.
Can you try it or tell me if I miss something?
Make sure that all Verilog object names are inserted in the namespace
first (even if they are not used in any Migen block), so that the
generated code is guaranteed not to use names that will clash with
existing objects.
Wire/reg will also be an issue that needs to be addressed. If the
Verilog code uses a "wire" that Migen assigns to in a "always" block,
you have a problem. You can sort it out it by:
* storing if a particular signal was declared as "wire" or "reg".
* in case of a mismatch, using an intermediate signal declared in the
way appropriate for the Migen assignment.
* inserting "glue" statements such "assign final_signal =
intermediate_signal;" or "always @(*) final_signal <= intermediate_signal;".
It's an ugly workaround for an ugly "feature" of Verilog...
Sébastien
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