On 07/19/2012 07:25 PM, Florent Kermarrec wrote:
it can be very simple to share Verilog macro/parameters with Migen
Blocks (if in the first time only non parameterized are supported):
- parse input file to find all verilog macros/parameters.
- don't replace it in Migen blocks but only declare it as Python Vars
in a buffer and execute this buffer.
When Migen blocks will be executed, Macro/Parameters will be known
as Python Vars ;), but maybe I misunderstood your idea??
Maybe you could create variables a cleaner way using the ast module and
friends (from the standard Python library) - have you looked at it?
One thing I don't quite understand is how you plan to access existing
Verilog objects (e.g. signals or input/output ports) from the embedded
Migen code... could you explain?
(The wire/reg idiosyncrasy will probably be particularly painful here...
phew)
Thanks,
Sébastien
PS: two more small coding style details: use spaces after commas, and
try to avoid aligning stuff (unless it makes the code really really
clearer), e.g.
foobar = 1
x = 2
should become:
foobar = 1
x = 2
The reason behind this is the spaces are a waste of time to maintain
when a variable name is changed, or if an assignment to a variable with
a longer name is added.
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