With the migen fsm example it gives:
[-
from migen.fhdl.structure import *
from migen.fhdl import verilog
from migen.corelogic.fsm import FSM
-]
module foo();
reg [2:0] control_word;
[... some datapath that is controlled with control_word ...]
[-
control_word = Signal(BV(2))
myfsm = FSM("FOO", "BAR")
myfsm.act(myfsm.FOO, control_word.eq(1), myfsm.next_state(myfsm.BAR))
myfsm.act(myfsm.BAR, control_word.eq(0), myfsm.next_state(myfsm.FOO))
print(verilog.convert(myfsm.get_fragment(),{control_word},module=False))
-]
endmodule
Internals reg that are declared in verilog are the ios of migen. With
module=False , the module interface is not generated.
And if declared verilogs wire/regs are parsed by the Python script and
redefined automatically as migen vars and added to the ios lists
(block_ios), it can give something like:
[-
myfsm = FSM("FOO", "BAR")
myfsm.act(myfsm.FOO, control_word.eq(1), myfsm.next_state(myfsm.BAR))
myfsm.act(myfsm.BAR, control_word.eq(0), myfsm.next_state(myfsm.FOO))
print(verilog.convert(myfsm.get_fragment(),{block_ios},module=False))
-]
And if we define a verilog.convertblock function, we can also get rid
of the {block_ios},module=False) part and only have
print(verilog.convertblock(myfsm.get_fragment()))
Can you try it or tell me if I miss something?
Thanks,
Florent
2012/7/21 Sébastien Bourdeauducq <sebastien.bourdeaud...@lekernel.net>
>
> On 07/20/2012 12:31 PM, Florent Kermarrec wrote:
>>
>> - I have to code an FSM, but keep fine control of others parts of my code,
>> let's use migen only for my FSM!
>
>
> Can you give an explicit example of how you'd do this?
>
> As I understand it, the Migen code for the FSM has to assign to external
> (non-Migen) Verilog signals at some point, and it's not clear to me how it
> can be done with your current code.
>
> e.g.
>
> module foo();
> reg [2:0] control_word;
> [... some datapath that is controlled with control_word ...]
> [-
> FSM in Migen that writes to control_word... but how do you do this?
> -]
> endmodule
>
> Thanks,
> Sébastien
>
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