Florent Kermarrec wrote: > When Migen blocks will be executed, Macro/Parameters will be known > as Python Vars ;), but maybe I misunderstood your idea??
Hmm, maybe :-) I think what you're saying is to pass Verilog parameters and macros through Migen, and then let the Verilog synthesis (after Migen) evaluate them. This would work in cases where Migen itself doesn't need to know these items. But what if also Migen needs to know their values ? > I don't really understand, if you mean that Migen code will be distributed > among blocks in mig.v files An example: let's say you want to make an arbiter. One way to do it would be to have a central arbiter object and let each user of it "connect" to the central object. In this case, each user would modify the state of the central object and the resulting Verilog Migen generates for each user would be affected by at least the presence of other users. A different approach would be to create the central object with the number of users and all other information known in advance and then pass the items the users need to connect to them individually. So depending on how this is done, Migen may have to have some way to pass data around in a way that's not strictly top-down. Disclaimer: I haven't had time to play with Migen yet, so these scenarios are somewhat hypothetical. - Werner _______________________________________________ http://lists.milkymist.org/listinfo.cgi/devel-milkymist.org IRC: #milkymist@Freenode
