S?bastien Bourdeauducq wrote: > Interestingly enough, this > topic was brought on IRC a few days ago as a means to make Migen > easier to use for Verilog designers. I like the idea [...]
Me too :-) I think this could do wonders for lowering the barrier of entry to using Migen. However, I wonder if such a simple inclusion is enough. E.g., wouldn't it be desirable to share Verilog macros and parameters ? This could be accomplished by first running things through a Verilog parser which would perform the macro expansion and substitute parameters, and only then doing what migen_embedded does. Perhaps one of the existing Free Verilog-eating tools could provide most of the infrastructure for this. Also, will instances of Migen working on the same shared structure(s) but invoked from separate .mig.v files be able to cooperate ? Particularly, will they generate the same sets of identifiers and such ? - Werner _______________________________________________ http://lists.milkymist.org/listinfo.cgi/devel-milkymist.org IRC: #milkymist@Freenode
