On 07/20/2012 12:31 PM, Florent Kermarrec wrote:
- I have to code an FSM, but keep fine control of others parts of my code,
let's use migen only for my FSM!
Can you give an explicit example of how you'd do this?
As I understand it, the Migen code for the FSM has to assign to external
(non-Migen) Verilog signals at some point, and it's not clear to me how
it can be done with your current code.
e.g.
module foo();
reg [2:0] control_word;
[... some datapath that is controlled with control_word ...]
[-
FSM in Migen that writes to control_word... but how do you do this?
-]
endmodule
Thanks,
Sébastien
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