Thanks Pallav. I am using Electric 8.08 and it is the same inverter
given in Help->Load Built-in Libraries->MIPS Cells. Pallv i have tried
Peferences -> Spice -> Write Transistor size in Units and it generates
the following netlist.
*** SPICE deck for cell inv{lay} from library mipscells
*** Created on Sat Dec 23, 2000 03:57:45
*** Last revised on Thu Feb 20, 2003 05:31:11
*** Written on Fri Feb 26, 2010 14:51:26 by Electric VLSI Design
System,
*version 8.08
*** Layout tech: mocmos, foundry MOSIS
*** UC SPICE *** , MIN_RESIST 4.0, MIN_CAPAC 0.1FF
.OPTIONS NOMOD NOPAGE
.options parhier=local
*** Lambda Conversion ***
.opt scale=0.3U
*** TOP LEVEL CELL: inv{lay}
mn...@0 y a gnd gnd N L=2 W=6 AS=46 AD=45 PS=38 PD=28
mp...@0 y a vdd vdd P L=2 W=12 AS=76 AD=45 PS=50 PD=28
.END
the sizes given in the netlist above donot match with that of the
layout using the simple formulas i.e AD = (Width(drain) *
Length(drain)), PD = 2(Width(drain) + Length(drain)). Length of drain/
Source = 5 in the layout. May be Steven M. Rubin can help!!
On Feb 26, 3:41 am, pallav <[email protected]> wrote:
> On Feb 25, 12:34 pm, mani <[email protected]> wrote:
>
>
>
>
>
> > Hi everyone
> > I have extracted the netlist of a simple mipscells inverter. Lambda =
> > 0.3u
>
> > *** SPICE deck for cell inv{lay} from library my_mipscells
> > *** Created on Sat Dec 23, 2000 03:57:45
> > *** Last revised on Thu Feb 20, 2003 05:31:11
> > *** Written on Wed Feb 24, 2010 23:25:11 by Electric VLSI Design
> > System,
> > *version 8.10
> > *** Layout tech: mocmos, foundry MOSIS
> > *** UC SPICE *** , MIN_RESIST 4.0, MIN_CAPAC 0.1FF
> > .OPTIONS NOMOD NOPAGE
> > .options parhier=local
> > *** TOP LEVEL CELL: inv{lay}
> > mn...@0 y a GND GND N L=0.6U W=1.8U AS=4.14P +AD=4.05P PS=11.4U
> > PD=8.4U
> > mp...@0 y a vdd vdd P L=0.6U W=3.6U AS=6.84P AD=4.05P +PS=15U PD=8.4U
> > .END
>
> > Length of source = Length of drain = 5lambda for both transistors. How
> > is it possible that NMOS and PMOS have same AD and PD as PMOS is twice
> > as large as NMOS? Can anyone knows the formula that Electric uses to
> > extract Area/perim of drain and source of transistors.
>
> > Nauman Ahmed
>
> It would help to post the circuit schematic/layout. Don't know what
> formula Electric uses but the standard ones are AD = (Width(drain) *
> Length(drain)). PD = 2(Width(drain) + Length(drain)). You can go to to
> Peferences -> Spice -> Write Transistor size in Units. Play around
> with that option and Electric should generate the sizes in terms of
> lambda as opposed to microns (depending upon the scale).- Hide quoted text -
>
> - Show quoted text -
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