At 09:24 AM 2/27/2010, you wrote:
I am starting to learn Electric and have managed to get an inverter, nand2
and and2 completed and simulated in LTSpice.
My questions are:
When making the basic components what is the best way to make them "standard
cells"? Do I just make sure that the Vdd and gnd are y units apart on each
component? Metal 2 for inputs and outputs?
Is there am automated way to get Electric to turn a schematic view into a
layout if it is designed using the standard cells in the library?
Electric has a number of ways to place and route standard cells. The
"Silicon compiler" tool takes a netlist (in either schematic or VHDL
form) and uses it to place-and-route a standard cell library. The
results are suboptimal because it is an old tool which assumes the
need for routing channels between the cells.
However, this tool does convert from a schematic to a layout using a
standard cell library. You could conceivably optimize the results by
unrouting the placed-and-routed cell to reduce all connections to a
"rats nest" of unrouted arcs, re-placing the cells with the Placement
tool (I recommend the "simulated annealing-2" algorithm) and then
re-routing the results with the "sea of gates" router.
As far as marking a library as "standard cells", this is actually
something that Electric can do, using the "Cell Properties"
dialog. But the attribution is mostly for documentation purposes.
-Steven Rubin
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