On Feb 27, 12:24 pm, "Edward Schram" <[email protected]> wrote: > I am starting to learn Electric and have managed to get an inverter, nand2 > and and2 completed and simulated in LTSpice. > > My questions are: > > When making the basic components what is the best way to make them "standard > cells"? Do I just make sure that the Vdd and gnd are y units apart on each > component? Metal 2 for inputs and outputs? > > Is there am automated way to get Electric to turn a schematic view into a > layout if it is designed using the standard cells in the library? > > Thanks for any help. > > Ed
The idea behind standard cells is that they are usually fixed in one dimension (commonly height). For example all the cells in a library can have a center-to-center (measured from center of power rail to gnd- rail) of say 50 or 60 lambda. If you design all your cells in this manner, then you can easily see that they can be abutted together into a row. Then wiring tracks can be laid out above/below power/gnd lines and connections can be easily made through vertically. There is no automated way to turn a simple schematic into a layout. For basic cells, you have to do the effort. Electric does have automatic placement/routing but that depends on already having the basic cells in place. Look at Lab 1 in 8-bit microprocessor labs in http://cmosedu.com/cmos1/electric/electric.htm to how to design a sample standard cell library. Make sure to align your I/O pins to gnd/ vdd substrate contacts. Also most standard cell libraries provide gates of different strengths (having the ability of driving different loads). For example, a inverter of strength 1 could be defined to drive a maximum load of X units or to drive another inverter. Then an inverter of strength 2 would be designed to drive twice as much load as that of an inverter with strength 1. Standard cells can be optimized for various parameters: area, delay, power, or a combination of those and other criteria (equal rise/fall times). Depends on what you want. Generally, a good way to design libraries is to size the transistors to give lowest "average" delay. Average delay is defined as rise (propagation delay + fall propagation delay)/2. How do you determine this ratio? You simulate the standard FO4 inverter circuit (a cascade of 5 inverters with each inverter being 4 times as big as its predecessor). The 3rd inverter is the device under measurement. You run Spice simulations to figure out the P/N ratio that gives the lowest average delay. For example, in the AMI 0.5 um technology process from MOSIS this is 1.4:1. If you had designed for equal rise/fall delays, you would have ended using a ratio of 2:1 which consumes more area. I'll upload the f04.zip file and you can go through it to see the sample circuit/optimization setup etc. Try to see if it runs in LTSpice. I used it on HSpice and it ran fine. -- You received this message because you are subscribed to the Google Groups "Electric VLSI Editor" group. To post to this group, send email to [email protected]. To unsubscribe from this group, send email to [email protected]. For more options, visit this group at http://groups.google.com/group/electricvlsi?hl=en.
