On 10/1/2011 6:05 PM, Kirk Wallace wrote: > On Sat, 2011-10-01 at 17:41 -0400, Kent A. Reed wrote: >> Jon and Kirk, both. >> >> I forgot to ask, what does lspci -v report for your SIIG and StarTech cards? >> >> Regards, >> Kent > My office examples are here: > http://wiki.linuxcnc.org/cgi-bin/emcinfo.pl?Startech (bottom) > http://wiki.linuxcnc.org/cgi-bin/emcinfo.pl?SIIG > > Thinking aloud, once the card is set to EPP mode, from that point on it > handles the hardware hand shake (from the EPP data register), which is > in firmware, so should not change from one PC to another. The PC end is > very basic, just place the out data on the data (base+4) register, then > read the in data from the data register. There doesn't seem to be much > room for something to go wrong, except in the NetMos case where the > firmware is broken, and is consistently broken. I have forced NetMos > cards into EPP and gotten the Pico comm test to mostly work (errors > every few cycles), but this doesn't seem to be something that works on > one PC and not another. The only thing that comes to mind is the timing > of when the one or anther PC writes and reads the EPP data register. > Maybe more here? (bottom): > http://www.beyondlogic.org/epp/epp.htm > Well, duh, when did you slip those pages into the Wiki? No, wait, don't tell me...I've already read their timestamps. It's amazing how much I can know about some parts of the Wiki and yet remain in abject ignorance of other parts:-(
I've been musing too about what could cause system-to-system variations in the behavior of these cards and I agree with your line of thinking. Unfortunately, now that I'm retired I don't have access to decent bench-test equipment, certainly not multichannel analyzers. I couldn't possibly measure the signal timings described in the IEEE 1284 standard. If I recall correctly, Jon has complained in the past about how loose the standard is in this regard, so even if timing isn't the only problem it is certainly one of them. Since different motherboards use different southbridge chipsets, it's also possible that a parallel-port adapter will see different timings for reasons over which we have absolutely no control. One can only hope the adapter card designer has taken this into account. Unfortunately, my guess would be that most PCI- and PCIe-parallel port adapters were designed based on information for cpu/southbridge sets that are several generations old. After all, they all come with drivers for Win95, WinNT, Win98, Win2K, as if these were current O/Ses! As long as we're thinking aloud, another possibility that comes to mind is that the effective signaling (voltage levels and current sourcing/sinking) capabilities of these cards could be different when placed on different motherboards due to different treatments of the voltage rails, different sizes and layouts of traces, etc. This could affect their performance as well as the performance of other boards that work against them. Again, I have no means to measure this. I'm getting depressed. Regards, Kent ------------------------------------------------------------------------------ All of the data generated in your IT infrastructure is seriously valuable. Why? It contains a definitive record of application performance, security threats, fraudulent activity, and more. Splunk takes this data and makes sense of it. IT sense. And common sense. http://p.sf.net/sfu/splunk-d2dcopy2 _______________________________________________ Emc-developers mailing list [email protected] https://lists.sourceforge.net/lists/listinfo/emc-developers
