Kent A. Reed wrote:
> On 10/1/2011 9:43 PM, Jon Elson wrote:
>   
>> Well, MUCH more interesting!  I hadn't tried EMC, as I couldn't get my
>> diagnostics to work.  But, I eventually tried EMC2, and it DID work!
>> After that, my diagnostic program ALSO worked.  So, apparently the
>> port management routine knows how to map to the ECR register
>> and select EPP mode.  I will tinker some more with this to see if I
>> can find the magic that lets the EMC driver do it right.
>>
>> Jon
>>
>>     
> Cool, Jon. Maddening, but cool.
>
> I asked Google about the OX9162 chip and came up with 
> http://pdf1.alldatasheet.com/datasheet-pdf/view/161706/OXFORD/OX9162.html
>
> This data sheet is dated 1999!
>
> The language concerning EPP mode-setting is exactly the same as I quoted 
> from a more recent chip's sheet, and your finding here seems to confirm 
> that everything is laid out is a reasonable fashion.
>
>   
Thanks for the datasheet.  Page 22 shows the standard register layout, 
with the ECR
at 402 above the base register, but clearly PCI PnP did NOT set up the 
board in
that configuration on the D525MW, it packed the address ranges together.
> I can't wait to hear what causes this peculiar 'it doesn't work, no, 
> wait, now it does' behavior.
>
> And now if we could just figure out Kirk's problem.
>   
I don't know whether other EMC2 drivers properly handle this arrangement 
of the
registers, or even if they are different in other systems.  I think the 
PnP enumeration
is done by the BIOS, not the OS.  I wasn't clear if this was an EPP 
problem or not.
I know that when I tried the D510MO mobo, it did not work on one of my 
boards,
and I had to make an update to the firmware.  So, there is a timing 
difference on
at least the D510MO.  Maybe the new SIIG boards also have different 
timing, which
could affect various EPP target board implementations.

Jon

Jon

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