OK, got this SIIG card figured out. It does have a non-standard
register setup.
EMC apparently knows how to deal with this, due to some code for par port
sharing built by Jeff Epler, that at least my driver uses. This is in
hal_parport.h,
the routine is hal_parport_get, that gets the addresses of the main register
group as well as the "high" register group.
Anyway, for this SIIG card, with the PCI PNP addresses as shown in my
lspci listing before :
Region 0: I/O ports at 1020 [size=8]
Region 1: I/O ports at 1028 [size=4]
Region 2: I/O ports at 1000 [size=32]
Region 0 is the main registers (data port, control port, EPP ports)
and 1028-102c are the "high" field. 102a is the ECR register, and if you
write 0x80 to this register it puts the board into EPP mode.
So, my driver already does this fine. But, my diagnostic doesn't do this.
My old pcisetup program assumes the high field is always 0x400 above
the data port, which is not true in this case. I made pcisetup work by
giving
it a different address, which was 102a - 402 = C28. So, I said
sudo ./pcisteup c28
knowing it would add 0x402 to the c28 to give the desired address of
102a.
I will have to figure out some better way of dealing with this for my
diagnostic program, the above trick is really gross and a bit dangerous.
But, it DOES make the port go to EPP mode from a user-mode program,
so it is useful for testing.
The new SIIG port really blasts along, too, it seems faster than the old
one. But, that may be a processor + PCI difference. The old board is in an
ancient 1 GHz Pentium 4 machine, the new one is in the D525MW Atom
board with a faster CPU and memory, and probably a faster PCI bridge, too.
Jon
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