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Re-factored patch to compile and work with Andreas's changes that were recently pushed. Will fix the python param code issue with the Checker for SE mode in another patch to come soon. - Geoffrey Blake On Jan. 25, 2012, 3:04 p.m., Geoffrey Blake wrote: > > ----------------------------------------------------------- > This is an automatically generated e-mail. To reply, visit: > http://reviews.gem5.org/r/910/ > ----------------------------------------------------------- > > (Updated Jan. 25, 2012, 3:04 p.m.) > > > Review request for Default, Ali Saidi, Gabe Black, Steve Reinhardt, and > Nathan Binkert. > > > Description > ------- > > CheckerCPU: Re-factor CheckerCPU to be compatible with current gem5 > > Brings the CheckerCPU back to a functioning state allowing FS and SE mode > checking of the O3CPU. These changes have only been tested with the > ARM ISA. Other ISAs will potentially require modification. > > > Diffs > ----- > > src/arch/arm/isa.cc 78b08f92c290 > src/arch/arm/isa/insts/m5ops.isa 78b08f92c290 > src/arch/arm/isa/insts/misc.isa 78b08f92c290 > src/arch/arm/table_walker.hh 78b08f92c290 > src/arch/arm/table_walker.cc 78b08f92c290 > src/arch/arm/tlb.hh 78b08f92c290 > src/arch/arm/tlb.cc 78b08f92c290 > src/arch/arm/utility.cc 78b08f92c290 > src/cpu/BaseCPU.py 78b08f92c290 > src/cpu/CheckerCPU.py 78b08f92c290 > src/cpu/DummyChecker.py PRE-CREATION > src/cpu/SConscript 78b08f92c290 > src/cpu/base.cc 78b08f92c290 > src/cpu/base_dyn_inst.hh 78b08f92c290 > src/cpu/base_dyn_inst_impl.hh 78b08f92c290 > src/cpu/checker/cpu.hh 78b08f92c290 > src/cpu/checker/cpu.cc 78b08f92c290 > src/cpu/checker/cpu_impl.hh 78b08f92c290 > src/cpu/checker/thread_context.hh 78b08f92c290 > src/cpu/dummy_checker_builder.cc PRE-CREATION > src/cpu/o3/O3CPU.py 78b08f92c290 > src/cpu/o3/O3Checker.py 78b08f92c290 > src/cpu/o3/checker_builder.cc 78b08f92c290 > src/cpu/o3/commit_impl.hh 78b08f92c290 > src/cpu/o3/cpu.hh 78b08f92c290 > src/cpu/o3/cpu.cc 78b08f92c290 > src/cpu/o3/dyn_inst_impl.hh 78b08f92c290 > src/cpu/o3/fetch_impl.hh 78b08f92c290 > src/cpu/o3/iew_impl.hh 78b08f92c290 > src/cpu/o3/lsq_unit_impl.hh 78b08f92c290 > src/cpu/o3/thread_context.hh 78b08f92c290 > src/cpu/o3/thread_context_impl.hh 78b08f92c290 > src/cpu/simple/BaseSimpleCPU.py 78b08f92c290 > src/cpu/simple/base.hh 78b08f92c290 > src/cpu/simple/base.cc 78b08f92c290 > src/cpu/simple_thread.hh 78b08f92c290 > src/cpu/thread_context.hh 78b08f92c290 > src/mem/bus.cc 78b08f92c290 > src/mem/cache/cache_impl.hh 78b08f92c290 > src/mem/packet.hh 78b08f92c290 > > Diff: http://reviews.gem5.org/r/910/diff/diff > > > Testing > ------- > > Successfully runs gzip in SE mode. Successfully boots linux kernel in FS > mode. Works with checkpoints and fast-forwarding. Testing with buggy O3CPUs > to test checker's capabilities. > > > Thanks, > > Geoffrey Blake > > _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
