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There are only a few small things to fix now, at least as far as I can see. src/arch/arm/isa.cc <http://reviews.gem5.org/r/910/#comment2497> This line is too long. src/arch/arm/isa.cc <http://reviews.gem5.org/r/910/#comment2498> So is this one. src/arch/arm/isa.cc <http://reviews.gem5.org/r/910/#comment2499> And this one. src/arch/arm/isa.cc <http://reviews.gem5.org/r/910/#comment2500> And this one. I'll stop pointing them out, but please fix throughout. src/cpu/checker/cpu.hh <http://reviews.gem5.org/r/910/#comment2501> It's not from you, but there's some whitespace at the end of this line. Since you're getting rid of commented out code, you could get rid of the whitespace too. src/cpu/checker/cpu.cc <http://reviews.gem5.org/r/910/#comment2502> This sentence seems to have dropped off half way there. - Gabe Black On Jan. 26, 2012, 7:10 a.m., Geoffrey Blake wrote: > > ----------------------------------------------------------- > This is an automatically generated e-mail. To reply, visit: > http://reviews.gem5.org/r/910/ > ----------------------------------------------------------- > > (Updated Jan. 26, 2012, 7:10 a.m.) > > > Review request for Default, Ali Saidi, Gabe Black, Steve Reinhardt, and > Nathan Binkert. > > > Description > ------- > > CheckerCPU: Re-factor CheckerCPU to be compatible with current gem5 > > Brings the CheckerCPU back to a functioning state allowing FS and SE mode > checking of the O3CPU. These changes have only been tested with the > ARM ISA. Other ISAs will potentially require modification. > > > Diffs > ----- > > src/arch/arm/isa.cc 78b08f92c290 > src/arch/arm/isa/insts/m5ops.isa 78b08f92c290 > src/arch/arm/isa/insts/misc.isa 78b08f92c290 > src/arch/arm/table_walker.hh 78b08f92c290 > src/arch/arm/table_walker.cc 78b08f92c290 > src/arch/arm/tlb.hh 78b08f92c290 > src/arch/arm/tlb.cc 78b08f92c290 > src/arch/arm/utility.cc 78b08f92c290 > src/cpu/BaseCPU.py 78b08f92c290 > src/cpu/CheckerCPU.py 78b08f92c290 > src/cpu/DummyChecker.py PRE-CREATION > src/cpu/SConscript 78b08f92c290 > src/cpu/base.cc 78b08f92c290 > src/cpu/base_dyn_inst.hh 78b08f92c290 > src/cpu/base_dyn_inst_impl.hh 78b08f92c290 > src/cpu/checker/cpu.hh 78b08f92c290 > src/cpu/checker/cpu.cc 78b08f92c290 > src/cpu/checker/cpu_impl.hh 78b08f92c290 > src/cpu/checker/thread_context.hh 78b08f92c290 > src/cpu/dummy_checker_builder.cc PRE-CREATION > src/cpu/o3/O3CPU.py 78b08f92c290 > src/cpu/o3/O3Checker.py 78b08f92c290 > src/cpu/o3/checker_builder.cc 78b08f92c290 > src/cpu/o3/commit_impl.hh 78b08f92c290 > src/cpu/o3/cpu.hh 78b08f92c290 > src/cpu/o3/cpu.cc 78b08f92c290 > src/cpu/o3/dyn_inst_impl.hh 78b08f92c290 > src/cpu/o3/fetch_impl.hh 78b08f92c290 > src/cpu/o3/iew_impl.hh 78b08f92c290 > src/cpu/o3/lsq_unit_impl.hh 78b08f92c290 > src/cpu/o3/thread_context.hh 78b08f92c290 > src/cpu/o3/thread_context_impl.hh 78b08f92c290 > src/cpu/simple/BaseSimpleCPU.py 78b08f92c290 > src/cpu/simple/base.hh 78b08f92c290 > src/cpu/simple/base.cc 78b08f92c290 > src/cpu/simple_thread.hh 78b08f92c290 > src/cpu/thread_context.hh 78b08f92c290 > src/mem/bus.cc 78b08f92c290 > > Diff: http://reviews.gem5.org/r/910/diff/diff > > > Testing > ------- > > Successfully runs gzip in SE mode. Successfully boots linux kernel in FS > mode. Works with checkpoints and fast-forwarding. Testing with buggy O3CPUs > to test checker's capabilities. > > > Thanks, > > Geoffrey Blake > > _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
