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configs/common/Simulation.py
<http://reviews.gem5.org/r/1089/#comment2836>

    Will remove this is next change ...



src/cpu/inorder/inorder_dyn_inst.hh
<http://reviews.gem5.org/r/1089/#comment2838>

    This code compiles and runs for ALPHA-Hello World now.
    
    It needs to be run through the regressions before an update as well as get 
an update from the reviewers.
    
    Next up is adding micro-ops to InOrder and then...finally...it will be 
ARM-Compatible.



src/cpu/translation.hh
<http://reviews.gem5.org/r/1089/#comment2837>

    Both ITB/DTB are using this so I am planning on deleting this assert...


- Korey Sewell


On April 4, 2012, 11:29 a.m., Korey Sewell wrote:
> 
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> This is an automatically generated e-mail. To reply, visit:
> http://reviews.gem5.org/r/1089/
> -----------------------------------------------------------
> 
> (Updated April 4, 2012, 11:29 a.m.)
> 
> 
> Review request for Default.
> 
> 
> Description
> -------
> 
> inorder: add timing translation
> This is Erik Tomusk's patch to add timing translation to InOrder. It's the 
> next step
> in getting InOrder to work for ARM.
> 
> 
> Diffs
> -----
> 
>   configs/common/Simulation.py 97f06a79b6f5 
>   src/cpu/inorder/SConscript 97f06a79b6f5 
>   src/cpu/inorder/cpu.hh 97f06a79b6f5 
>   src/cpu/inorder/cpu.cc 97f06a79b6f5 
>   src/cpu/inorder/inorder_dyn_inst.hh 97f06a79b6f5 
>   src/cpu/inorder/resources/cache_unit.hh 97f06a79b6f5 
>   src/cpu/inorder/resources/cache_unit.cc 97f06a79b6f5 
>   src/cpu/inorder/resources/fetch_unit.hh 97f06a79b6f5 
>   src/cpu/inorder/resources/fetch_unit.cc 97f06a79b6f5 
>   src/cpu/inorder/resources/graduation_unit.cc 97f06a79b6f5 
>   src/cpu/inorder/resources/inorder_translation.hh PRE-CREATION 
>   src/cpu/inorder/resources/inorder_translation.cc PRE-CREATION 
>   src/cpu/translation.hh 97f06a79b6f5 
> 
> Diff: http://reviews.gem5.org/r/1089/diff/
> 
> 
> Testing
> -------
> 
> This is not fully tested yet but a work in progress.
> 
> 
> Thanks,
> 
> Korey Sewell
> 
>

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